34063

Description
The MC34063A Series is a monolithic control circuit containing the primary functions required for DC-to-DC converters.
These devices consist of an internal temperature compensated reference, comparator, controlled duty cycle oscillator
with an active current limit circuit, driver and high current output switch. This series was specifically designed to be
incorporated in Step-Down and Step-Up and Voltage-Inverting applications with a minimum number of external
components.

Features
• Operation from 3.0 V to 40 V Input
• Low Standby Current
• Current Limiting
• Output Switch Current to 1.5 A
• Output Voltage Adjustable
• Frequency Operation to 100 kHz
• Precision 2% Reference

Plastic Package Pin Connections

Internal Block Digram

Driver 8 1 Switch
Collector
Collector
S Q Q2

R Q1
Ipk 7
Sense
100
Ipk Switch
CT 2
Oscillator Emitter
3 Timing
Capacitor
Comparator
6
VCC 1.25 V
Comparator Reference
Inverting
Input 4
5 Gnd

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Absolute Maximum Ratings
Symbol Parameter Maximum Units
VCC Power Supply Voltage 40 Vdc
VIR Comparator Input Voltage Range -0.3 to +40 Vdc
VC(switch) Switch Collector Voltage 40 Vdc
VE(switch) Switch Emitter Voltage (V PIN1 = 40 V) 40 Vdc
VCE(switch) Switch Collector to Emitter Voltage 40 Vdc
VC(driver) Driver Collector Voltage 40 Vdc
IC(driver) Driver Collector Current (Note 1) 100 mA
ISW Switch Current 1.5 A
TJ Operating Junction Temperature +150 °C
TA Operating Ambient Temperature Range 0 to +70 °C
Tstg Storage Temperature Range -65 to +150 °C

Electrical Characteristics
(Vcc=5.0V, Ta=Tlow to Thigh , unless otherwise
specified)
Characteristics Symbol Min Typ Max Units
OSCILLATOR
Frequency (Vpin5 = 0V, CT = 1.0 nF, TA = 25°C) fOSC 24 33 42 kHz
Charge Current(VCC = 5.0V to 40V, TA = 25°C) Ichg 24 35 42 µA
Discharge Current (V CC = 5.0V to 40V, TA = 25°C) Idischg 140 220 260 µA
Discharge to Charge Current Ratio (Pin 7 to V CC, TA = 25°C) Idischg / 5.2 6.5 7.5 –
Ichg
Current Limit Sense Voltage (I chg = Idischg, TA = 25°C) Vipk(sence) 250 300 350 mV
OUTPUT SWITCH (NOTE 2)
Saturation Voltage, Darlington Connection (I SW = 1.0 A, Pins 1, 8 connected) VCE(sat) – 1.0 1.3 V
Saturation Voltage, Darlington Connection (I SW = 1.0 A, Rpin 8 = 82Ω to VCC , Forced β ≅ 20) VCE(sat) – 0.45 0.7 V
DC Current Gain (ISW = 1.0 A, VCE = 5.0 V, TA = 25°C) hFE 50 75 – –
Collector Off-State Current (V CE = 40 V) IC(off) – 40 100 µA
COMPARATOR
Threshold Voltage Vth V
(TA=25°C) 1.225 1.25 1.275
(TA =Tlow to Thigh) 1.21 – 1.29
Threshold Voltage Line Regulation Regline – 1.4 5.0 mV
(Vcc=3.0 V to 40 V)
Input Bias Current IIB – -20 -400 nA
(Vin=0 V)
TOTAL DEVICE
Supply Current (Vcc = 5.0 V to 40 V, CT = 1.0 nF, Pin 7 = V CC, Vpin 5 > Vth, Pin 2 = ICC – – 4.0 mA
Gnd, remaining pins open)

NOTES : [Link] package power dissipation limits must be observed.

[Link] duty cycle pulse techniques are used during test to maintain junction temperature
as close to ambient temperature as possible

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Typical Performance Characteristics
Figure 1. Output Switch On-Off Time versus
Oscillator Timing Capacitor Figure 2. Timing Capacitor Waveform

Figure 3. Emitter Follower Configuration Output Figure 4. Common Emitter Configuration

Saturation Voltage versus Emitter Current Output Switch Saturation Voltage
versus
Collector Current

Figure 5. Current Limit Sense Voltage Figure 6. Standby Supply Current versus
versus Temperature Supply Voltage

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Typical Applications Circuit

Figure 1. Step-Up Converte .r

Note: R to 0 for constant Vin

Figure 2a. External NPN Switch. Figure 2b. External NPN Saturated Switch.

Figure 2. External Current Boost Connections for I eak Greater than

P 1.5 .A

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 34063

Figure 3. Step-Down Converte .r

Figure 4a. External NPN Switch. Figure 4b. External PNP Suturated Switch.

Figure 4. External Current Boost Connections for I eak Greater than

P 1.5 .A

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Figure 5. Voltage Inverting Converte .r

Figure 6a. External NPN Switch. Figure 6b. External PNP Saturated Switch.

Figure 6. External Current Boost Connections for I eak Greater than

P 1.5 .A

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Design Formula Table
Calculation Step-Up Step-Down Voltage-Inverting

ton/toff out + − V
in + VF out+VF
V V −Vsat − V +V
in (min) in (min)
in sat
− sat V V outV V 1
(ton+toff)max 1 1 f
min

CT f -5
4.0 x 10 ton f -5
4.0x10 ton 4.0 x 10-5
lpk(switch) t    
2 I + 1 2I out(max) 2I  + 1
(max)

 on  ont 

RSC 0.3/lpk(switch) 0.3/lpk(switch) 0.3/lpk(switch)
L(min) − Vin(min) V −
 V −sat  ×t Vin (min) V sat V   t on(max)
  out 
in sat
I pk ( switchV) 
on (max)
  × on (max)  I 
 
I pk ( switch )
  pk ( switch) 

CO I out ton I pk ( switch ) + ) tI

9 ( t 8V t 9
Vripple ( pp ) ripple ( pp ) Vripple ( pp )

TERMS AND DEFINITIONS

Vsat - Saturation voltage of the output switch.
VF - Forward voltage drop of the output rectifier.
The following power supply characteristics must be chosen:
 R
Vout = .1 25 1+ 
 R
1 
Vin - Nominal input voltage.
Vout - Desired output voltage,
Iout - Desired output current.
fmin - Minimum desired output switching frequency at the selected values of V in and IO.
Vripple(p-p) –Desired peack-to-peack output ripple voltage. In practice, the calculated capacitor value will need to be increased due to its
equivalent series resistance and board layout. The ripple voltage should be kept to a low value since it will directly affect the
line and load regulation.

Ordering Information

O RDERING NUM BER P ACK AGE M ARKING

34063A SOP-8 /DIP-8 MC34063A

Address : 6A06--6A07
Rm 6A07,Changyin Office Building ,No.88,Yong Ding Road,Hai Dian District ,Beijing
Postalcode:100039
Tel: 86-010-58895780 / 81 / 82 / 83 / 84 Fax : 010-58895793
Http://[Link]
Email:sales@[Link]
REV No:01-060810

BEIJING ESTEK ELECTRONICS CO.,LTD