TOPIC 6

MEMORY AND I/O INTERFACING

MEMORY INTERFACING
i. External ROM (program memory) Interfacing

P1 P0 D0-D7

EA A0
| ROM/
8051 LATCH A7 EPROM
ALE
clock
A8 Address
P3 | lines
A15
PSEN OE

FIGURE 1 INTERFACING OF ROM/EPROM TO µC 8051.

above figure shows how to access or interface ROM to 8051.

port 0 is used as multiplexed data & address lines.
it gives lower order (A7-A0) 8 bit address in initial T cycle & higher
order (A8-A15) used as data bus.
8 bit address is latched using external latch & ALE signal from 8051.
port 2 provides higher order (A15-A8) 8 bit address.
PSEN is used to activate the output enable signal of external
ROM/EPROM.

ii. External RAM (data memory) Interfacing

P1 D0 data
P0 | lines
D7
RAM
8051 LATCH A0
ALE clock |
A7 address
lines

RD P3 P2

Chapter: 6 MEMORY AND I/O INTERFACING

WR WR OE

FIGURE 2 INTERFACING OF RAM(DATA MEMORY) TO µC 8051.

above figure shows how to connect or interface external RAM(data

memory) to 8051.
port 0 is used as multiplexed data & address lines.
address lines are decoded using external latch & ALE signal from 8051
to provide lower order (A7-A0) address lines.
port 2 gives higher order address lines.
RD & WR signals from 8051 selects the memory read & memory write
operations respectively.
RD & WR signals: generally P3.6 & P3.7 pins of port 3 are used
to generate meamory read and memory write
signals.
remaining pins of port 3 i.e. P3.0-P3.5 can be used for other
functions.

1
LINEAR AND ABSOLUTE DECODING
i. Absolute Decoding
all higher address lines : decoded to select memory chip for
specific logic levels.
for other logic levels memory chip is disabled.
generally used in large memory systems.
figure below shows memory interfacing using absolute decoding.

Vss
P0.7 D7-D0
EA |
P0.0
74LS373 A7-A0

ALE G OC 16k x 8
8051 RAM
P2.0
| A8-A13
P2.5
P2.6
P2.7 CS

PSEN
P3.6 WR

P3.7 RD

FIGURE 3 MEMORY (RAM) INTERFACING USING ABSOLUTE DECODING.

ii. Linear Decoding (Partial Decoding)

for small systems : individual higher order address lines used
to select memory chip.

replacing the hardware by

decoding logic.

reducing the cost of decoding, drawback is- multiple addresses.

as shown in figure below, A14 line is directly connected to chip
select line, A15 line not connected anywhere, kept open.
so, status of A15- not considered for generation of chip select
signal.

Chapter: 6 MEMORY AND I/O INTERFACING

Vss
P0.7 D7-D0
EA |
P0.0
74LS373 A7-A0

ALE G OC 16 x 8
8051 RAM
P2.0
| A8-A13
P2.5
P2.6 CS (A14)
P2.7 A15

PSEN
P3.6 WR

P3.7 RD

FIGURE 4 MEMORY (RAM) INTERFACING USING LINEAR DECODING.

2
 Address Mapping(Memory Map)
i. Absolute Decoding
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
ii. Linear Decoding
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end x 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
Comparison between Full address(Absolute) & Partial address (Linear) Decoding.
-----------------------------------------------------------------------
Full Adress(Absolute) | Partial Address(Linear
Decoding | Decoding
-----------------------------------------------------------------------
i. all higher address lines are |i. few or individual address lines
decoded to select memory or | are decoded to select memory or
I/O device. | I/O device.
ii. more hardware : decoding |ii. less hardware : decoding logic.
logic. | (sometimes none.)
iii. decoding circuit : higher |iii. decoding circuit : less cost.
cost. |
iv. No multiple addresses. |iv. multiple addresses possible.
v. used in large systems. |v. used in small systems.
-----------------------------------------------------------------------
Solved Examples:
Example 1: Design a µController system using [Link] the external RAM
of size 16k x 8.
Solution: Given, Memory size: 16k
that means we require 2n=16k :: n address lines
here n=14 :: A0 to A13 address lines are required.
A14 and A15 are connected through OR gate to CS pin of external RAM.
when A14 and A15 both are low (logic ‘0’), external data memory(RAM) is
selected.
Address Decoding(Memory Map)for 16k x 8 RAM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.

Chapter: 6 MEMORY AND I/O INTERFACING

starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
Vss
P0.7 D7-D0
EA |
P0.0
74LS373 A7-A0

ALE G OC 16k x 8
8051 RAM
P2.0
| A8-A13
P2.5
P2.6
P2.7 CS

PSEN
P3.6 WR

P3.7 RD

FIGURE 5 16K X 8 MEMORY (RAM) INTERFACING TO µC 8051.

3
Example 2: Design a µController system using [Link] the external ROM of
size 4k x 8.
Solution: Given, Memory size: 4k
that means we require 2n=4k :: n address lines
here n=12 :: A0 to A11 address lines are required.
remaining lines A0, A0, A0, A0 & PSEN are connected though OR gate to CS &
RD of external ROM.
when A0 to A0 are low (logic ‘0’), only then external ROM is selected.
Address Decoding(Memory Map)for 4k x 8 RAM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0FFFH
Vss
P0.7 D7-D0
EA |
P0.0
74LS373 A7-A0

ALE G OC 4k x 8
8051 ROM
P2.0
| A8-A11
P2.5
P2.6
P2.7 WR

PSEN CS
P3.6

P3.7 RD

FIGURE 6 4K X 8 MEMORY (ROM) INTERFACING TO µC 8051.

Example 3: Design a µController system using 8051, 16k bytes of ROM & 32k
bytes of RAM. Interface the memory such that starting address for ROM is
0000H & RAM is 8000H.
Solution: Given, Memory size- ROM : 16k
that means we require 2n=16k :: n address lines
here n=14 :: A0 to A13 address lines are required.

Chapter: 6 MEMORY AND I/O INTERFACING

A14,A15,PSEN ORed CS

when low – ROM is selected.

Memory size- RAM :32k

that means we require 2n=32k :: n address lines
here n=15 :: A0 to A15 address lines are required.

A15 inverted(NOT Gate) CS

when high- RAM is selected.

PSEN is used as chip select pin ROM.

RD is used as read control signal pin. for RAM
WR is used as write control signal pin. selection.

4
 Address Decoding(Memory Map)for 16k x 8 ROM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3FFFH
Address Decoding(Memory Map)for 32k x 8 RAM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8000H
end 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH
Vcc Vcc
Vss
P0.7 D7-D0 D7-D0
EA |
P0.0
74LS373 A7-A0 A7-A0

ALE G OC 16k x 8 32k x 8

8051 ROM RAM
P2.0
| A8-A13 A8-A13
P2.5
P2.6 To
P2.7 CS CS(A15)
P2.7
To
PSEN P2.6 A14
P3.6 RD
RD WR
P3.7

FIGURE 7 16K X 8 ROM AND 32K X 8 RAM INTERFACING TO µC 8051.

Example 4:Design a µController system using 8051, 8k bytes of program ROM &
8k bytes of data RAM. Interface the memory such that starting address for
ROM is 0000H & RAM is E000H.
Solution: Given, Memory size- ROM : 8k
that means we require 2n=8k :: n address lines
here n=13 :: A0 to A12 address lines are required.

Chapter: 6 MEMORY AND I/O INTERFACING

A13,A14,A15,PSEN ORed CS

when low – program ROM is selected.

Memory size- RAM :8k

that means we require 2n=8k :: n address lines
here n=13 :: A0 to A12 address lines are required.

A13,A14,A15 NANDed CS

when high- data RAM is selected.

PSEN is used as chip select pin ROM.

RD is used as read control signal pin. for RAM
WR is used as write control signal pin. selection.

5
 Address Decoding(Memory Map)for 8k x 8 ROM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0000H
end 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1FFFH
Address Decoding(Memory Map)for 8k x 8 RAM.
Address A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 HEX
adrs.
starting 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 E000H
end 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 FFFFH
Vcc Vcc
Vss
P0.7 D7-D0 D7-D0
EA |
P0.0
74LS373 A7-A0 A7-A0

ALE G OC 8k x 8 8k x 8
8051 ROM RAM
P2.0
| A8-A12 A8-A12
P2.4 To
P2.7
P2.5
To
P2.6 CS P2.6 CS
P2.7 To
PSEN P2.5

P3.6 RD
WR RD
P3.7

FIGURE 8 8K X 8 ROM AND 8K X 8 RAM INTERFACING TO µC 8051.

Chapter: 6 MEMORY AND I/O INTERFACING

6
 I/O interfacing
1. 8255 Programmable Peripheral Interface-
Features:
* widely used programmable parallel I/O device.
* TTL compatible & compatible with all Intel & most other processors.
* can be programmed to transfer data- simple I/O, Interrupt I/O.
* three 8 bit ports- port A, port B and port C.
* bit set/reset mode: setting/resetting of individual bits of port c.
* can operate in I/O modes-
i. Mode 0
ii. Mode 1
iii. Mode 2
port A programmed as input or output : with or without handshaking
signals.
or as a bidirectional
port.

port B programmed as input or output : with or without handshaking

signals.
port C divided in two parts : port C upper port C lower

(PC4-PC7) (PC0-PC3)

can be programmed as an input or output port.

can be individually set/reset to generate control signals.

40 pin DIP chip.
8255 Block Diagram: PA
Group A
Group A
Port A
Control
(8)
PA7-PA0

PC
Bidirectional Group A
data bus
Data Port C PC7-PC4
Bus upper(4)
D7-D0 buffer

Chapter: 6 MEMORY AND I/O INTERFACING

I/O
ports
PC
Group B
Port C PC3-PC0
RD lower(4)

WR
Read/
A0 Write
control
A1 logic PB
Group B
Reset Group B
Control Port B PB7-PB0
(8)

CS

FIGURE 9 BLOCK DIAGRAM OF 8255A.

7
 above figure shows internal block diagram of 8255.
consist of data bus buffer, control logic- group A and group B.
DATA BUS BUFFERS-
tri-state bidirectional buffer.
interfaces internal databus of 8255 to the system databus.
i/p or o/p instructions executed by the CPU either read data from or write
data into buffer.
data from & to CPU always passed through buffer.
CONTROL LOGIC-
accepts control bus signals, i/ps from address bus & issues command to the
individual group control blocks.(Group A & Group B control)
it issues appropriate enabling signals to the access required data/control
words or status words.
following are the inputs for the control logic section,
Group A and Group B control-
receives control words from CPU & issues appropriate commands to
ports associated with it.
Group A controls the Port A and Port C upper part i.e. PC7-PC4.
Group B controls the Port B and Port C lower part i.e. PC3-PC0.
Port A-8 bit latched inputs.
8 bit latched & buffered output.
can be programmed in 3 modes viz. mode 0, mode 1 and mode 2.
Port B-8 bit data input buffer.
8 bit data I/O latch/buffer.
can be programmed in mode 0 & mode 1.
Port C-8 bit unlatched input buffer.
8 bit output latch/buffer.
divide into two parts- each one used as control signal for port A
& B in handshake mode.
can be programmed for bit set/reset operation.
8255 PIN DIAGRAM

PA3 1 40 PA4
2 39
PA2 PA5
PA1 3 38 PA6
PA0 4 37 PA7
RD 5 36 WR

Chapter: 6 MEMORY AND I/O INTERFACING

CS 6 35 RESET

GND 7 34 D0
A1 8 33 D1
A0 9 32 D2
PC7 10 31 D3
PC6 11 30 D4
PC5 12 8255 29 D5
PC4 13 28 D6
PC0 14 27 D7
PC1 15 26 Vcc
PC2 16 25 PB7
PC3 17 24 PB6
PB0 18 23 PB5
PB1 19 22 PB4
PB2 20 21 PB3
FIGURE 9 PIN DIAGRAM OF 8255.
8
figure above shows the pin diagram of 8255.
PA0-PA7 (Port A)
8 bit bidirectional I/O pins.
to send/receive data to & from I/O devices.
functions as 8 bit data i/p buffer, 8 bit data o/p buffer/latch.
D0-D7 (Data Bus)
8 bit bidirectional, tri-state data bus.
connected to system data bus.
used to transfer data & control word from processor to 8255 or to
receive data/status word from 8255 to processor.
PB0-PB7 (Port B)
8 bit bidirectional I/O pins.
to send/receive data to & from I/O devices.
functions as 8 bit data i/p buffer, 8 bit data o/p buffer/latch.
PC0-PC7 (Port C)
8 bit bidirectional I/O pins.

PC U PC L
(PC7-PC4) (PC3-PC0)
for handshaking purpose.
to send receive data in & out.
RD (Read)
when low, CPU can read the data in port or status word through
buffer.
WR (Write)
when low, CPU can write the data on ports or in control registers
through buffers.
CS (Chip Select)
when low, chip is activated/enabled for data transfer between CPU
and 8255.
RESET
active high input to reset 8255.
when RESET= 1 :: control register is cleared & all ports are set
to input mode.
usually RESET OUT from processor is used to reset 8255.
A0 & A1 selects specific ports & control register.
-----------------------------------------------------------------

Chapter: 6 MEMORY AND I/O INTERFACING

A1 | A0 | RD | WR | CS | OPERATION
-----------------------------------------------------------------
Input (read) operation
0 | 0 | 0 | 1 | 0 | port A to data bus.
0 | 1 | 0 | 1 | 0 | port B to data Bus.
1 | 0 | 0 | 1 | 0 | port C to data bus.
-----------------------------------------------------------------
Output (write) operation
0 | 0 | 1 | 0 | 0 | data bus to port A.
0 | 1 | 1 | 0 | 0 | data bus to port B.
1 | 0 | 1 | 0 | 0 | data bus to port C.
1 | 1 | 1 | 0 | 0 | data bus to control register.
-----------------------------------------------------------------
Disable Function
X | X | X | X | 1 | data bus tri-stated.
1 | 1 | 0 | 1 | 0 | illegal condition.
X | X | 1 | 1 | 0 | data bus tri-stated.
-----------------------------------------------------------------

9
Operating Modes
Bit Set Reset Mode (BSR mode)
individual bits of port C can be set or reset by sending out single OUT
instruction to the control register, whenever port C is used for
control/status operation.
I/O modes-
1. Mode 0: simple Input/ Output
Port A & B :: two simple 8 bit I/O ports.
Port C :: two 4 bit ports.
port(any) can be programmed to function as simply input or output port.
I/O features are as follows-
i. outputs are latched.
ii. inputs are buffered, not latched.
iii. ports don’t have handshake or interrupt capability.
2. Mode 1: Input/ Output with handshake.
i/p or o/p data transfer is controlled by handshaking signals.

to transfer data between devices whose

data transfer speeds are not same.

Features-
i. Port A & B- 8 bit I/O ports :: either input or output port.
ii. Port C-3 lines for handshaking signals &
2 lines for I/O functions.
iii. input and output data are latched.
iv. interrupt logic is supported.
3. Mode 2: Bidirectional I/O data transfer.
allows bidirectional data transfer.

make use of handshaking signals

(PC3-PC7) for Port A only.

both inputs and outputs are latched.

when peripheral request processor, data is sent from CPU through Port A
appears on bus.
Port C lines are used for simple I/O functions.
Port B- programmed in Mode 0 or Mode 1.

PC0-PC2 used for handshaking.

CONTROL WORDS FORMATS Chapter: 6 MEMORY AND I/O INTERFACING

8255 PPI got inbuilt control registers.

also called as control or

command word register.

loaded 8 bit pattern decides I/O functions of each port & mode of
operation of port.
1. Bit set/ reset mode:
bit set/ reset control word format is shown below.
BSR word – written for each bit that is to be set or reset.
also used for enabling/ disabling interrupt signals by setting/
resetting the associated bits of interrupts.

10
 D7 D6 D5 D4 D3 D2 D1 D0

0 for X X X 0 0 0 PC0 in BSR Mode

BSR mode. 0 0 1 PC1 1 - set
0 1 0 PC2 0 - reset
0 1 1 PC3
1 0 0 PC4
1 0 1 PC5
1 1 0 PC6
1 1 1 PC7
FIGURE 10 BSR CONTROL WORD FORMAT.

2. for I/O mode:

D7 D6 D5 D4 D3 D2 D1 D0

1 for Port A mode seln Group B

i/o mode mode selection 1- i/p 0- mode 0 PCL
0 0 mode 0 0- o/p 1- mode 1 1- i/p
0 1 mode 1 Group A Port B 0- o/p
1 x mode 2 PCU 1- i/p
1- i/p 0- o/p
0- o/
FIGURE 11 BSR CONTROL WORD FORMAT FOR I/O MODE.

I/O PORT EXPANSION USING 8255

P2.7 CHIP
SELECT CS
|
P2.0 LOGIC PA
PB
PC
ALE
8255
8051 G

Chapter: 6 MEMORY AND I/O INTERFACING

AD7
P0.7 A1 A1
| 74LS373
A0
A0
P0.0 AD0 OC
RD WR D7
D7 RES

D0 WR RD
D0

FIGURE 12 8051 CONNECTION TO THE 8255.

as seen earlier, for external memory interfacing to 8051 port 0 & port
2 are used as multiplexed address/data bus & higher order data bus
respectively.
if circuit needs on-chip peripherals(e.g. serial I/O & interrupts) then
only port is available for I/O.

11
 in such situation, I/O expansions is necessary & it is achieved by
using 8255.
data bus of 8255 is connected to the port 0.
address line A0 & A1, after latches are connected to A0 & A1 of the
8255.
INTERFACING TO µCONTROLLER 8051
1. Interfacing Push button switches(Keys & LEDs)
Vcc

pull up
resistors
P1.0
PORT 1 P1.1
P1.2
P1.3
P1.4
8051
P1.5
P1.6
P1.7

FIGURE 13-A 8051 PORT 1 CONNECTION TO SWITCHES(KEYS).

AS shown in above figure 13-A 8 push buttons are connected to port 1.

Vcc

P0.0

P0.1

Chapter: 6 MEMORY AND I/O INTERFACING

PORT 0 P0.2

P0.3

P0.4

8051 P0.5

P0.6

P0.7

FIGURE 13-B 8051 PORT 0 CONNECTION TO LEDS.

as shown in above figure 13-B 8 LEDs (in common anode configuration)

are connected to port 0.
PORT 1- input port
PORT 0- output port
12
 when push button pressed, bounce(make & break) take place ... before
firm contact.
soln to this is wait for 10- 20 sec till key is settled & then key is
checked again.

PROGRAMMING STEPS
i. check if key is pressed.
ii. wait for key debounce.
iii. identify the key in binary format.
iv. display the key condition using 8 LEDs.
---------------------------------------------------------------------
SAMPLE PROGRAM: key_led.asm
labels mnemonics comments
---------------------------------------------------------------------
mov p1, #0ffh ;make p1 as input port.
start: MOV A, P1 ;read the data from P1.
cjne a, #0ffh, check ;key pressed- branched to check1.
sjmp start ;branch to start.
check: acall delay ;call delay.
mov a, p1 ;read data from port 1.
cpl a ;complement a.
mov p0, a ;send data to LED.
ajmp start ;branch to start.
delay: mov r6, #20h ;delay routine. load r6 with 20h.
next: mov r7, #0ffh ;load r6 with 20h.
here: djnz r7, here ;wait until r7 becomes 0.
djnz r6, next ;wait until r6 becomes 0.
ret ;return to next instruction.
end ;end address of program.
-----------------------------------------------------------------------
2. Interfacing Seven Segment Display

100Ω a a
P0.7
100Ω b b
P0.6
100Ω c
P0.5 c

PORT 0

P0.0
74ALS244

100Ω h
8 8 h

Chapter: 6 MEMORY AND I/O INTERFACING

PORT 2
P2.4 1-2
DECODER
1k

1k . .
FIGURE 14 8051 PORT 0 CONNECTION TO 7 SEGMENT DISPLAY.

3. Interfacing Of Stepper Motor

stepper motor: stepping or step motor

rotates in fixed steps. 13

 if rotor rotates 90º in each step(from one pole segment to another)-
full step motor.

Coil 1
ROTOR

ROTOR
Coil 4 Coil 2

Coil 3
STATOR STATOR
(14-b 1)
(14-a)

FIGURE 14-a INSIGHT OF STEPPER MOTOR.

Coil 1
Coil 1

Coil 1
Coil 4 Coil 2 Coil 4 Coil 2 Coil 4 Coil 2
Coil 3
Coil 3

Coil 3
(14-b 2) (14-b 3) (14-b 4)

FIGURE 14-b FULL STEP STEPPER MOTOR DRIVE SEQUENCE.

stepper motor may also be operated with half step sequence.

rotor rotates through 45º in

each step.

common stepping sequence- 1.8º, 7.5º and 15º etc.

---------------------------------------------

Chapter: 6 MEMORY AND I/O INTERFACING

step sequence | No. of steps required
| for 1 rotation
---------------------------------------------
1.8º | (360º/1.8º=) 200 steps
7.5º | (360º/7.5º=) 48 steps
15º | (360º/15º=) 24 steps
---------------------------------------------
figure below shows the drive sequence for half step stepper motor.
Coil 1
Coil 1
Coil 1

Coil 4 Coil 2 Coil 4 Coil 2 Coil 4 Coil 2

Coil 3
Coil 3
Coil 3

(15.1) (15.2) (15.3) 14

 Coil 1
Coil 1
Coil 1
Coil 4 Coil 2 Coil 4 Coil 2 Coil 4 Coil 2

Coil 3
Coil 3
Coil 3
(15.4) (15.5) (15.6)

Coil 1
Coil 1
Coil 1

Coil 4 Coil 2 Coil 4 Coil 2 Coil 4 Coil 2

Coil 3
Coil 3
Coil 3

(15.7) (15.8) (15.9)

FIGURE 15.1-15.9 HALF STEP STEPPER MOTOR DRIVE SEQUENCE.

stepper motors can be driven directly by transistor to supply high

currents.
µC provide drive pattern at the output which causes the motor to
rotate.
diodes – flyback diodes which protects transistors from reverse bias.
+Vcc
Stepper motor

T1
D1
Vcc
+Vcc

Chapter: 6 MEMORY AND I/O INTERFACING

Vcc
T2
D2

+Vcc
PORT 2
T3
D3

+Vcc

T4
D4

FIGURE 16 STEPPER MOTOR DRIVE CIRCUIT INTERFACING WITH PORT2.

15
 PROGRAMMING STEPS:
i. port 2 is used as output port for interfacing the stepper motor.
--------------------------------------------------------------------------
SAMPLE PROGRAM: steppermotor_interfacing.asm
Labels Mnemonics Comments
--------------------------------------------------------------------------
ORG 0000H ; start address of program.
LOOP: MOV P2, #03H ; load step sequence 03h.
ACALL DELAY ; call delay.
MOV P2, #09H ; load step sequence 09h.
ACALL DELAY ; call delay.
MOV P2, #0CH ; load step sequence 0ch.
ACALL DELAY ; call delay.
MOV P2, #06H ; load step sequence 06h.
ACALL DELAY ; call delay.
AJMP LOOP ; repeat.
DELAY: MOV R0, #0FFH ; load r5 with 0ffh.
DELAY1: MOV R1, #0FFH ; load r7 with 0ffh.
HERE: DJNZ R1, HERE ; wait until r1=0.
DJNZ R0, DELAY1 ; wait until r0=0.
RET ; return to main program.
END ; end address of program.
-----------------------------------------------------------------------
the step sequence is described below,
depending on no. of steps the step sequence is given below.

a. normal 4 step sequence-

-----------------------------------------------------------------------
Step A B C D Hex Equivalent
-----------------------------------------------------------------------
Clockwise

1 0 0 1 1 03H
clockwise
2 1 0 0 1 09H Anti-
3 1 1 0 0 0CH
4 0 1 1 0 06H
-----------------------------------------------------------------------
b. normal 8 step sequence-
-----------------------------------------------------------------------
Step A B C D Hex Equivalent
-----------------------------------------------------------------------
1 0 0 1 1 03H

Chapter: 6 MEMORY AND I/O INTERFACING

2 0 0 0 1 01H
Anticlockwise
Clockwise

3 1 0 0 1 09H
4 1 0 0 0 08H
5 1 1 0 0 0CH
6 0 1 0 0 04H
7 0 1 1 0 06H
8 0 0 1 0 02H
-----------------------------------------------------------------------

4. Interfacing Relay
µC: pins at output provides Max. 1.32mA current.
relay coil needs around 10mA.
hence µC lacks sufficient driving current for relay.
relay driver – ULN2803 or power transistors employed for this purpose.
figure below shows the connection of relay driver ULN2803 between µC &
relay.

16
 +12V

+5V +5V +5V

ULN2803 RELAY COIL

µC 8051

P1.0

FIGURE 17 RELAY DRIVER & RELAY COIL INTERFACING WITH PORT 1.

solid state relay:

no coil, spring or mechanical contact switch.
no mechanical parts made of semiconductor.
extreamely low input current requirement& small packaging makes
it ideal for µC & logic control switching.
widely used in controlling pumps, solenoids, alarms & other power
applications.
AC Mains
Vcc
SSR

T3
Zero Fan
8051 Voltage
ckt

P1.0

FIGURE 18 FAN CONTROL USING A SOLID STATE RELAY (SSR).

above figure shows control of a fan using a solid state

relay(SSR).

Chapter: 6 MEMORY AND I/O INTERFACING

17