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East Delta University CSE Assignment 3

This document contains the solutions to two exercises on digital logic circuit design from a Digital Electronics and Pulse Technique lab course. For Exercise 1.2, the student designs a circuit with three inputs A, B, C that outputs HIGH when a majority of the inputs are HIGH. For Exercise 1.4, the student designs a circuit to control a laser beam based on the states of three switches. Truth tables, circuit diagrams, and timing diagrams are provided for both solutions.

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M.K. Ataul Karim
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57 views11 pages

East Delta University CSE Assignment 3

This document contains the solutions to two exercises on digital logic circuit design from a Digital Electronics and Pulse Technique lab course. For Exercise 1.2, the student designs a circuit with three inputs A, B, C that outputs HIGH when a majority of the inputs are HIGH. For Exercise 1.4, the student designs a circuit to control a laser beam based on the states of three switches. Truth tables, circuit diagrams, and timing diagrams are provided for both solutions.

Uploaded by

M.K. Ataul Karim
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Assignment-3 (1.2 & 1.

4)

Course Title: Digital Electronics and Pulse Technique Lab


Course Code: CSE 224

Submitted To: Pranta Saha


Lecturer
School of Science, Engineering and Technology

East Delta University, Chittagong

Submitted By:
M.K. Ataul Karim
ID: 163001112
Submission Date: 7th July, 2020.
Exercise 1.2:
Design a logic circuit that has three inputs, A, B, and C, and whose output will be HIGH
only when a majority of the inputs are HIGH.
Answer:
From the problem statement the output should be 1(high), when two out of three or all
three inputs are 1(high). Other outputs should be 0 (low).
So the truth table should be:
A B C Output (f)
0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 1

1 0 0 0
1 0 1 1

1 1 0 1

1 1 1 1

Here we found four cases where the outputs are HIGH. So the Boolean expression of this
statement is:
f= A’BC +AB’C +ABC’ +ABC
Minimization of this function is:
f= A’BC+ AB’C +ABC’ +ABC
= A’BC +ABC +AB’C +ABC +ABC’ +ABC (since A+A=A)
= BC (A’+A) +AC (B’+B) + AB (C’+C)
= BC +AC +AB (since A+A’=1)
= AB +BC +AC
Here the main circuit picture in DSCH software given below:

Timing diagram of this circuit is:


Minimize function circuit of main function in DSCH software is:

Timing diagram of this minimize circuit:


Exercise 1.4:
Assume, there is a laser beam in a Lab facility. A three switch-system could be
implemented to protect personnel from the laser beam, with a switch S1 on the door to
the lab, a switch S2 on the plastic covers over the beam path, and an over-ride S3 switch
for all these interlocks which a maintenance technician might make use of. To fire the
beam in normal use, we want S1 and S2 to be closed and S3 open. We choose this way
round because switches activated by doors generally close (complete an electrical circuit)
when a door is closed. When the switch is closed, the logic level is low. Now, implement
the logic and design the circuit.
Answer:
From the problem statement we understood that the laser beam should be fired when S1
and S2 are closed and S3 is open.
Here, logic level low means that the active state of a switch is a 0 or false status. So we
can say that, the laser is fired when S1 and S2 is false (0) and S3 is open (1).
We know that only NOR gate give the output false if and only if at least one input is true.
So if we use a NOR gate between S1 and S2 we can solve the problem of S1 and S2
switch. Now we have to use an AND gate because only AND gate makes the output true
if, and only if, all inputs are [Link] the Boolean expression of this problem should be,
f= S3 (S1’ S2’)
= S3 (S1+S2)
= (S1+S2)’ S3
Truth table of this function:
S1 S2 S3 Output(f)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Circuit Diagram of this function is:

Minimization circuit Diagram of this function is:


Here the main circuit pictures in DSCH software given below:

Figure 1: When all inputs S1,S2,S3 are low(0) so the output is low.

Figure 2: When S1 and S2 is low (0) and S3 is high (1) so the output is high (1).
Timing diagram of this circuit:

Here the minimize circuit pictures in DSCH software given below:

Figure 1: When all inputs S1, S2, S3 are low(0) so the output is low.
Figure 2: When S1 and S2 is low (0) and S3 is high (1) so the output is high (1).

Timing diagram of minimize circuit:


Class work

Minimize function of this circuit:


f= (x1+x2) x3

Truth table of this function:


X1 X2 X3 Output(f)
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
Here the circuit picture in DSCH software given below:

Timing diagram of this circuit:

Common questions

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The Boolean expression for firing a laser in this switch system, where switches S1 and S2 should be closed and S3 open (represented as logic level low for closed switches), is f = (S1 + S2)' S3. This setup ensures that the laser fires only when S1 and S2 are in the active state (0, closed), and S3 is in the non-active state (1, open).

To minimize the circuit design for the problem of laser firing involving logic switches, you start by establishing the initial Boolean expression based on specified conditions. For the problem given, you create a truth table reflecting S1, S2, and S3's conditions, then derive and simplify the Boolean expression using techniques such as combining terms and using identities like (A+A'). The minimized expression results can be implemented using logic gate configurations such as NOR and AND, ensuring the most efficient circuitry for the operation .

The logical conclusion about using a NOR gate combined with S3 in this context is that it ensures the protective conditions are met for safe laser operation. The NOR gate ensures both S1 and S2 are closed (active) before considering S3. By integrating S3 with an AND operation, it guarantees that all conditions for a safe laser fire are fulfilled, providing a robust safeguard against accidental activation .

The timing diagram of a logic circuit provides a visual representation of the circuit's performance over time. It shows the relationship between inputs and the resulting outputs, indicating the periods when inputs change and how quickly the output responds. Such diagrams are crucial for verifying that the circuit meets the temporal requirements and behaves as expected under given input conditions .

DSCH software is used for designing and simulating digital logic circuits. It provides visualization tools, allowing users to create circuit schematics, observe timing diagrams, and verify the behavior of circuits against truth tables. This helps in ensuring the designs are correct before physical implementation, offering a platform for experimenting with circuit configurations virtually .

Truth tables play a crucial role in designing and verifying logic circuits as they systematically list all possible combinations of inputs and their corresponding outputs. They help in understanding the behavior of logic functions, ensuring that the designed circuit reflects the desired logical operations. By providing a clear relationship between inputs and outputs, truth tables facilitate the derivation of Boolean expressions needed for circuit implementation .

To design a logic circuit that outputs HIGH when a majority of the three inputs A, B, and C are HIGH, you need to create a truth table and derive the Boolean expressions. The output should be 1 (HIGH) when at least two out of the three inputs are HIGH. The truth table would have four cases where the output is HIGH: when inputs are (0,1,1), (1,0,1), (1,1,0), and (1,1,1). The corresponding Boolean expression can be derived and minimized to f = AB + BC + AC .

The simplified Boolean expression for a problem where at least two of the three inputs A, B, and C need to be HIGH for the output to be HIGH is f = AB + BC + AC. This expression is derived by summing products corresponding to the truth table cases where at least two inputs are HIGH .

A NOR gate is suitable because it outputs false only if at least one input is true. For switches S1 and S2, which are closed when low, the NOR gate ensures the output remains true only if both are in their active (closed/low) state, which matches the requirement to prepare the circuit to fire the laser .

The combination of NOR and AND gates is used to satisfy the switch conditions for laser operation. The NOR gate handles the condition for S1 and S2, ensuring the output is true only when both switches are closed. The AND gate is then used to combine the output of the NOR operation with S3, so the whole expression outputs true only if the result from S1 and S2 is true and S3 is open. Thus, the expression (S1 + S2)' S3 correctly models the required logic .

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