1978 RCA Linear Integrated Circuits
Uploaded by
lykaonas1978 RCA Linear Integrated Circuits
Uploaded by
lykaonasLinear
Integrated
SSD·24·0A
Circuits
RCA
Linear Integrated Circuits
This DATABOOK contains complete Table of Contents
technical information on the full line Page
of RCA standard commercial linear in- Index to Devices ................................................... 3
tegrated circuits and MOS field-effect
transistors for both industrial and con- Packages......................................................... 5
sumer applications. An Index to Product Qassification Chart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Devices provides a complete listing of Operating and Handling Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
types, together with an indication of Terms and Symbols ................................................ 10
package options available for each of
them. Cross-Reference Directory. . . . . . . . . . . . . . .. . . .. . . . . . .. . . . . . . . . . .. . . . . . 12
The pages immediately following the Linear Integrated Circuits for Industrial Applications-Technical Data. . . . . 17
Index to Devices include photographs Linear Integrated Circuits for Consumer Applications-Technical Data .... 291
of the packages used for RCA linear MOS Field-Effect Transistors-Technical Data. . . . . . . . . . . . . . . . . . . . . . . .. 433
integrated circuits and MOS/FET's, a
product-classification chart, recom- Dimensional Outlines. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 475
mended operating and handling con- Application Notes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 483
siderations, a list of special terms and RCA Sales Offices, Manufacturers' Representatives, and
symbols used in the characterization of Authorized Distributors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 559
RCA linear integrated circuits and
MOS/FET's, and a cross-reference
directory that indicates RCA types
recommended as direct replacements
for other manufacturers' types.
Three separate data sections provide
definitive ratings and electrical
characteristics for (1) Linear Integrated
Circuits for Industrial Applications,
(2) Linear Integrated Circuits for
Consumer Applications, ~d (3) MOS
Field-Effect Transistors (MOSI
FET's). Data pages for individUal
devices are included as nearly as pos-
sible in alpha-numerical sequence of
type numbers. Because some devices
are grouped together to show similarity
of function or data, individual type
numbers may be out of sequence. If
you don't find the data on a specific
type where you expect it to be, check
the Index to Devices.
The DATABOOK also includes dimen-
ROI"
sional outlines for all currently
available packages and selected RCA Brussels' Buenos Aires' Hamburg' Madrid' Mexico City' Milan
Application Notes on RCA Linear In- SOlidi Montreal' Paris' Sao Paulo' Somerville NJ • Stockholm
tegrated Circuits and MOS/FET's. • • State Sunbury·on·Thames • Taipei' Tehran' Tokyo
Index to Devices - Linear Ie's
Data Data
Type Packaga Bullelln Typa Package Bullelln
Number Suffix File No. Page Number Suffix Fila No. Paoa
CA101
CA101A
T
T
S
S
-
G
-
-
-
-
-
-
786
786
18
18
CA3007
CA3008 ...• -
-
-
-
-
-
-
-
-- 126
316
72
74
CA107 T S G - - - 785 22 CA3008A ... - - - - - 310 78
CA111 T S G - - - 797 25 CA3010 -
•• - - - - - 316 74
CA124 E G - - - - 796 29 CA3010A - - - - 310 78
- - - - -- -
••• -H
CA139 E G 795 32 CA3011 - - - 128 82
CA139A E G - - - - 795 32 CA3012 - - - 128 82
CA158 T S G -
-
-
-
-
-
1019 35 CA3013 -- -
-
- - 129 84
•• L H
CA158A T S G 1019 35 CA3014 - - - 129 84
CA201 T S - - - - 786 18 CA3015 - - - 316 74
-
...• - -- --
CA201A T S G - - - 786 18 CA3015A - - 310 78
:A207 T S G - - - 785 22 CA3016
... - - - - - 316 74
CA211
CA224
T
E
S
G -
G -
-
-
-
-- 797
796
25
29
CA3016A
CA3018 L H -
-
-
-
-
310
338
78
87
- -
--- --
CA239 E G - - 795 32 CA3018A - - - - 338 87
CA239A E G - - - - 795 32 CA3019 H - - 236 90
CA258 T S G - - - 1019 35 CA3020 H - - 339 92
CA258A
CA270
T
W
S
- -
G -
-
-
-
-
-
1019
879E
35
292
CA3020A
CA3021
-
-
-- -- -
-
-
-
339
243
92
96
CA301A T S E' G H - 786 18 CA3022 - - - - - 243 96
CA307
CA311
T
T
S
S
E'
E'
G
G
H
-
-
-
785
797
22
25
CA3023
CA3026
H
H
-
-
-
-
-- -- 243
338
96
99
CA324 E G H GH - - 796 29 CA3028A S L - H - 382 103
CA339 E G H GH - - 795 32 CA3028B S - - - - 382 103
CA339A E G - - - - 795 32 CA3029 - - - - - 316 74
CA358 T S G H
-
GH
-
- 1019 35 CA3029A - - - - - 310 78
CA358A T S G - 1019 35 CA3030 - - ~
- - 316 74
CA555
CA555C
T
T
S
S
E'
E'
G
G
-
H
-
-
834
834
42
42
CA3030A
CA3035
-
VI
-
H
-
-
-
-
-- 310
I 274
78
319
CA723 T E - - - - 788 46 CA3036 - - - - - I 275 108
CA723C T E H - - - 788 46 CA3037 - - - - - 316 74
CA741
CA741C
T
T
S
S
E'
E'
G
G
L
H
-
GH
531
531
50
50
CA3037A
CA3038
t
t
-- -
-
-
-
-
-
-
-
310
316
78
74
CA747 T E G - - - 531 50 CA3038A t - - - - - 310 78
- - - --
,•• --
CA747C T E G H GH 531 50 CA3039 L H 343 109
CA748 T S E' G - - 531 50 CA3040 - - - 363 111
CA748C
CA758
T
E
a
S
-
E'
-
-
G
-
-
H
-
-
GH
-
-
531
760
50
295
CA3041
CA3042 , -
-
-
-
-
-
-
-
-
-- 318
319
320
323
CA810
CA810A a
OM
OM - - - -
1154
1154
298
298
CA3043
CA3044
•• H
VI - -
-
-
-
-
331
340
326
328
CA920 E - -- - - - 1132 301 CA3045 t F L H - - 341 114
CA1190 a - - - - 1155 303 CA3046 t - - - - - 341 114
CA1310 E - - - - - 761 306 CA3048 • - - - - - 377 117
CA1352 E - - - - - 961 309 CA3049 T L H - - - 611 120
CA1391 E' - - - - - 981 310 CA3050 t - - - - - 361 124
CA1394 E' - - - - - 981 310 CA3051 • - - - - - 361 124
CA1398 E - - - - - 686 312 CA3052 • - - - - - 387 331
CA1458 T S E' G H GH 531 50 CA3053 •• S - - - - 382 103
CA1541 0 H - - - - 536 54 CA3054 L H - - - 388 99
CA1558 T S E' G - - 531 50 CA3058 t - - - - - 490 127
CA2002 (j) M - - - - 1156 314 CA3059 •0 H - - - - 490 127
CA2004 (j) M - - - - 1105 317 CA3060 E H - - - 537 132
CA2111A E a - - - - 612 57 CA3060A 0 - - - - - 537 132
CA2904 G - - - - - 1019 35 CA3060B - - - - - 537 132
,,,
0
•••
CA3000 H - - - - 121 59 CA3064 E - - - - - 396 335
CA3001 H - - - - 122 61 CA3065 - - - - - 412 337
CA3002 H - - - - 123 64 CA3066 - - - - - 466 340
CA3004
CA3005
•• H
H
-
-
-
-
-
-
-
-
124
125
66
69
CA3067
CA3068 , -
-
-
-
-
-
-
-
-
-
466
467
340
343
CA3006 • - - - - - 125 69 CA3070 • - - - - - 468 345
______ ~ ___________________________________________________________ 3
~
!
Index to Devices - MOS/FET's
Data Data
Type Bulletin Type BulieUn
Number Package File No. Page Number Package File No. Page
3N128 10·72 309 434 3N212 10·72 875 458
3N138 10·72 283 436 3N213 10·72 875 458
3N139 10·72 284 437 40467A 10·72 324 462
3N140 10·72 285 438 40468A 10·72 323 463
3N141 10·72 285 438 40559A 10-72 323 463
3N142 10·72 286 441 40600 10-72 333 464
3N143 10·72 309 434 40601 10-72 333 464
3N152 10·72 314 442 40602 10-72 333 464
3N153 10·72 320 443 40603 10-72 334 465
3N154 10·72 335 444 40604 10-72 334 465
3N159 10·72 336 459 40673 10-72 381 466
3N187 10·72 326 446 40819 10-72 463 467
3N200 10·72 436 450 40820 10-72 464 468
3N204 10·72 959 453 40821 10-72 464 468
3N205 10·72 959 453 40822 10-72 465 470
3N206 10·72 959 453 40823 10-72 465 470
3N211 10·72 875 458 40841 10-72 489 471
Packages
D Suffix E Suffix E Suffix
Dual·ln·Line Welded-Seal Dual·ln·Line Plastic Package Power Stud Plastic
Ceramic Package Dual·ln·Line Package
H1828
14 and 16·lead versions 8, 14, and 16·lead versions CA3134E only
EM Suffix EM Suffix F Suffix
Modified 16·lead Dual· Modified 16·lead Dual· Dual-ln·Line Fril·Seal
In·Line Plastic Package In-Line Plastic Package Ceramic Package
H1827
CA3134EM only CA3131EM, CA3132EM only 14 and 16·lead versions
5
Product Classification Chart
Induatrlal Clrculta
OPERATIONAL AMPLIFIERS DIFFERENTIAL ARRAYS
AMPLIFIERS
General Purpose Amplifier/
General Purpose Variable Transistor
Wideband Diode
Single Unit Dual Unit Single Unit High Current CA3000 Amplifier CA3018 CA3095
CA101 CA158 CA3008 CA3094 CA3001 CA3026 CA3036 CA3096
CA107 CA258 CA301 0 Micropowar CA3004 CA3035 CA3045 CA3097
CA201 CA358 CA3015 CA3060 CA3005 CA3048 CA3046 CA3118
CA207 CA747 CA3016 CA3078 CA3006 CA3049 CA3050 CA3127
CA301 CA1458 CA3029 CA3080 CA3007 CA3052 CA3051 CA3138
CA307 CA1558 CA3030 CA6078· CA3026 CA3054 CA3081 CA3146
CA741 CA2904 CA3037 CA3028 CA3060 CA3082 CA3183
CA748 Quad Unit CA3038 CA3049 CA3102 CA3083 CA3600·
CA6741· CA124 CA31 00* CA3050 Diode CA3084 CA3724
CA224 CA3130* CA3051 CA3019 CA3086 CA3725
CA324 CA3140· CA3053 CA3039 CA3093
CA3401 CA3160* CA3054 CA3141
Dual Unit CA3102
CA324O*
VOLTAGE IZERO-VOL TAGE VOLTAGE SPECIAL-FUNCTION
REGULATORS SWITCHES COMPARATORS CIRCUITS MOS/FET's
CA723 CA3058 Single Unit A/D Converter Single Gate Dual Gate
CA3085 CA3059 CA111 CA3162 3N128 3N140
CA3079 CA211 BCD-to-7-Segment Decoder/Driver 3NI38 3N141
CA311 CA3161 3N139 3N159
CA3098+ Memory Sense Amplifier 3N142 Dual Gate
CA3099+ CA1541 3N143 Protected
Duel Unit Four-Ouadrant Multiplier 3N152 3N187
CA3290* CA3091 3N153 3N200
Quad Unit Timer 3N154 40819
CAI39 CA555
CA239 Programmable Schmitt Trigger
CA339 CA3098
Con au mer Clrculta
BROADBAND AM/FM
(VIDEO) COMMUNICATIONS AUDIO FM IF TV RECEIVER MOS/FET's
AMPLIFIERS CIRCUITS CIRCUITS CIRCUITS CIRCUITS
CA3002 CA2111A Preamplifiers Subsystems Tuning Chroma Systems Single Gate Dual Gate
CA1352 CA3011 CA3036 CA2111A CA3163 CA1398 40467A Protected
CA3020 CA3012 CA3052 CA3013 CA3166 CA3066 40468A 3N204
CA3021 CA3013 Drivers CA3014 CA3168 CA3067 40559A 3N205
CA3022 CA3014 CA3094 CA3043 AFT CA3070 Dual Gate 3N206
CA3023 CA3043 Power Amplifiers CA3044 CA3071
CA3075 40600 3N211
CA3040 CA3064 CA3072
CA3075 CAB10 CA3089 40601 3N212
CA3139 CA3121
CA3076 CA2002 CA3189 40602 3N213
MULTIPLEX Sound IF CA3125
CA3088 CA2004 Gain Blocks CAII90 40603 40673
DECODERS CA3126
CA3089 CA3131 CA3011 CA2111A CA3128 40604 40820
CA758 CA3123 CA3132 CA3012 CA3041 CA3151 40821
C1310 CA3163 CA3076 CA3042 CA3170 40822
CA3090A CA3189 CA3065 Luminance 40823
CA3134 Processors
40841
PIX IF CA3135
CA270 CA3143
CAI352 CA3144
CA3068 Horizontal
CA3136 Systems
Remote Control CAI391
CA3035 CAI394
,.Jungle" Circuits CA920A
CA3120 CA3159
CA3142 CA3172
• Low-noise versions of CA741 and CA3078 * BiMOS types ·CMOS type + Programmable
7
Operating and Handling Considerations
tions, with virtually no problems of damage due to SOLID STATE CHIPS
electrostatic discharge. Solid state chips, unlike packaged devices, are non-
In some MOS FETs, diodes are electrically connected hermetic devices, normally fragile and small in physical size,
between each insulated gate and the transistor's source. and therefore, require special handling considerations as
These diodes offer protection against static discharge and follows:
in-circuit transients without the need for external shorting
mechanisms. MOS FETs which do not include gate- I. Chips must be stored under proper conditions to insure
protection diodes can be handled safely if the following basic that they are not subjected to a moist and/or contam-
precautions are taken: inated atmosphere that could alter their electrical,
physical, or mechanical characteristics. After the shipping
1. Prior to assembly into a circuit, all leads should be kept container is opened, the chip must be stored under the
shorted together either by the use of metal shorting following conditions:
springs attached to the device by the vendor, or by the A. Storage temperature, 40 0 C max.
insertion into conductive material such as "ECCOSORB* B. Relative humidity, 50% max.
LD26" or equivalent. C. Clean, dust-free environment.
(NOTE: Polystyrene insulating "SNOW" is not suffi- 2. The user must exercise proper care when handling chips
ciently conductive and should not be used.) to prevent even the slightest physical damage to the chip.
2. When devices are removed by hand from their carriers,
the hand being used should be grounded by any suitable 3. During mounting and lead bonding of chips the user must
means, for example, with a metallic wristband. use proper assembly techniques to obtain proper elec-
3. Tips of soldering irons should be grounded. trical, thermal, and mechanical performance.
4. Devices should never be inserted into or removed from 4. After the chip has been mounted and bonded, any
circuits with power on. necessary procedure must be followed by the user to
insure that these non-hermetic chips are not subjected to
moist or contaminated atmosphere which might cause
*Trade Mark: Emerson and Cumming, Inc. the development of electrical conductive patlis across the
relatively small insulating surfaces. In addition, proper
consideration must be given to the protection of these
devices from other harmful environments which could
conceivably adversely affect their proper performance.
__________________________________________________________________________ 9
Terms and Symbols
VBE(sat) base-ta-emitter saturation VG2S gate-No.2-to-source voltage magnitude of sma II-signal,
voltage (dual-gate types) common-source, short-circuit,
V(BR)CBO collector-to-base breakdown V G2S (off) gate-No.2-to-source cutoff reverse transadmittance
voltage voltage (dual-gate types) phase angle of small-signal,
collector-to-emitter break- <Vrs
V(BR)CES VI input voltage common-source, short-circuit,
down voltage VI(Lim) input limiting voltage reverse transadmittance
V(BR)OI dc breakdown voltage be- VICR common-mode input voltage (-)rs angle of reverse trans-
tween diode and substrate range admittance, common-source
V(BR)R dc reverse breakdown voltage V IL input-voltage, low level circuit
V(BR)EBO emitter-to-base breakdown V IH input-voltage, high level input impedance
voltage Zl
VIO input offset voltage
dc gate-to-source forward IVIOI magnitude of input offset Zo output impedance
V(BR)GSSF
breakdown voltage, all other voltage
Zz zener impedance
</> phase angle
terminals shorted to source "VlOi"T temperature coefficient of phase margi n
</>
(single-gate types) magnitude of input offset efficiency
7)
V(BR)G1SSF dc gate-No.1-to-source voltage open-loop phase lag
</>·L
forward breakdown voltage, "VlOi"T temperature coefficient of
all other terminals shorted to input offset voltage drift
source Idual-gate types) "VloI"V+ positive input-off set-voltage
V(BR)G2SSF dc gate No.2-to-source forward sensitivity
breakdown voltage, all other "VlOi"V- negative input-offset-voltage
terminals shorted to source sensitivity
(dual-gate types) aVIO average temperature
V(BR)GSSR de gate-ta-source reverse coefficient of input-offset
breakdown voltage, all VOltage
other terminals shorted to Vil Lim) input limiting voltage (knee)
source Isingle-gate types) V knee protective diode knee
V(BR)G2SSR de gate-No.2-to-source voltage (protected gate types)
reverse breakdown voltage, VN output noise voltage
all other terminals shorted output voltage
Vo
to source (dual-gate types) "VOi"V- dc supply voltage sensitivity
VCBO collector-to-base voltage L\VOilOV+ dc supply voltage sensi1ivity
VCC drain supply voltage open-loop output voltage
used as a second positive VO(rms)
swing
supply voltage. It is';;;;V OO "'VO output voltage temperature
and referenced to V SS coefficient
VCO voltage controlled oscillator V Op_p output voltage swing
VCEO collector-ta-emitter voltage recovered af voltage
VOlat)
VCEO(sus) collector-ta-emitter
VOL output voltage, low level;
sustaining VOltage
the voltage level at an output
VCIO collector-ta-substrate voltage when the input logic
VCP charge pump voltage conditions have been set to
VOO drain supply voltage (the most establish logic LOW output.
positive supply voltage; output offset voltage
VOO
always referenced to ground) V OH output voltage, high level;
VOG drain-to-gate voltage Isingle- the voltage level at an output
gate types) when the input logic conditions
V OG1 drain-to-gate-No.1 voltage have been set to establish a
(dual-gate types) logic HI GH output.
V DG2 drain-to-gate-No.2 voltage VOM + maximum output voltage
(single-gate types) VOM - maximum output voltage
VDIO diode-to-substrate voltage VOP charge pump voltage
V DR diode reverse voltage V OPL charge pump input voltage,
VDS drain-ta-source voltage low level
VEE source voltage (the most V OPH charge-pump input voltage,
negative supply voltage in a high level
3-supply voltage system) V REF reference voltage
VF dc forward voltage V REG regulated supply voltage
I\VFi"'T temperature coefficient of V RR supply voltage rejection
forward·voltage drop ratio
V GH channel gate input voltage, VTH input threshold voltage
high level V z zener voltage
V GL channel gate input voltage, Vfs magnitude of small-signal,
low level common-source, short-
V GS gate-ta-source voltage circuit forward transfer
VGS(TH) gate-to-source threshold admittance (transadmittance)
voltage \'is small-signal, common-source,
VGSIOff) gate-to-source cutoff voltage short-circuit, input-admittance
Isingle-gate types) Iconductance, rea I part of
VG1S gate-No.l-to-source voltage admittance; susceptance,
(dual-gate type) imaginary part of admittance)
VG1S (Off) gate-No.1-to-source cutoff Vos small-signal, common-source,
voltage Idual-gate types) short-circuit, output
______________________________________ admittance
~-----------------------11
Cross-Reference Directory for Linear Integrated Circuits
RCA RCA RCA
Industry Replacement Industry Replacement Industry Replacement
Type Type Type T,Ipe Type Type
LM311L CA311T LM1558H CAl558T MCl558P CAl558G, CA1558E
LM311N CA3llG, CA3llE LM1558J CAl558G MC1558Pl CA1558G, CAl558E
LM3llN·14 CA311G,CA3l1E LMl558N CAl558G, CAl558E MCl558T CAl558T
LM3llP CA3llG, CA3llE LMl800N CA758E MCl558U CAl558G
LM3llT CA3llT LM1820N CA3l23E MC1723CG CA723CT
LM3l8H CA3l3OT LMl845N CA3120E MC1723CP CA723CE
LM324AD CA324AG LM2lllN CA2lllAE MC1723G CA723T
LM324AN CA324AG, CA324AF LM2901N CA339G MC1741CG CA741CT
LM324D CA324G LM2904N CA2904G MC1741CL CA741CG
LM324F CA324G LM2904P CA2904G MC1741CPl CA741CG, CA741CE
LM324J CA324G LM30llH CA3011 MC1741CP2 CA741CG,CA741CE
LM324N CA324G, CA324E LM30l8H CA3018 MC1741G CA741T
LM339AD CA339AG LM30l8AH CA30l8A MC1741L CA741G
LM339AF CA339AG LM30l9H CA3019 MC1741U CA741G
LM339AJ CA339AG LM3026H CA3028 MC1747CG CA747CT
LM339AN CA339AG, CA339AE LM3028AH CA3028A MC1747CL CA747CG
LM339A CA339G, CA339E LM3028B CA3028B MC1747G CA747T
-
LM339D CA339G LM3039H CA3039 MC1747L CA747G
LM339F CA339G LM3045D CA3045 MC1748CG CA748CT
LM339J CA339G LM3048N CA3048 MC1748CPl CA748CG, CA748CE
LM339N CA339G, CA339E LM3053H CA3053 MC1748CU CA748CG
LM358AH CA358AT LM3054N CA3054 MC1748G CA748T
LM358AN CA358AG, CA358AE LM3084H CA3084T MC1748U CA748G
LM358AT CA358AT LM3084N CA3084E MC3348P CA3048
LM358JG CA358G LM3085N CA3085 MC3388P CA3088
LM358H CA358 LM3088N CA3088 MC3401L CA3401G
LM358L CA358T LM3087N CA3067 MC3401P CA3401E
LM358N CA358G, CA358E LM3070N CA3070 MLM101AG CA101AT
LM358P CA358G, CA358E LM3071N CA3071 MLM101AU CA101AG
LM358T CA358T LM3075N CA3075 MLM107G CA101T
LM393N CA3290E LM3088N CA3088 MLM107U CA101G
LM555CH CA555CT LM3089N CA3089E, CA3l89E MLMlllG CAll1T
LM555CN CA555CG, CA555CE LM3l28N CA3l28E MLMlllU CAlllG
LM555H CA555T LM3148AN CA3l48AE MLMl24L CA124G
LM555N CA555G, CA555E LM3401N CA3401G, CA3401E MLM139AL CAl39AG
LM723CD CA723CE MC13l0P CA13l0E MLMl39L • CA139G
LM723CH CA723CT MCl352P CAl352E MLMl58G CAl58T
LM723CN CA723CE -MCl357P CA2l11AE MLMl58Pl CAl58G, CAl58E
LM723D CA723E MCl357PQ CA2111AQ MLMl58U CAl58G
LM723H CA723T MC1358P CA3085 MLM201AG CA201AT
LM723N CA723E MCl384G CA3084T MLM201AP1 CA201AG, CA201AE
LM741CH CA741CT MCl384P CA3084E MLM201AU CA201AG
LM741CJ CA741CG MC13lOP CA3070 MLM201G CA207T
LM741CN CA741CG, CA741CE MC1371P CA3071 MLM207U CA207G
LM741H CA741T MC1375P CA3075 MLM2llG CA2llT
LM741N CA741G, CA741E MCl389P CA3089E, CA3l89E MLM2llU CA2llG
LM748N CA3072 MCl391P CA1391E MLM224L CA224G
LM747CD CA747CG MC1394P CAl394E MLM224P CA224G, CA224E
LM741CH CA747CT MCl398P CAl398E MLM239AL CA239AG
LM747CJ CA747CG MCl455G CA555CT MLM239AP CA239AG, CA239AE
LM747CN CA747CG, CA747CE MC1455Pl CA555CG,CA555CE MLM239L CA239G
LM747D CA747G MCl455U CA555CG MLM239P CA239G,CA239E
LM747H CA747T MCl458JG CAl458G MLM258G CA258T
LM747J CA747G MCl458G CA1458T MLM258U CA258G
LM748CH CA748CT MCl458L CAl458T MLM301AD CA301AG
LM748CJ CA748CG MCl458P CAl458G, CAl458E MLM301AG CA301AT
LM748CN CA748CG, CA748CE MC1458Pl CAl458G, CAl458E MLM301APl CA301AG, CA301AE
LM748H CA748T MC1458T CAl458T MLM301AU CA301AG
LM749J CA748G MCl541L CAl54l 0 MLM307G CA307T
LM13l0N CA13l0E MCl555G CA555T MLM307Pl CA307G, CA307E
LM1391N CAl391E MCl555Pl CA555CG, CA555CE MLM307U CA307G
LM1394N CAl394E MCl555U CA555G MLM3llG CA3llT
LM1458H CAl458T MCl558JG CAl558T MLM3llPl CA3llG, CA3llE
LMl458J CAl458G MCl558G CAl558T MLM3llU CA3llG
LM1458N CAl458G, CAl458E MCl558L CAl558T MLM324L CA324G, CA324E
13
Cross-Reference Directory for Linear Integrated Circuits
RCA RCA RCA
Industry Replacement Industry Replacement Industry Replacement
Type Type Type Type Type Type
SN76666N CA3065 ~101H CA101T ~748CJ CA748CG
SN76675N CA3075 ~107H CA10n ~748Cl CA748T
SN76676P CA3076 ~111H CAll1T ~748CN CA748G,CA748E
SN76689N CA3089E, CA3189E ~111R CAlllG ~478CP CA748G,CA748E
SP3724 CA3724G ~201AD CA201AG ~748CT CA748CT
SP3725 CA3725G ~201AH CA201AT ~748DC CA748CG
SSS101AJ CA101AT ~201D CA201G ~748DM CA748G, CA748E
SSS101AP CA101AG, CA101AE ~201H CA201AT ~748HC CA748CT
SSS107J CA10n ~207H CA20n ~748HM CA748T
SSS107P CA107G, CA107E ~301AD CA301AG ~748MJG CA748G
SSS201AJ CA201AT ~301AH CA301AT ~748MJ CA748G
SSS201AP CA201AG, CA201AE ~307H CA30n ~748Ml CA748T
SSS207J CA20n ~30n CA307G, CA307E ~748MN CA748G,CA748E
SSS301AJ CA301AT ~301AT CA301AG, CA301AE ~748MP CA748G, CA748E
SSS301AP CA301AG, CA301 AE ~311H CA311T ~748T CA748T
SSS741CJ CA741CT ~311R CA311G ~748TC CA748CG, CA748CE
SSS1458J CA1458T ~311T CA311G, CA311E ~758PC CA758E
SSS1558J CA1558T ~555HC CA555CT ~780PC CA3070
TBA81OS CA810Q ~555HM CA555T ~781PC CA3071
TBA810AS CA810QM ~555TC CA555CG, CA555CE ~787PC CA3126Q
TDA2002V CA2002 ~720PC CA3123E ~1391T CA1391E
TDA2002H CA2002M ~723CA CA723CE ~1394T CA1394E
TBB0747 CA747CT ~723CK CA723CT ~1458HC CA1458T
TBB0748 CA748CT ~723Cl CA723CT ~1458Rl CA1458G
TBB0748B CA748CE ~723CN CA723CE ~1458HC CA1458G, CA1458E
TBB1458B CA1458E ~723DM CA723E ~1558HM CAl558T
TBC0747 CA74n ~723HC CA723CT ~3018HM CA3018
TCA270 CA270 ~723HM CA723T ~3018AHM CA3018A
TDA3081N CA3081 ~723K CA723T ~3019HM CA3019
TDA3082N CA3082 ~723MN CA723E ~3026HM CA3026
TDA3083N CA3083 ~723Ml CA723T ~3036HM CA3036
TDB0723 CA723CT ~723PC CA723CE ~3039HM CA3039
TDB0723A CA723CE ~741CJG CA741CG ~3045DM CA3045
TDC0723 CA723T ~741CJ CA741CG ~3048DC CA3048
U5B7741312 CA741T ~741CN CA741CG,CA741CE ~3064HC CA3064T
U5B7741393 CA741CT ~741Cl CA741T ~3064PC CA3064E
U5B7748312 CA748T ~741CP CA741CG, CA741CE ~3085PC CA3065
U5B7748393 CA748CT ~741CT CA741CT ~3066PC CA3066
U5R7723312 CA723T ~741DC CA741G ~3075PC CA3075
U5R7723393 CA723CT ~741DM CA741G ~3066DC CA3066F
U6A7723393 CA723CG, CA723CE ~741HC CA741CT ~3089E CA3089E, CA3189E
U9T7758393 CA1458G ~741HM CA741T ~3401P CA3401 G, CA3401 E
U9T7741393 CA741CG, CA741CE ~741MJG CA741G ~PC151A CA741CT
ULN2111A CA2111AE ~741MJ CA741G ~PC151C CA741CG, CA741CE
UlN2111N CA2111AQ ~741Ml CA741T ~PC157A CA301 AT
ULN2114A CA3072 ~741MN CA741G,CA741E ~PC157C CA301AG, CA301AE
ULN2124A CA3070 ~741MP CA741G, CA741E ~PC251A CA747CT
UlN2125A CA3120E ~741PC CA741G, CA741E ~PC251C CA1458G, CA1458E
ULN2127A CA3071 ~746PC CA3072 ~PC301AC CA301AG, CA301AE
UlN2129A CA3075 ~747CA CA747CE ~PC311C CA311G, CA311E
UlN2137A CA3123E ~747CJ CA747CG ~PC324C CA324G, CA324E
UlN2165A CA3065 ~747CK CA747CT ~PC339C CA339G, CA339E
UlN2210A CA1310E ~747Cl CA747CT I'PC741C CA741CG, CA741CE
UlN2212B CA3012 ~747CN CA747CG, CA747CE I'PC1458C CA1458G, CA1458E
ULN2262A CA3126Q ~747DC CA747CG
ULN2264A CA3064 ~747DM CA747G
UlN2266A CA3066 ~747HC CA747CT
ULN2267A CA3067 ~747HM CA74n
ULN2269A CA3121E ~747MJ CA747G
UlN2289A CA3089E, CA3189E ~747Ml CA74n
ULN2298A CA1398E ~747MN 'CA747G, CA747E
ULX2244A CA758E ~747PC CA747G, CA747E
~101AH CA101AT ~747A CA747E
~101AD CA101AG ~747K CA74n
~101D CA101G ~748CJG CA748G
15
Linear Integrated Circuits
for Industrial Applications
Technical Data
_ _ _ _ _ _ _ _ _ _ _ _ _ 17
CA10l, CA201, CA301 Types
ELECTRICAL CHARACTERISTICS
TEST CONDITIONsA LIMITS LIMITS
CA101A
CHARACTERISTICS Supply Voltage (V±) CA10l CA201 UNITS CA301A UNITS
=5to15V CA201A
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
I nput Offset Voltage TA=250C I RS';;;10kn - 1 5 - 2 7.5 - - - - - -
VIO I RS";;50kn - - - - - - mV
- 0.7 2 - 2 7.5
mV
RS";;10kn - - 6 - - 10 - - - - - -
RS";;50kn - - - - - - - - 3 - - 10
Average Temperature RS";;lOkn - 6 - - 10 - - - - - - -
Coefficient of Input RS";;50n - 3 - - 6 - J.i.V/oC - - - - - - J.i.V/oC
Offset Voltage oNIO - - -- - - - - 3 15 - 6 30
Average Temperature -55°C t.o +25 0 C - - -- - - - - 0.0 0.2 - - -
Coefficient of Input OOC to +25 0 C - - - - - -
nA/oC
- - - - 0.02 0.6
nA/oC
Offset Current '+25 0 C to + 70°C - - - - - - - - - - 0.D1 0.3
0' 110
+ 25°C to + 125°C - - - - - - - 0.01 0_1 - - -
Input Offset Current TA=OoC - - - - 150 750 - - - - - -
[Link] - 40 200 - 100 500 - 1.5 10 - 3 50
110 TA=700C - - - - 50 400
nA
- - - - - -
nA
TA=1250C - 10 200 - - - - - - - - -
- - - - - - - - 20 - - 70
TA=-550C - 100 500 - - - - - - - - -
-
Input Bias Current TA=-550C - 0.2S 1.5 - - - - - - - - -
liB
TA=OoC - - - - 0.32 2 - - - - - -
J.i.A J.i.A
TA=25 0 C - 0.12 0.5 - 0.25 1.5 - 0.03 0.075 - 0.07 0.25
- - - - - - - - 0.1 - - 0.3
Supply Current TA=[Link] I V±=15V - - - - - - - - - - 1.8 3
I± I V±=20V - 1.S 3 - 1.S 3 rnA - 1.8 3 - - - rnA
TA=1250C V±=20V - 1.2 2.5 - - - - 1.2 2.5 - - -
Open-Loop Differen- TA=250C V±=15V
tial Voltage Gain 50 160 - 20 150 - 50 160 - 25 160 -
VO=±lOV RL;;>2kH
V/mV V/mV
AOL V±=15V
VO=±lOV RL;;>2kn
25 - - 15 - - 25 - - 15 - -
Input Resistance RI TA=250C 0.3 O.S - 0.1 0.4 - MS2 1.5 4 - 0.5 2 - Mn
Output Voltage V±=15V RL =10kn ±12 ±14 - ±12 ±14 - ±12 ±14 - ±12 ±14 -
V V
Swing VOPP V±=15V RL =2kH ±lO ±l3 - ±lO ±l3 - ±10 ±13 - ±10 ±13 -
Common-Mode V±=l5V ±l2 - - ±l2 - - - - - ±12 - -
Input-Voltage V V
V±=20V - - - - - - tl5 - - - - -
Range VICR
Common-Mode RS<lOkn 70 90 - 65 90 - - - - - - -
Rejection Ratio dB dS
CMRR RS<50kH - - - - - - SO 96 - 70 90 -
Supply-Vol tage RS<lOkn 70 90 - 70 90 - - - - - - -
Rejection Ratio dB dB
PSRR RS";;50Hl - - - - - - 80 96 - 70 90 -
.. Characteristics applicable over operating temperature range (TA) as shown [Link], unless otherwise specified:
CA10l, CAl01A: -55 to +1250 C; CA20lA: -25 to +S50C; CA201, CA30lA: 0 to 70°C
Max. VIO
Max. 110
1 TA=
25°C
CA101
5
200
CA201
500
7.5
CA101A
2
10
CA201A
2·
10
CA301A
7.5
50
mV
nA
Min. AOL 50 20 50 50 25 V/mV
TA Range -55 to o to -55 to -25 to o to °c
(Operating) +125 +70 +125 +85 +70
Slew Rate
(Summing amp/.) - - 10 10 10 V/!'s
______________________________________________________________________ 19
CA101, CA201, CA301 Types
Two-Pole Compensation
CI il:
CS'lO,F
:".c: 2
" TIME itJ- ....
FREOUENCV (II-ttl Fig. 16 - Test circuit employing two-pole
compensation. Fig. 17 - Voltage follower pulse response.
Fig. 15 - Supply voltage rejection ratio vs. frequency.
Feed-Forward Compensation
',,1--+1\[----11--+-+---+---+-+-+-1
VOLTAGE SUPPLY IV:!: j"!:IV
1--+--\\-+ ~~:~~,~iN~i~:~r~T~7~:TAJ'25'C- '0
I--+-+-+ TWO-POLE COMPENSATION .-
\
\
I'\.
10 100 Ik 10k lOOk , '100M
FREQUENCY Itl-HI
FREQUENCY!II-Hz F ;g. 20 - Test circuit employing
feed forward compensation.
Fig. 18 - Voltage gain and phase lag vs. frequency. Fig. 19 - Output voltage swing vs. frequency.
7, OUT..,.
''0 I--~OLTAGE
100 - -
SUPPLY IV'!')' 15V
AMBIENT TE~PERATURE (T A)' 25'"C 225
FEEDF10RWARD COMPENSATION
\ VOLTAGE SUPPLY IV±.'-15V
INPUT
I------'l--+ AMBIENT TEMPERATURE (T AI- 25'"C
\ FEEDFORWARD COMPENSATION
\.
\.
\.
VOLTAGE SUPPLY (\/.1'.I,V
-7.5 AMBIENT TEMPERATURE IT A'- 25'C
FEEOFORWfoRO COMP£NSATION
TIME 1tI-~.
1011 lOOk tM
FREQUENCV Ill-Hz
10M ,.
FREQUENCY (fl-HI
Fig. 21 - Inverter pulse response. Fig. 22 - Voltage gain and phase lag vs_ frequency_ Fig. 23 -Output voltage swing vs_ frequency.
CA101A AND CA201A
- r--
r-- -
r-
I
'0'"
10' 2 4 &8 102
I
2 468'0 3 2 468'042 4 6810~ 101 2 4 . '101 2 4 1'10' I 4 ' '104 I 4 1'10'
FREQUENCY (f)-Hz FREQUENCY (fl-HI "
fREQUENCYlt)-H,
Fig. 24 - I/f noise voltage vs. frequency. Fig. 25 - Ilf noise current vs. frequency _
Fig. 26 - Common-mode rejection ratio vs_ frequency_
____________________________________________________________________ 21
CA107, CA207, CA307 Types
Maximum Ratings, Absolute-Maximum Values at TA = 25° C:
-;
DC SUPPL Y va L TAGE (Between V+ and V- Terminals):
CA 107, CA207 44 V
CA307 36 V
DC INPUT VOLTAGE ±15 V
(For supply voltages less than ±15 V. the absolute maximum input voltage is equal
to the supply voltage)
DIFFERENTIAL INPUT VOLTAGE. ±30 V
-70 -50 -25
OUTPUT SHORT·CIRCUIT DURATION* Indefinite AMBIENT TEMPERATURE (TAI-"C
'00
'"
DEVICE DISSIPA110N UP TO TA ··700C 500 mW
Above T A = 70 C Derate linearly at 6,67 mW/oC Fig. 4 - Input offset and input bias currents liS.
AMBIENT TEMPERATURE RANGE: ambient temperature.
Operating - CA1C7. -55 °C to +125 °C
CA207, -2SoC to +8S oC"
CA307, aOc to +700C t
-6SoC to +150°C
Storage _. All Types.
LEAD TEMPERATURE lOuring Soldering): ~~iPLY it;!n a-r/~ 1!!lI!!! Hi ~v ":' '}
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 seconds max. I'ii '''-IJ.i.
:T, mJ
flf .u. :1 lill!'!'
:;1 :
.III
4
g " "
*For tyge CA307 continuous short circuit is allowed for Case Temperature to +70o C and ambient temperature
iii rri'<:~
.1. +" IT ' ~' 1" !, I~
to +55 C.
"'Types CA207G. S, and T can be operated over the temperature rangeof -55 to +12SoC,although the published
i tlOHI t
~ I I! 'll
limits for certain electrical specifications apply only over the temperature range of -25 to +8So C. ,g
~ ~:
~ -q p
tTvpes CA307G, E, S. and T can be operated over the temperature range of -55 to +12SoC. alth~ugh the pub- ,,''il ~
lished limits for certain electrical specifications apply only over the temperature range of 0 to 10 C. i1
~
:n
' I
.~ ~
n 'It "
lUi: d~ II IH
u,
'"
OUTPUT CURRENT lIol-mA
Fig. 5 - Output voltage swing vs. output current.
AM81ENT TEMPERATURE (TAJ-2S"C I' t ~: l:;:1 II'!
:!l + -. h j. :.!:;. - +; It-l~I' .j;
0.3 p~
80
10' 2 .. 68 102 2 .. 6 Sial 2 .. 68104 2 .. 68105 o 5 10 15 o 5 10 15
SUPPLY IIOlTAGE(lI t )-V SUPPLY VOLTAGE IV:!:I-V
FAEQUENCY!lI-Hr
Fig. 6 - 1/f noise current vs. frequency. Fig. 7 - Supply current vs. supply voltage. Fig. 8 - Open-loop differential voltage gain liS.
supply voltage.
.I @ ili pt 1::1
'''Hll''H!!:r ',: ::n'".
;: +;
:!!. 1m rnilUi!J;J! i .Hi!I I Hi!L ~•
£ 4: 1;: IIH iiljl!i!lliTit trH
l:Zs't • 1"!
Ii
H
II
•• 1+1
, sol • "0 H,' II
~!'i HI I\J1I II,! i .1
3 rro r!I, t!
~ HI q ~ AMBI:7r~EMPERATURE
,,. 25 ~ ::-: ttHti ~T~~.~~~
.. ,+
, 't' HI i ~ 1:5 • ~ j.
;:: Ii:,
~ t.,
:!!~
+
:i1:
1il
20 '0 70 BO
::i;
::~:
::;:g:1
't!. ,.. t±-. lib ~ I
111 II
A"BIE~T TEMPERATUR£ !TA)--C o to :t10 :!:15 101 2 • 6 8 102 2 4 ' 810l 2 4 & 8 104 2 4 6 8 10,
OUTPUT CURRENT (tel-iliA FREOUENCV(II-HI 92CS-23tI93
Fig. 9 - Input offset and input bias current vs. Fig. 10 - Output voltage swing liS. output current. Fig. 11 - 1If noise current vs. frequency.
ambient temperature.
____________________________________________________________________ 23
CA111, CA211, CA311 Types
Voltage Comparators v+
GND I
For Commercial and Industrial Applications
• INPUT OFFSETI
"G" Suffix Types-Hermetic Gold-CHIP in STROlE
Dual-In- Line Plastic Package 5 INPUT OFFSET
"E" Suffix Types-Standard Dual-In-Line
Plastic Package
"T" and "s" Suffix Types-T0-5 Style Package Functional diagram for plastic package.
v-
Applications NOTE: PIN 4 IS CONNECTED TO CASE
Functional diagriHn for TfJ.5' style packiIIJII,
• Multivibrators
• Positive and negative peak datectors
• Crystal oscillators
~
• Zero-crossing detectors Temp_
• Solenoid, reley, and lamp drivers MaX,VIO Max. 110 Max. liB Package
(mVI Range (TA'
Type (nAI (nAI °c (Suffix I
CA111 3 10 100 -55 to +125 G,S,T
CA211 3 10 100 -25 to +85'"' G,S,T
CA311 7.5 50 250 Oto+70t G,E,S,T
Features
• Single- or dual-supply operation _
• Power consumption - 135 mW at ±15 V
• Strobe capability MAXIMUM RATINGS,AbsolulirMBximum Ve1ueur TA =25"C
• low input-offset current:
CA111, CA211 - 4 nA(typ_1 DC SUPPLY VOLTAGE Ibetween V+ and V- terminal,) . . • . . . . • • • . . . . . . • . . . . . • . . . 36 V
CA311 - 6 nA(typ_1 DC INPUT VOLTAGE* . • . • . . . . . . . . . . . • . . . . • . . . . . . • . • . . . . . . . . • . . • . . ±l5 V
• Differential input-voltage range- - ±30 V DIFFERENTIAL INPUT VOLTAGE . • . . • . . . • . • . . • . . . . • . . . . . . . • . • . • • • . . . ±30 V
• Directly interchangeable with National OUTPUT TO NEGATIVE SUPPLY VOLTAGE IV 7 -4):
Semiconductor LM111, LM211, and CAllI, CA211 . . • . • . . . . . . . . • . • • . . . . . . . • . . . . . . . . . . . . . . . . . . . . • . . 50 V
LM311 Series types CA3" • . . . . . . . • . . . • . . . . . . . . . . . . . • , . . . . . . . . . . . . . . . . . . . . . . . . . . 40V
GROUNDTO NEGATIVE SUPPLY VOLTAGE IV , -41. . . . . . • . . . • . . . . • . . • . . • . . . . . 30 V
OUTPUT SHORT·CIRCUIT DURATION . . • • . . • . . • . • . • • . . . . . . . . • . • . . . . . . . . . 10.
DEVICE DISSIPATION:
Up to T A = 25°C . . • . . . . . . • . . . . . . . . . . . • . • . . . . . • . . . • . . . . . . . . . • . 500 mW
Aboya T A = 25°C . . • . . . • . • • . • • . . . . . • . . • . . • . • . . . . . derate linearly at 6.67 mW/oC
The RCA-CA111, CA211, and CA3l1 are
AMBIENT TEMPERATURE RANGE:
monolithic voltage comparators that operate
Operating:
from dual supplies up to ±15 V, or from
CAllI . . . . . . . . • . . . . . • . . . • . . . . • . . . . . . . . . . • • . . . . . . . . . . -55to+1250C
single supplies down to 5 V. This single-
CA211 . . . . . • . . . . . . • . . . • . . . . • . . . . . . . . . . . . . . . . . . . . . . . . -25 to +B5°()6.
supply capability makes the outputs of these
CA311 . . . . . . . . . . • . . . • . . . . . . . . . . • . . • . . . . . . . . . . . . . . . . . . 0 to +70oC t
devices compatible with RTL, DTL, TTL,
Storage, all typas • . . . . . . . . • . . . . . . . . . . . . . • . . . . . . . . . . . . . . . . . -65 to +150oC
and MOS circuits. In addition, they can drive
LEAD TEMPERATURE IDURING SOLDERING):
lamps or relays, and switch voltages up to
At distance 1/16 ± 1/32 in. 11.59 ±0.79 mm)
50 V (CA311, 40 VI at currents as high as
from ca.. for 10 IOCOnds mex. . . . . . . . . . . . . • . . . . . • . . . . . . . . • . . . . . . .. +2650C
50mA.
The inputs and the outputs of the CA 111, *This rating appli .. for ±l5 V supplies. The positive Input·voltage limit i. 30 V above the negative supply.
CA211, and CA311 can be isolated from The negative input..yoltage limit is equal to the negative supply voltage or 30 V below the positive supply.
system ground, allowing the output to The negative input·yoltage limit is equal to the negative supply voltage or 30 V below the positive supply.
drive loads referred to ground, V+, or V-. whichever is less.
All types are available in hermetic gold-CHIP
dual-in-line plastic packages (G suffix I, 8- .. Types CA211G,S, and T can be operated over the temperature range of -55 to +125°C,
lead T0-5 style packages with standard leads although the published limits for certain electrical specifications apply only over the temper-
(T suffix), and with dual-in-line formed leads ature range of -25 to +85°C.
("OIL-CAN", S suffix). The CA311 is also
available in the 8-lead dual-in-line plastic t Types CA311G,E,S and T can be operated over the temperature range of -55 to +125°C,
package ("MIN~ DIP",E suffixl, and in chip although the published limits for certain electrical specifications apply only over the temper-
form (H suffix I. ature range of 0 to 70°C.
____________________________________________________________________ 25
CA111, CA211, CA311 Types
ELECTRICAL CHARACTERISTICS TYPICAL CHARACTERISTICS - CA111,
TEST CONDITIONS LIMITS CA211 (CONT'D)
CHARACTERISTICS SUPPLY VOLTAGE IV:!I-15 V ~n CA3" UNITS
UNLESS OTHERWISE SPECIFIED
TYP. MAX. TYP. MAX.
,TA~2SoC
Input Offset
R • .;;;; S k n , Note 2 0.7 3 2 7.S
mV
Voltage, V 10 Not. 1 - 4 - 10
VI = -SmV,lo = SOmA
T A =2SoC 0.7S 1.5 - -
IForCA3",VI ';;;;-10mVI
V
Saturation Voltage V+ ;;o4.S V, V =0, VI';;;; -6 mV,
ISINK ';;;;BmA Not. 1 0.23 0.4 - -
IForCA31',VI ';;;;-IOmVI
Input Voltage
Range, VIPP Note 1 ±14 - ±14 - V
DIFFERENTIAL INPUT VOLTAGE ,IIIIOI-V
Fig. 10 - Input characteristcs.
Input Off••t ~oC 4 10 6 SO
nA
[Link], 110 Note 2 Not. 1 - 20 - 70
REFERRED TO SU....Ly VOLTAGI$
Input Bias TA=2SoC 60 100 100 250
Current, liB Not. 2 nA
Note 1 - ISO - 300
[Link] Supply
Current, 1+ TA = 25°C 5.1 6 5.1 7.5 mA
Nagative Supply TA=2SoC
Current 1- 4.1 S 4.1 5 mA
Output Leakage
Current
VI;;o5 mY. Vo = 35 V
IFor CA31', VI;;o -10mVI
TA=25 C 0.2 10 - - nA
Not. 1 0.1 0.5 - - /JA
Strobe On Current TA=25 u C 3 - 3 - mA y-
-150 ·215 0 215 150 ." 100 125
Voltage Gain, A TA=25OC 200 - 200 - V/mV AMIIENT TEMPERATURE. (TA1.--C 'IICI-M~'O
Fig. 11 - Commo&mode voltage range limits
Response Time 100 mV Input Step with
TA=250C 200 - 200 - ns vs. ambient temperature.
5 mV overdrive voltage
10
Note 1: Ambient temperature ITA) over applicable operating temperature range as shown
below. NORMAL OUTPUT
LOAD RESISTANCE (RU"IIiA
CAlll CA211 CA311
=
w
O
~>~
40
E. ..TTER-FOLLOWER
OUTPUT
Y7-4"SO V
-55 to +125°C -25 to +85°C o to +70 oC '0 RL"eoOA
Note 2: The input offset characteristics given are the values required to drive the output to
within 1 V of either supply with a l·mA load. These characteristics define an error '0
band which takes into account the worst·case effects of voltage gain and input
-0.5 0 0.5
impedance. The input offset voltage, input offset current, and input bias current OIFfERENTIAL INPUT VOLTAGE IVIOI-rnV
specifications apply for any supply voltage from a 5 V single supply up to a ±15 V
dual supply. Fig. 12 - Transfer function.
SUPPLYVOlTAGEIII.)a,SV t 11lln~ i~~:I;
:. '1!! ~ ::::
'0
d;'Hn :::1 " ..
POSITIVE SUPf'lY-
OUTPUT HIGH
POSITIVE AND NEGATIVE SUPPLY-
OUTPUT LOW
OUTPUT CURRENT 1:101-.'-
-'0 -2' !SO
.W.I£NT TEIIIPERATURF 11&1-·C
'00 8 ~ • •
AMBIENT [Link] ITai-"C
~
Fig. 13 - Output saturation lIo/rage vs. Fig. 14 - Supply current vs. [Link] Fig. 15 - Input and output leakage current
output current. temperature. vs. ambient temperature.
___________________________________________________________________ 27
CA124, CA224, CA324 Types
"E" Suffix Types: Standard Dual-In-Line
Quad Operational Amplifiers Plastic Package
"G" Suffix Types: Hermetic Gold-Chip
For Commercial, Industrial, and Military Applications Dual-In-Line Plastic Package
The RCA-CA 124, -CA224, and -CA324 con- (single-supply operation) make the CA124,
sist of four independent, high-gain opera- CA224, and CA324 suitable for battery Features:
tional amplifiers on a single monolithic operation. • Operation from single or dual supplies
substrate. An on-chip capacitor in each of the The CA124, CA224, and CA324 are supplied • Unity-gain bandwidth. . . . . . 1 MHz (typ.)
ampl ifiers provides frequency compensation in a 14·lead dual-in-line plastic package (E • DC voltage gain . . . . . . 100 dB (typ.)
for unity gain. These devices are designed suffix), or in a hermetic gold-chip 14-lead • Input bias current . 45 nA (typ.)
specifically to operate from either single or dual-in-line plastic package (G suffix) to pro- • Input offset voltage 2 mV (typ.)
dual supplies, and the differential voltage vide true hermetic performance. The CA324 • Input offset current 5 nA (typ.)
range is equal to the power-supply voltage. is also available in chip form (H suffix). and tor CA224, CA324
low power drain and an input common- as a hermetic gold-chip (HG suffix). 3 nA (typ.) for CA124
mode voltage range of from 0 V to V+ -1.5 V • Replacement for industry types 124,224,324
MAXIMUM RATINGS,Abso(ute-Max;mum Va(uesat TA = 25°C
Applications
SUPPLY VOLTAGE 32Vo,±16V
DIFFERENTIAL INPUT VOLTAGE. ±32 V • Summing amplifiers
INPUT VOLTAGE . . . . • . -0.3 V to +32 V
INPUT CURRENT IV I <-0.3 V)t . 50mA
• Multivibrators
OUTPUT SHORT CIRCUIT TO GROUND • Oscillators
IV+ ';;;15 V)* Continuous • Transducer amplifiers
DEVICE DISSIPATION:
Up to T A = 55°C 750mW • DC gain blocks
Above T A = 55°C . derate 1inearly at 6.67 mW/oC
AMBIENT TEMPERATURE RANGE:
Operating. -55 to +125 0 C
Storage -65 to + 150°C
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1116 ± 1132 in. 11.59 ±0.79 mml
from case for 10 seconds max. NEG
INPUT I
pos
INPUT I
*The maximum output current'is approximately 40 rnA independent of the magnitude of V+. Continuous
>
short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short, circuits
from the output to V+ can cause overheating and eventual destruction of the device. pos
INPUT 2
tThis input current will only exist when the voltage at any of the input leads is driven negative. This current
is due to the collector·base junction of the input p·n-p transistors becoming forward biased and thereby
acting as input diode clamps. In addition to this diode action, there is also lateral n·p·n paraSitic transistor
action on the Ie chip. This transistor action can cause the output voltages of the amplifiers to go to the 92CS-24204
V+ voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. TOP VIEW
This transistor action is not destructive and normal output states will re-establish when the input voltage,
Fig. 1 - Functional diagram.
which was negative, again returns to a value greater than -0.3 V dc.
Fig. 2-Schematic diagram-one of four operational amplifiers.
_________________________________________________________________ 29
CA124, CA224, CA324 Types
TYPICAL CHARACTERISTICS CURVES
••
~~o
AMBIENT TEMPERATURE
INPUT COMMON-MODE VOLTAGE
RANGE CYICR)-OY f---f--ITAI·2~·C _
415'1
I "n
~~.,.:
jl
. ,.
z
~
:"
- ~
ISV
1\
SV ~ ,
AMBIENT TEMPERATURE (TAJ-
o
~ '\
TO +125-C ~
_ ~ ~ 0 e
AMBIENT TEMPERATURE (TA)--':
~ ~ ~ ~ o 1015202530
_ ·c
SUPPLY VOLTAGE (Y+)-Y
, . .. ,
FREQUENCY
. , .I'-..... , . ..
(IJ-H~
Fig. 3-/nput current VI. ambient temperature. Fig. 4-Supply current drain vs. supply tloltage. Fig. 5-Large-signal frequency response.
1
I
~ [Link] RESISTANCE IR,,.I-20Ilil
~
t
! ..n
il!
Ii '"
I
20
..
-flO -2!I 2~ $0 7~
,. to
AMBIENT TEMPERATURE CTA I-'C
• HCS-2<1:roe SUPPL.Y [Link] ('1+)-'1
Fig. 6-0utput current VI. ambient temperature. Fig. 7-/nput ;;urrent VI. supply tlo/tage. Fig. 8- Voltage gain vs. supply voltage.
~IENT TEMPERATURE: (TA)-2S-C
SUPPLY VOLTAGE CY+)-30Y
~
I~
~ ,~ IVo J t' ,.
i :t--t--t' ~
g y
VI
• 50".:r
- --,
.~T,: •
- .:l:l
tt
'"
~ 4Of--+-+--I~~ ~
i 1.1--1--1--+--+-~"" 0
•
OUTPUT
10 n 1011 10011 ,.M 0 I
• • 4 •
an
TIM[(t)-,..
FREQUENCY III-H,
Fig. 9-Open-/oop frequency response. Fig. 10-Voltage follower pulse response Fig. 11- Voltage follower pulse response.
(small signal).
____________________________________________________________________ 31
CA139, CA239, CA339 Types
ELECTRICAL CHARACTERISTICS TYPICAL CHARACTERISTICS (Cont'd)
TEST CONDITIONS LIMITS
V+-5V CA139 CA139A
CHARACTERISTIC UNITS 1 -~·c
Unless otherwise
indicated Min. Typ. Max. Min. Typ. Max.
? .0
.....IENT TEMPERATURE (TA)-O-C
Input Offset a 40
2'·C
Voltage (ViOl VREF =
2SoC - 2 5 - 1 2
~ 30 7 C
mV !;
At Output Switch 20
Point V "" 1.4 V
1.4 V,RS = 0 Note 1 - - 9 - - 4 ~
10
Keep all inputs ~O V
Differential Input
Voltage (VIOl
for V- (If usedl, - - 36 - - 36 V 10 20 30 40
Notes 1,2 SUPPLY VOLTAGE (V1')-V
VI = 1 V, Fig. 4-lnput current vs. suPPIv voltage.
Saturation Voltage VI+=OV,
25°C - 250 500 - 250 500
(V sat ) mV
ISINK .;;
4mA
Note 1 - - 700 - - 700
Common·Mode
Input Voltage Note 3
25 0 C 0 - V+-1.5 0 - V+-l.5
V
Range (VICR)
Note 1 0 - V+-2 0 - V+-2
Input Offset
11+- 11-
2SoC - 3 25 - 3 25
nA
Current (1101 Note 1 - - 100 - - 100
II+or 11-
Input Bias Current with Output
25°C - 25 100 - 25 100
nA
(lIBI in Linear
Range
Note 1 - - 300 - - 300
TIME (11-,.5
R L - 00 on all com·
Supply Current (1+)
parators, T A = 25°C
- 0.8 2 - 0.8 2 mA Fig. 5-Response time for various input
overdrives-negative transition.
VI+~l V,
VI-=O, 25°C - 0.1 - - 0.1 - nA
Output Leakage Vo = 5 V
Current VI+~l V,
VI-'=O, Note 1 - - 1 - - 1 J1A
Vo = 30 V
VI ~1 V,
Output Sink VI+=O,
Current VO';;+1.5V,
6 16 - 6 16 - mA
TA = 25°C
RL ~lS kG;.t+=15 V,
Voltage Gain (AOLI
TA = 25°C
- 200 - 50 200 - V/mV
VI = TTL Logic
Fig. 6-Response time for lIarious input
Swing, VREF = overdrives-positille transition.
Large Signal
Response Time
+1.4 V,VRL = 50 V, - 300 - - 300 - ns
RL = 5.1 kG,
TA = 25°C
VRL =5V,
Response Time
See Figs. 5 & 6
RL =5.1 kG, - 1.3 - - 1.3 - J1S
TA = 250 C
Note 1: Ambient Temperature (T A) applicable over operating temperature range as shown below.
CA139 (-55 to +125 0 CII CA239 (-25 to +85 0 CII CA339 (0 HOoCI
CA139A CA239A CA339A to
Note 2: The comparator will provide a proper output state even if the positive swing of the inputs exceeds
the power supply voltage level. if the other input remains within the common-mode voltage range.
The low input voltage state must not be less than -0.3 V (or 0.3 V below the magnitude of tha
negative power supply, if used).
OUTPUT SINK CURRENT !Iol-mA
Note 3: The upper end of the common-mode voltage range is (V+J - 1.5 V. but either or both inputs can
go to +30 V without damage.
Fig. 7-0utput saturation voltage vs. output sink
current.
__________________________________________ ~ ________________________ 33
CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
Dual Operational Amplifiers Features:
• Internal frequency compensation for unity gain
For Commercial, Industrial, and Military [Link] • High dc voltage gain - 100 dB typo
• Wide bandwidth at unity gain - 1 MHz typo
The RCA-CAI58, -CAI58A, -CA258, supply current is basically independent of • Wide power supply range:
-CA258A, -CA358, -CA358A, and CA- the supply .voltage over the recommended Single supply . 3 to 30 V
2904 types consist of two independent, high voltage range. Dual supplies. ± 1.5 to ± 15 V
gain, internally frequency compensated op- These devices are particularly useful in in- • Low supply current - 1.5 mA typo
erational amplifiers which are designed speci- terface circuits with digital systems and can • Low input bias current
fically to operate from a single power supply be operated from the single common 5 Vdc
over a wide range of voltages. They may also • Low input offset voltage and current
power supply. They are also intended for
be operated from split power supplies. The transducer ampl ifiers, dc gain blocks and • Input common-mode voltage range
includes ground
• Differential input voltage range equal to
V+ range
MAXIMUM RATI NGS, Absolute-Maximum Values at TA = 2!PC • Large output voltage swing - 0 to V+
SUPPLY VOLTAGE, v+: -1.5V
CA2904. 26 Vor ±13 V
Other Types 32Vor±16V
DIFFERENTIAL INPUT VOLTAGE:
CA2904 ±26V
Other Types ±32V many other conventional op amp circuits
INPUT VOLTAGE -0.3 V to V+ V which can benefit from the single power
INPUT CURRENT IVI <
-0.3 V) + 50mA supply capability.
OUTPUT SHORT CIRCUIT TO GROUND The CA158, CA158A, CA258, CA258A,
IV+ ';;;15 V)* Continuous CA358 and CA358A types are supplied in
DEVICE DISSIPATION: hermetic gold-CHIP 8-lead dual-in-line plastic
Up to T A = 55°C . 630mW packages (G suffix), 8-lead TO-5 style pack-
Above T A = 55°C. derate linearly at 6.67 mW/oC ages with standard leads (T suffix). and
AMBIENT TEMPERATURE RANGE: with dual-in-line formed leads (01 L-CAN, S
Operating . -55 to + 125°C suffix). The CA2904 is supplied only in the
Storage. ...fl5 to + 150°C gold-CHIP plastic package (G suffix).
LEAD TEMPERATURE (During Soldering):
The CA 158, CA 158A, CA258, CA258A,
At distance 1116 ± 1132 in. 11.59 ± 0.79 mm)
CA358, CA358A, and CA2904 types are an
from case for 10 seconds max.
equivalent to or a replacement for the in-
dustry types 158, 158A, 258, 258A, 358,
358A, and 2904.
+ This input current will only exist when the voltage at any of the input leads is driven negative. This current
is due to the collector-base junction of the input p-n-p transistors becoming forward biased arid thereby act-
ing as input diode clamps. In addition to this diode action, there is also lateral n-p-n parasitic transistor ac-
tion on the Ie chip. This transistor action can cause the output voltages of the amplifiers to go to the V+
voltage level (or to ground for a large overdrive) for the time duration that an input is driven negative. This
transistor action is not destructive and normal output states will re~establish when the input voltage, which
was negative, again returns to a value greater than -0.3 V dc.
TOP VIEW
* The maximum output [Link] is approximately 40 rnA independent of the magnitude of V+. Continuous
>
short circuits at V+ 15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of the device. Destructive dissipa'
tion can result from simultaneous short circuits on both amplifiers.
r-__~________~~__~__~__~____~~T02
Fig.2 - Functional diagram for CA 158, CA258.
~
. and CA358 S- and T-suffix types.
2 7
6 -
'sc
I Vo
~---+--~--~~~----~~----~~--~----~_T02
92CM-29:>69 92CS-25015
Fig.3 - Functional diagram for CA 158, CA258,
Fig. 1- Schematic diagram - one of two operational amplifiers. CA358, and CA2904 G-suffix types.
----------------------------------------------~----------------------~
CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
AMBIENT TEMPERATURE ITAloZ5"C
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)
~
I ISO
~ 125 LOAD RESISTANCE (Rd" 20ka
TEST CONDITIONS LIMITS 111
an
CHARACTERISTIC CA258A (G, T, SI UNITS
Supply Vol1Bge (V+) = 5 V
Unless Otherwise Specified Min. Typ. Max.
TA = 250 C
Input Offset Voltage, VIO Note 3 - 1 3 mV
20
Output Voltage Swing, VOpp RL = a n 0 - V+ -1.5 V SUPPLY VOLTAGE (V+I-V
Input Common·Mode Fig.S - Voltage gain as a function of
Voltage Range, VICR
Note 2, V+ = 30 V 0 - V+ -1.5 V
supply voltage.
Input Offset Current, 110 11+ -II - 2 15 nA
Input Bias Current, liB II+or II ,Note 1 - 40 80 nA 140 n
,~,--t------H~
VI+=+l V, VI-=OV,
Output Current (Source l. 10 20 40 - mA
V+= 15 V
VI+=O V, VI-= 1 V, V+=15 V 10 20 - mA !
Output Current (Sink), 10 VI+=O V, VI-= 1 V, ~
12 50 - /lA ~ 60f--+---J-'
Vo=200mV
~
Short Circuit Output Current R L = 0 (to Ground) Note 4 - 40 60 mA
RL;;'2 kn, V+: 15 V
i 20f--+--1---+-~-~~
Large Signal Voltage Gain, AOL 50 100 - V/mV
(For large Vo swing)
'0 '00 10k lOOk 'OM
Common-Mode Rejection FREQUENCY (fl-Hz
Ratio, CMRR DC 70 85 - dB
Fig.9 - Open-loop frequency response.
Power' Supply Rejection
Ratio, PSRP DC 65 100 - dB
Amplifier-to-Amplifier
Coupling
f = 1 to 20 kHz (Input referred) - -120 - dB AMBIENT TEMPERATURE ITA '-2S·C
SUPPLY VOLTAGE (V+l-15V
LOAD RESISTANCE (RL'-2kn
T A = -25 to +85 0 C
Input Offset Voltage, VIO Note 3 - - 4 mV
Temperature Coefficient of
Input Offset Voltage,"'VIO Rs =0 - 7 15 /lV/oC
Input Offset Current, 110 It-II- - - 30 nA
Temperature Coefficient of
Input Offset Current, "'110 - 10 200 pAloC
Input Bias Current, liB II+or 11- - 40 100 nA
~S-lI4l1n
Input Com~on-Mode Fig. 10 - Voltage follower pulse response.
Voltage Range, VICR V+ = 30 V, Note 2 0 - V+-2 V
RL =co On All Amp!. - 0.7 1.2
Supply Current, 1+ mA
RL =co, V+ = 30 V - 1.5 3
AMS lENT TEMPERATURE (TA).2~.C
SU~ PLY VOLTAGE (Y+).30 V
NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output. ~ I.
tt
V,~
NOTE 2: The input signal voltages and the input common-mode voltage should rrot be allowed to go negative by /"""
more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V. but either or both
9
IVo
i1 I
inputs can go the + 32 V without damage. "j- +-
NOTE 3: Va = 1.4 VOC. Rs = 0 n with V+ from 5 V to 30 V, and over the full input common-mode voltage range
~
g40C
+
-I
50pF
:INPUT'"
(0 V to V+ - 1.5 V).
5 l •+
.. U
NOTE 4: The maximum output current is approximately 40 rnA independent of the magnitude of Vi. Continuous ~~ ,
short circuits at V+ >15 V can cause excessive power dissipation and eventual destruction. Short circuits
300
~TPUT
t ,. , FT
from the output to V+ can cause overheating and eventual destruction of the device. Destructive dissi-
pation can result from simultaneous short circuits on both amplifiers.
0 1 2 3
t.
4 • 6
ej..t;.
gW 9
TIME (1)-,..
Fig. 11 - Voltage follower pulse response
(small signa/).
______________________________________________________________________ 37
CA158, CA158A, CA258, CA258A, CA358, CA358A, CA2904 Types
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)
.
..
60
LIMITS I
~
CHARACTERISTIC
TEST CONDITIONS
Supply Voltage (V+) = 5 V
CA158 (G, T, S)
CA258 (G, T,S) UNITS ~
! .. J
Unless Otherwise Specified Min. Typ. Max. ~ ,.
TA=250C
a 2.
- ~ ,. I
.-,.
Input Offset Voltage, VIO Note 3 2 5 mV
Output Voltage Swing, VOPP
Input Common-Mode
RL = 2 kn
Note 2, V+ =30 V
0
0
-
-
V+ -1.5
V+ -1.5
V
V
-00
-" ." ,. ".
AMBIENT TEMPERATURE (TA}--t
100
'"
92CS-2420B
Voltage Range, VICR Fig. 16 - Output current as a function of
Input Offset Current, 110 11+-11 - 3 30 nA ambient temperature.
Input Bias Current, liB 11+ or II ,Note 1 - 45 150 nA
VI+=+1 V, VI-=O V,
Output Current (Source). 10 20 40 - mA
V+= 15 V
VI+=O V, VI-= 1 V, V+=15 V 10 20 - mA
Output Current (Sink), 10 VI+=O V, VI-= 1 V,
12 50 - p.A
Vo=200mV
Short Circuit Output Current R L = 0 (to Ground) Note 4 - 40 60 mA
RL;;' 2 kn, V+ = 15 V
Large Signal Voltage Gain, AOL
(For large Vo swing)
50 100 - V/mV
Common-Mode Rejection
Ratio, CMRR DC 70 85 - dB
Power' Supply Rejection
Ratio, PSRR DC 65 100 - dB
Amplifier-to-Amplifier -
Coupling
f = 1 to 20 kHz (Input referred) - -120 dB
TA = -55 to + 125°C (CA158); TA = -25 to +850 C (CA258)
Input Offset Voltage, VIO Note 3 - - 7 mV
Temperature Coefficient of
Input Offset Voltage,o:VIO Rs = 0 - 7 - p.V/oC
Input Offset Current, 110 11+-11- - - 100 nA
Temperature Coefficient of
Input Offset Current, 0:110 - 10 - pA/oC
Input Bias Current, liB II+or 11- - 40 300 nA
Input Common·Mode
Voltage Range, VICR V+=30V,Note2 0 - V+-2 V
RL = 00 On All Ampl. - 0.7 1.2
Supply Current, 1+ mA
R L = 00, V+ = 30 V - 1.5 3
NOTE 1: Due to the p-n-p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant, independent of the state of the output.
NOTE 2: The input signal voltages and the input common-mode voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common~mode voltage range is V+ - 1.5 V, but either or both
inputs can go the + 32 V without damage.
NOTE 3: Vo "" 1.4 Voe. Rs "" 0 n with V+ from 5 V to 30 V. and over the full input common~mode voltage range
(OV,oV+-l.5V).
NOTE 4: The maximum output current is approximately 40 mA independent of the magnitude of Vi-. Continuous
short circuits at V+ >15 V can cause excessive power dissipation and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of the device. Destructive dissi~
pation can result from simultaneous short circuits on both amplifiers.
__________ ~ _____________________________________________________________ 39
CA158, CA158A~ CA258, CA258A, CA358, CA358A, CA2904 Types
ELECTRICAL CHARACTERISTICS (Values Apply for Each Operational Amplifier)
TEST CONDITIONS LIMITS
CHARACTERISTIC CA2804G UNITS
Supply Vol.... 1v+1 • 5 V
Unl. . Otherwise Specified Min. Typ. Ma.
TA = 25°C
Input Offset Voltage. VIO Note 3 - 2 7 mV
Output Voltage Swing, VOpp RL:'> 10kfl 0 - V+ -1.5 V
Input Common·Mode
Voltage Range, VICR Note 2, V+ =30 V 0 - V+ -1.5 V
Input Offset Current, 110 11+ -II - 5 50 nA
Input Bias Current, liB 11+ or II ,Note 1 - 45 250 nA
VI+=+1 V, VI =OV,
Output Current (Source),lo 20 40 - mA
V+= 15 V
Output Current (Sink), 10 VI+=O V, VI-= 1 V. V+=15 V 10 20 - mA
Short Circuit Output Current RL = 0 (to Ground) Note 4 - 40 60 mA
RL:'>2kfl, V+= 15 V
Large Signal Voltage Gain, AOL
(For large Vo swing)
- 100 - V/mV
Common-Mode Rejection
Ratio, CMRR DC 50 70 - dB
Power" Supply Rejection
Ratio, PSRR DC 50 100 - dB
Amplifier·to-Amplifier
Coupling
f = 1 to 20 kHz (lnputreferred) - -120 - dB
TA = -40 to + 850C
Input Offset Voltage, VIO Note 3 - - 10 mV
Temperature Coefficient of
Input Offset Voltage,a:VIO Rs = 0 - 7 - /lV/oC
Input Offset Current, 110 j 11+-11- - 45 200 nA
Temperature Coefficient of
Input Offset Current, 0:110 - 10 - pAloC
Input Bias Current, liB 11+ or II - 40 500 nA
Input Common-Mode
Voltage Range, VICR V+ = 30 V. Note 2 0 - V+-2 V
RL = 00 On All Amp!. - 0.7 1.2
Supply Current, 1+ mA
RL = 00, V+ = 30 V - 1.5 3
NOTE 1: Due to the p·n~p input stage the direction of the input current is out of the IC. No loading change exists
on the input lines because this current is essentially constant. independent of the state of the output.
NOTE 2: The input signal voltages and the input common-moqe voltage should not be allowed to go negative by
more than 0.3 V. The positive limit of the common-mode voltage range is V+ - 1.5 V. but either or both
inputs can go the + 32 V without damage.
NOTE 3< Vo = 1.4 Voe, As = 0 n with V+ from 5 V to 30 V, and over the full input common·mode voltage range
(0 V to V+ - 1.5 VI.
NOTE 4: The maximum output current is approximately 40 rnA independent of the magnitude of V·. Continuous
short circuits. V+ ::>15 V can cause excessive power dissipatiorl and eventual destruction. Short circuits
from the output to V+ can cause overheating and eventual destruction of thedevice. Destructive dissi-
pation can result from simultaneous short circuits on both amplifiers.
________________________________________________________________ ~ ____ 41
CA555, CA555C Types
ELECTRICAL CHARACTERISTICS, At TA =2!PC, vr =5 to 15 V unless otherwise specified
150
LIMITS
CHARACTERISTIC TEST CONDITIONS CA555 CA555C UNITS I
Min. Typ. Max. Min. Typ. Max.
.00
~ ~E.\~
..
,.~
!J~ C
1 ,,,,#"':' lJt#t !
DC Supply Voltage, ~.,
V+ 4.5 - 18 4.5 - 16 V '~l~ c
50
1"r.'",:S:
V+ = 5 V. : .\2. c
RL = 00 - 3 5 - 3 6 mA
DC Supply Current
(LowState)*.I+ V+ = 15 V.
c{tt1HII
MINI~LM TRIGGER ~;ULSEI VOLT,!>oi IIlV+) * 0.4
RL = 00 - 10 12 - 10 15 mA *WHERE • IS THE DECIMAL MU .... TIPLIER OF THE SUPPLY VOLTAGE
Threshold Voltage.
Fig. 4 - Minimum pulse width vs. minimum
VTH - (2/3)V+ - - (2/3)V+ - V
trigger voltage.
Trigger Voltage
V+ = 5 V 1.45 1.67 1.9 - 1.67 - V
V+ = 15 V 4.8 5 5.2 - 5 -
Trigger Current - 0.5 - - 0.5 - /J. A
Threshold Current....
ITH - 0.1 0.25 - 0.1 0.25 JJ.A
Reset Voltage 0.4 0.7 1.0 0.4 0.7 1.0 V
Reset Current - 0.1 - - 0.1 - mA
Control Voltage V+ = 5V 2.9 3.33 3.8 2.6 3.33 4 V (
9.6 10 V iil
Level V+ = 15 V 10.4 9 10 11
V+ = 5V
ISINK = 5 mA
- - - - 0.25 0.35
V
ISINK = 8 mA - 0.1 0.25 - - -
Output Voltage V+ = 15 V
Drop: ISINK = 10mA
- 0.1 0.15 - 0.1 0.25 Fig. 5 - Supply current vs. supply voltage.
Low State. VOL
ISINK = 50 mA - 0.4 0.5 - 0.4 0.75
I '
TEMJERALRE! (Tll.-55.~
V
ISINK = 100 rnA
ISINK = 200 mA
-
-
2.0
2.5
2.2
-
-
-
2.0
2.5
2.5
- f I.'
0
AMBILT
I ; +;t5-C
ill
--r--r:V
~ !
V+ = 5V
~ I., I
3.0 3.3 - 2.75 3.3 -
ISOURCE = 100 mA ~ J- ~ !---
High State. VOH V+ = 15 V V ~ 0 .•
~
ISOURCE = 100 mA 13.0 13.3 - 12.75 13.3 -
~ i I
ISOURCE = 200 mA - 12.5 - - 12.5 - 0.'
J
rpPI
:
t+I.5v:!'1
I
Timing Error
(Monostable) :
I nitial Accuracy
Rl, R2
= 1 to 100 kil
- 0.5 2 - 1 - %
~ 0
, .,.
LY rLTAGE
.0
SOURCE CURRENT I ISOURCE)- rnA
, ,
V+:!'115V
.
1
.
'00
Frequency C = 0.1 /J.F
p/m/ Fig. 6 - Output voltage drop (high state) vs.
Drift with Tested at - 30 100 - 50 - °C source current.
Temperature V+ = 5 V,
Drift with Supply v+ = 15 V - 0.05 0.2 - 0.1 - %/V
Voltage
Output Rise Time. tr - 100 - - 100 - ns
Output Fall Time, tf - 100 - - 100 - ns
• When the output is in a high state, the dc supply current is typically 1 mA less than the
low·state value .
.... The threshold current will determine the sum of the values of Rl and R2 to be used in
Fig. 16 (astable operation): the maximum total Rl + R2 = 20 Mil.
.0
SINI( CURRENT !:lSINICI-mA
Fig.7 - Output voltage-low state vs. sink current
atV+=5V.
____________________________________________________________________ 43
CA555, CA555C Types
v ~ " I1!i
I I I I I I
.
2
~ I~~---P~--~---f~--+----+----~
I I I I I I
-I-' f-' f-' I-' f-' u .t
~
4
3.3 v -
1\ 1\ \ 1\ 1\ \ "
w
u
Z 2
1.1 v - f-" ;'! 0.1
~
~
:
.
2
O~~F_----t----f~--~~-f~--~~~
Top Trace: Output voltage (2V/div. and 2
0.5 msldiv'! 0·001
Bottom Trace: Capacitor voltage (1 VI
div. and 0.5 ms/div.)
Fig. 17 - Tvpical waveforms for repeat Fig.1S - Free running frequency of repeat cycle timer
cycle timer. with variation in capacitance and resistance.
____________________________________________________________________ 45
CA723 Types
ELECTRICAL CHARACTERISTlCS8t TA· 25C, y+. VC· VI-12V, V-a 0, YO· 5 V, TYPICAL CHARACTERISTICS
IL -1 mAo C1 -100 pF, CREF· 0, RSCp· 0, unless otherwise specified. Divider CURVES FOR TYPE CA723
impadloMe R1R2 R,+R2 8t non-inverting input, Term.S, ·'0 kn 1_ Fig. 23).
MAX JUNCTION TEMP. ITJ j"150·C
LIMITS THERMAL RESISTANCE o150·C/W
CHARACTERISTIC TEST CA723 CA723C UNITS ~ .'" QUIESCENT DISSIPATION IPQ)60mW
r i O HEAT SINK)
CONDITIONS Min. Typ. 1
Max. Min Typ. Max.
Quiescent Regulator IL = 0,
"
Current, 10 VI = 30 V - 2.3 3.5 - 2.3 4 rnA i
B
.DC
Input Voltage
Range, VI
Output Voltage
9.5 - 40 9.5 - 40 V ..
~
, '0
Range, Vo 2 - 37 2 - 37 V
~
0
Differential Input- 0 .0 20 50 40
Output Voltage, DIFFERENTIAL INPUT-OUTPUT VOLTAGE IVI-VO I-V
VI-VO 3 - 38 3 - 38 V
Fig. 5 - Max. load current VB differential input-
Reference Voltage, output voltage.
VREF 6.95 7.15 7.35 6.8 7.15 7.5 V
VI = 12
t04DV - 0.02 0.2 - 0.1 0.5
VI = 12
to 15V - 0.01 0.1 - 0.01 0.1
VI = 12
Line Regulation to 15V, %VO
(See Note 1) TA = -55 to
+125"C - - 0.3 - - -
VI = 12
to 15 V.
TA = Oto
70"C - - - - - 0.3 OUTPUT CURRENT (lOI-mA
IL = 1
to 50 rnA -' 0.03 0.15 - 0.03 0.2
Fig. 6 - Load regulation without current limiting.
IL = 1
to 50 rnA,
TA = -55 to
Load Regulation
(See Note 1)
+125"C - - 0.6 - - - %VO
IL = 1
to 50 rnA,
TA =0
to 70"C - - - - - 0.6
Output-Voltage TA = -55
to +125°C - 0.002 0.Q15 -
Temp. CoeffiCient,
- -
%fc
AVO TA = 0
to 70°C - - - - 0.003 0.Q15
f = 50 Hz
OUTPUT CURRENT (lOI-mA
to 10 kHz - 74 - - 74 -
Ripple Rejection dB
f=50 Hzto Fig. 7 - Load regulation with current limiting.
(See Note 2)
10kHz,
CREF = 51'F - 86 - - 86 -
Short-Circuit
limiting Current, RSCp = 10 n,
ILiM
Vo = 0 - 65 - - 65 - rnA
BW 100 Hz
to 10 kHz,
Equivalent Noise RMS CREF = 0 - 20 - - 20 -
Output Voltage. VN I'V
(See Note 2) BW = 100 Hz
10 kHz,
CREF = 51'F - 2.5 - - 2.5 -
Note 1: Line and load regulation speCifications are given for condition of a constant chip
temperature. For high-dissipation conditions, temperature drifts must be sepa- OUTPUT CURRENT !.IO l-mA
rately taken into account. Note 2:· For CREF. see Fig. 23.
Fig. 8 - Load regulation with current limiting.
______________________________________________________________________ 47
CA723 Types
'0,6 INPUT "OLTAGE l"I'.12"
2 468 2 .. 68 2 .. 68 2 468
100 Ik I k 10k 1M
TIM[ Itl-,.. FREQUENCY III-HI 92CS.24177
Fig. 21 - Load transient response. Fig. 22 - Output impedance vs. frequency.
TYPICAL APPLICATION CIRCUITS
'st_
",C"'"'''R£''NITT-o'V'v'''''-R~8i'~elED
CA723 LIM.
CA723C
NON
IN"·
INPut
CIRCUIT PERFORMANCE DATA: CIRCUIT PERFORMANCE DAtA:
CIRCUIT PERFORMANCE DATA:
REOULATEDQUTPUTVOLTAGE • REGULATEOOUTf'UTVOLTAGE .
REGULATIEDOUTPUTVOLTAGE . . • -15 V
LlNEREOULATKJNfAYI-3VI • • • • lUI mY LINE REGULATION ~VI· 3 VI • • • • 1.5 mV
LlNEREGULATlONlt,vI'"3VI. . 1 mV
LOADREQULATtON!.AIL-IIGIIIA!• • • 1.& mY LOAD REGULATION ~IL" 50 mAl • • 4.5 mV
LOAD REOULATK)N IAIL" 100 mAl • 2 mV
NDt.: R3 - :!+~~Ior I'III..._ .......... drih Not., R3" :~+:! lor minimUfll ......N .. drift NDt.:For ........ ionI~theTO·55tvt-PKII...
_wt..
dio*VZit; ..... _ _.n
bei ...... _ItmIII&.2·woIr
_.. [Link]. wilh
Fig. 23 - Low-voltags regulator circuit fV0 =2 R3....., [Link] for minimum componenl count. 92CS-24119
_ 5houId
to 7 volts). Fig. 24 - High-voltJIge regulator circuit fV0 = 7
VolT_inIIIISI.
to 37 volts)• Fig. 25 - NegstillB-VOltage reguliltor circuit..
•+ 0---<>------, .+
r'-_....L..l-_~~--;;;~:"!'~R£~GULATEO
~ Vo OUTPUT
2.r "ftn
CA7U
CA723C
CUftR[NT
LIM. Rscp
CA723
CA723C
CURRENT
LIM. ..
5-6kn
I--o--~r R~~ED
CIRCUIT NfiFORMANCE DATA: C1RCUIT I"[Link] DATA:
REOULATEDOU11'UTVOLTAGE . . . . 16 V REOULATEDOUTI'UTVOLTAGE • •• IS V
LlNERI!GULATIONCAV',-3YI • • • • 1.6 ,.y
CIRCUIT PERFORMANCE DATA: UNEREGULATION ItoVI-3VI • • • • 0.6 ..v
LOAD REGULATION ([Link]. t AJ. • • . 16 MY [Link] • LOADREOULATlONltolL - '0 ......1. . . 1 MY
LINE REGULATION 16VI" 3 VI . SHORT.(:IRCUITCURREfifT • • • • • • 20 IlIA
LOAD REGULATION ItoIL· 1 AI.
Fig. 26 - Positive-voltago-regulator circuit (with
external n-p-n pillS transistor}. Fig. 27 - Positive voltage-regulator circuit (with Fig. 28 - Fofdback currtlnt-limiting circuit.
external p-n-p pass transistor).
..0'..
oz •
"II
CIRCUIT I"ERFORIIIANCE DATA:
REGULATEOOUTf'UTVOLTAGE • • • 50 V
LINE REGULATION 16VI"20YI • • • 15 mY
NoJt:F.. ~....."..._T().6stPt LOADREOULATIONUl1l"60mA} • • • 20 mY
~"''''''VZ'''''''''''.''''·
t1m11118.Z-voIt_diodIlhouldt._
_ _ in __ wllhYOfT."m .... el. Fig. 29 - Positive-floating regulator cirr:uit
------------------------------------------------------------------~
CA741, CA747, CA748, CA1458, CA1558 Types
TOP VIEW
RCA No. of Pha.. Offset Voltage Min. Max. VIO [Link]
Type No. Amp/. Comp. Null AOL (mVI Ranga tCI
CA1458 dual into no 20k 6 o to +70·
CA1558 dual into no 50k 5 -55 to +125
CA741C single into yes 20k 6 o to +70'"
CA741 single into yes 50k 5 -55 to +125
CA747C dual into yes· 20k 6 o to +70'"
SO
CA747 dual into yes· 50k 5 -55 to +125 Id.-CA 14585,CA 1458T,CA 15585,
CA748C single ext. yes 20k 6 010 +70'" and CA 1558T and internal
single phase compensation.
CA748 ext. yes 50k 5 -55 to +125
*In the 14-lead dual-in-line plastic package only.
·AII types in any package style can be operated over the temperature range of -55 to +125 0 C, O'FSET NULL NC
although the published limits for certain electrical specifications apply only over the tempera·
I~~~T - '1+
ture range of 0 to +70o C.
NON -INV + 6 OUTPUT
INPUT
ORDERING INFORMATION '1- 4 !5 °J'~~ET
TOP VIEW
When ordering any of these types, it is important that the appropriate suffix letter for the
package required be affixed to the type number. For example: If a CA1458 in a straight-
le.-CA74ICE,CA74ICG,CA741E,
lead TO·5 style package is desired, order CA1458T.
and CA741G with internal
phase compensation.
PACKAGE TYPE AND SUFFIX LETTER
TOP '11[*
T0-5 Gold-CHIP Gold· BEAM-
Type No. PLASTIC CHIP FIG. No. OFfSET
STYLE PLASTIC CHIP LEAD 14 NUll'''''
8L 10L OIL-CAN 8L 14L 8L 14L :~ 2!}---t---"'V
CAI458 T S E G H GH Id,lh ::~fll 3
CAl 558 T S E G Id,lh
CA741C T S E G H GH la, Ie ~i-:~~;I !5
CA741 T S E G L la, Ie =;II~~ 6}--+---",!,-
OFfS£T
CA747C T E G H GH Ib, If 1~=~Tf81 .,}--+-~~/ NUll IS)
CA747 T E G Ib, If
If.-CA747CE,CA747CG,CA747E,
CA748C T S E G H GH Ie, Ig and CA747G with internal
phase compensation.
CA748 T S E G Ie, 19
. . .ECOM·S. PHASE
:~[SET
I~:~T -
COMP.
'1+
NON -IN\(
INPUT
+ 6 OUTPUT
'1- 4 O:~~ET
TOP VIEW
Ig.-CA748CE,CA748CG,CA748E,
and CA748G with external
phase compensation.
OUTPUT (AI I
7 OUTPUT fBI
INV
6 INPUT IBI
V- ~.i)-+---'
TOPVI[W
1h. -CA 1458E,CA 1458G,CA 1558E,
and CA 1558G with internal
phase compensation.
Fig.2-Schematic diagram of operational amplifier with external phase
compensation for CA748C and CA748. Fig. 1 - Functional Diagrams (Cont'd)
____________________________________________________________________ 51
CA741, CA747, CA748, CA1458, CA1558 Types
ELECTRICAL CHARACTERISTICS
For Equipment Design
LIMITS
TEST CONDITIONS
CA741C
Supply Voltage,
CA747C"
CHARACTERISTIC V+= 15V, UNITS
Ambient CA748C
V-=-15V
Temperature, TA CA1458*
Min. Typ. Max.
Input Offset Voltage,
25°C - 2 6
mV
RS=<;;10kn
VIO Oto 70°C - - 7.5
TIME-II'
Input Offset Current,
25°C - 20 200
nA Fig.8-0utput voltage vs. transient response time for
110 o to 70°C - - 300 CA741Cand CA741.
Input Bias Current, 25 °c - BO 500
nA
liB o to 70°C - - 800
Input Resistance, RI 0.3 2 - Mn INVERTING
INPUT
Open-Loop Differential RL;;' 2 kn 25°C 20,000 200,000 -
OUTPUT
Voltage Gain, AOL Vo = ±10 V Oto 70°C 15,000 - - NON-INVERTING
INPUT
Common-Mode Input
25°C ±12 ±13 - V
Voltage Range, VICR
Common-Mode
RS';;;10kn 25°C 70 90 - dB
Rejection Ratio, CMRR 92CS-19424R2
Supply-Voltage
Rejection Ratio, PSRR
RS';;;10kn 25°C - 30 150 IlV/v Fig.9- Voltage-offset null circuit for CA741C, CA741,
CA747CE, CA747CG, CA747E, andCA747G.
RL;;' 10 kn 25°C ±12 ±14 -
Output Voltage Swing,
VOPP
25°C ±10 ±13 - V
RL;;'2 kn
o to 70°C ±10 ±13 -
INVERTING
Supply Current, I± 25°C - 1.7 2.8 mA INPUT
Device Dissipation, Po 25°C - 50 85 mW OUTPUT
NON-INVERTING
* Values apply for each section of the dual amplifiers. INPUT
ELECTRICAL CHARACTERISTICS
Typical Values Intended Only for Design Guidance 92CS-19425A2
TEST TYP. Fig.10-Voltage-offset nu/J circuit for CA748C and
CHARACTERISTIC CONDITIONS VALUES UNITS CA748.
V± = ±15 V ALL TYPES
Input Capacitance, CI 1.4 pF
Offset Voltage )
Adjustment Range ±15 mV
Output Resistance, RO 75 n
>-@_~r---,VOUT
Output Short-Circuit Current 25 mA
Transient Response: Unity gain
Rise Time, tr VI = 20 mV 0.3 IlS
Overshoot RL = 2 kn 5 %
CL';;;100pF 92CS-15746
Slew Rate, SR:
Fig. 11- Transient response test circuit for all types.
Closed-loop 0.5
RL;;' 2 kn V/lls
Open-Ioo~ 40
... Open-loop slew rate applies only for types CA748C and CA748.
___________________________________________________________________ 53
CA1541D
ELECTRICAL CHARACTERISTICS y+·sy
TEST CONDITIONS
SIOA
V·" SV. V-· -5V
CHARACTERISTICS SYMBOLS VTH A~J.' ' ITA' 25°C LIMITS UNITS
-5\1 '!:. ,"'. lun'a"
(Term. 131 indicated
CEXT " 0.01 ",F otherwise) MIN. I TVP. MAX.
Static IDCI Ch.8Cterittia
Power Dinipetion Po l~O 180 mW
Input Offset Current ',0 "A
[Link] Bi8sCurrent:
25
TA=25o C liB "A
V5 • v ••
TA' 55°C 50
V3'" V4 ~
Output Voltage:
High VOH 10M = 200 '-'A
Low
V'4" 5 V, 350
TA'"2SC'C mV
VOL '9= lOrnA 400 Fig. 5 - Tnt circuit for measurementoflow (VOL) and
TA = 12SOC
high (VOH) output voltage le.,l£
StrObe Load Current IS V'2 = 0 1.5 mA
Strobe Reverse Current:
TA=25o C 'SR V'2 '" 5V "A
25
TA=l25 C
Input ~le Load Current 'G VlO '" V,1 0 2.5 mA
Input Gate Reverse Current
THRESHOLD
TA=250 C 'GR VIO '" Vll ~ 5V "A WAYEFDRMS
25
TA = 125°C
OUTPUT '.v~
Switchint CharKterilticl [Link]
AT TERM 9 035y _ _-
Input Threshold Vollage: 20
14 17
TA=250 C VTH mV
2"V~":~'
TA= 5510 125°C 12 17 22
Input Offset Voltage V ,O mV 'IN
Input Gate Voltage: IIA PROPAGATION
VGH I .• [Link] DELAY
V3 ~ V5 = 25 mY. OUTPUT - 50% WAYEFORMS
High
Low VGL V4'" V6 '" 0 0.7 AT TERM. I ~r-~y
Common·Mode Range:
Input Gate High VCM
:!:l.S
AT TERM. 9 Ov _-U-I~
_ __
Input Gate Low :!:1.5
Differential-Mode Range:
Input Gate High
VOH ,- mV
Input Gate Low .!.1.5
VOL
Propagation Delay:
InpullO Amplifier Output 'IA V3 ~ 25 mV Ipulsedl. 10 15
Input to Output '10 V,2 = 2V 20 30
Strobe to Output V3= V4= V5" V6'"O.
'SO 15 20
V 12 = 2V Ipulsed)
Gete Input to Amplifier Output 'GA V,I = 2V (pulsed) 10 15
Gate Input to Amplifier Input 'GI V3 = 25 mY 30 35
Common·Mode Recovery Time:
15 30
Input Gate High teMR V3~V5'"'·5V
Inpul Gate Low I. 30
NOTE I :YTH" ',.
iOO
Differentlal·Mode
NOTE 2: 52 IN ~a
ReCO_IY Time: 30 WHEN 51 IN ~a"
Input Gate High 'OR V3" Y5 =400mV S2 IN-b"
WHEN S2 IN -b-
Input Gate Low
Fig. 6 - Throrhold propagation deI.v, ,.",.nd input-of""t
telt circuit with 'lSOciared pul" MeW forms.
f !:IC SUPPLY VOLTAGE tV+,VM'."'5 v
25 AMBIENT TEMPERATURE (TA'-25-C
/
E20"--f---l---+--+/--2o''---+-+----1
~
/
~
i "f--f---t-/-./'--t-/-t-....,--f---t----t---1
"•~ 'Of---t-/-'--t--t--r-i--t--r-~
./
25 50 75
AMBIENT TEMPERATURE ITAJ--C
'00
'"
-3 -3.5 M" -".5 -5 5.5
THRESHOLD ADJUST VOLTAGE [VTH CADJ.J]-;~S_19l91
-6 -6.5 -7 -".5 -.
NEGATIVE DC SUPPU VOLTS \VMI
-5.5
Fig. 7. -Input VTH'" TA- Fig. 7b - Input VTH'" VTH (AOJ.J Fig. 7c - I~put VTH" V-.
__________________________________________________________ ~--------55
CA2111AE, CA2111AQ
Features:
FM IF Amplifieri-Limiter and
• Di......pIocoment for ULN2111A ond MC1357
Quadrature Detector • Good ••[Link]: [Link] Ilmlling "'''''110 Ik...1 1400
pY typo .. 10.7 MHz; Z50 pY typo ot 4.5 MHz
ond 6.5 MHzl
For FM I F and TV Sound I F Applications • Excollont AM ..joctl... 145 dB typo ot 10.7 MHzI
The CA2111A. on a single monolithic chip, provides a multi- • Pro"ilion for output from 3-1t11g1t I F amplifier section
stage wideband amplifler·limlter, a quadrature detector, and an • low hermonic distanion
emitter-follower output stage. This device is designed for use • Quadrature detection permits simplified single-coil tuning .'0.'
in FM receivers and in the sound IF sections of TV receivers.
In addition, an output terminal is provided which allows the
• Extremely low AFC
[Link]. Nnll
.0..... drift ewar full
use of the amplifier-limiter as a straight .60-d8 wideband
• Minimum number of external partJ required
amplifier.
Fig. '-Block diagrlJm of CA21 ',A lind
The amplifi ..·limiter features the excellent limiting character- DSochlte(/ outm,.rd componeh.
istics of 3 cascaded differential amplifiers.
The quadrature detector requires only one coli in the asso-
ciated outboard circuit and therefore, tuning is a simple MAXIMUM RATINGS. Abso/ute·M#Jlfimum V./[Link] TA-2!PC
procedure.
DC Supplv Voltage
(between terminals 13 IV+).nd 7 tV-I] ,. V
A unique feature of the CA2111A is its exceptionally low
AFC voltage drift over the full operating-temperature range. Device Dinipelion:
This devi~ can be supplied in either dual-in-line or quad-in· UptoTA""eooe " ...... " . 600 mW
line 14·lead plastic packages (CA2111AE and CA2111AQ, AboveT A .. we derate linearly 8.7 mwre
respectively).
Ambient T'mpIt'alur. Range:
ELECTRICAL CHARACTERISTICS ot T A • 25"C Operatinll ..... , -55 to +125 ·c
Stor. -66 to +150 ·c
LIMITS lAad Temperature (During Soldering):
CHARACTERISTIC SVMBOL TEST CONDITIONS UNITS At dinanca 1/18 ;t 1/32 in.
MIN. TVP. MAX. 11.59;t O.79nwn)
from case fOflOs max. . .... +265 ·c
v+ ~ 12V - -
DC Yoltage:
At Terminal 1 V, . BY -
5.4
3.7 -
At Terminals 4, 5, 6, 10 Y4.5.6.10 V+- BY - . 1.35 - Y
At Terminals 2,12 V2.12 - 3.5 -
DC Current linto Terminal 13)
-
- SUPPLY VOLTAGE !V"'oI2V
AMBIENT TEMPERATURE ITAI-2S"C
I.
1J .L .
I II _
AtY+' BY - 14 mA 50
IOC)%FM,30'IoAM
- - lo···5MItI ~~~.('l1 ",ofl'
'''E~ SIG"olL ",,\11 ~~
AtY+ '12Y 1,3 16
Amplifier Input Resistance R4 - 7 - kn 40 ~f.-... k'r
Amplifier Input Capacitance 11 pF --.. ~ ........ Y
1"4
Detector Input Resistance 1"12 70 kn .0 ~.; .. -
Detector Input Capacitance 1"12 fa' 10.7 MHz 2.7 pF
n b.:C"~
~.
Amplifier Output Resistance 1"10 60
Detector Output Resistance 1 200 n 20
. , . .. . ..
De-Emphasis Retistance 14 B.B kn -- -'j-
0
" , ,
•• I
INPUT SIGNAL VOLTAGE: (Vjl-IIIV[rlll.] "
DVNAMIC ELECTRICAL CHARACTERISTICS ot TA' 25°C
FM ModuIotion Frequency· 400 Hz, Sou,.. R._ • son
Fig. 2 I-AM Mjft:tion vs Input voIr.,. (4.5 MHz).
TEST CONDITIONS TESTCIR·
CUlT OR
CHARACTERISTIC SVMBOL fa - 10.7 MHz fa =4.5 MHz f o ' 5.5 MHz CHARAC-
UNITS
M' ± 75 KHz ll(:: ± 25 KHz [;f - ± 50 KHz TERISTIC
CURVES
y+. 12Y V'·SY y+ '12Y y+ =12V FIG. NO.
LIMITS
TVP. MAX. TVP. MAX. TVP. MAX. TVP. MAX.
AMPL·LlMITER
Input Limiting VjUim) 400 600 400 600 250 400 250 400 Y 7,6,8,9
Threshold Voltage (4) IRMS)
AM Rejection * * AMRllI 45 - 37 - 36 - 40 - dB 2,7,5,6
Ampl. Voltage Gain. AylIOI 55 - 55 - 60 - 60 - dB 7
DETECTOR
INPUT VOLTAGE IVjl-IIIV[rllllj
Recovered Audio* • YoIAF) 0.48 - 0.3 - 0.72 - 1.2 - Y 6.7,8,9
Output Voltage 111 IRMS) Fig_ 3-AM,.jectlon vsinputvo,.,. ([Link].
Total Harmonic*
Distortion THOll) 1 - 1 - 1.5 - 3 - % 1
4v i .. 10 mV (AMS) -100% FM. 30% AM
__ ~ ________________________________________________________________ 57
CA3000
DC Amplifier HIGHLIGHTS
• Input IlIP8dance • • • • • • • •• 195 10 hI'.
• Volt... Gain. • • • • • • • • •• 30 d8 typo
• Designed for use in Communication, Telemetry, Instrumentation, and • ~ Rejection [Link] • •• 98 dB typo
Oata-Process i ng Equ i pment • Input Off..t Volt.... • • • • •• 1.14- tN typo
• Pu.h-Pull Input and Output
• Balanced differential-alllplifier configuration with controlled • freqvenc,. Capabi lit,.
constant-current source to provide Dutstand ing versat i I ity DC to 30 MHz (with external C and R)
• Bu i It- in temperature stab i I ity for ope rat ion from -55OC to +125OC • Wide AGe Range. • • • • • • • •• 90 dB t,.,.
• Companion Application Note, ICAN 5030 "Applications of RCA CA3000
Integrated C i reu it DC Amp) i fier" covers character ist ies of different
operating lIodes, frequency considerations, 10 MHz narrow band APPLICATIONS
tuned amp1 ifier design, crystal oscillator deSign, and
liaR)' other
.ppl ieat ion aids • [Link] Trl,ger
• RC-ColI,led [Link] '.1'1 ifier
• 10-Lead hermetic TO-5 style package • [Link]
• COMparator
ABSOLUTE·MAXIMUM VOLTAGE LIMITS MAXIMUM POWER SUPPLY VOLTAGE ··160' ±S V • Modulator
at TFA = 2S o C • [Link] Oscillator
-650C to +1250C MAXIMUM SINGLE·ENDED INPUT-SIGNAL VOLTAGE .... V • Sense AIIIPI ifler
OPERATING-TEMPERATURE AANGE
STORAGE·TEMPERATURE RANGE -650C to +150oC MAXIMUM [Link] INPUT-SIGNAL VOLTAGE . ±:IV
LEAD·TEMPERATURE (During Soldering): MAXIMUM DEVICE DISSIPATION:
At distance 1116± t/32 Inch 11.59 ±O.19 mm) From -550C to BSoC. • . • • • • . • . • 460 mW
from case for 10 seconds max. . . . . Above S50C . • . . . . • . . . • Derate 5 mWflC
ELECTRICAL CHARACTERISTICS, at TrA = 25"C, Va:; = +6V, VEE = -6V, unle .. otherwi.e opecilied
V'
·LIMITS TYPICAL
SPECIAL TEST COIIOITliIIIS TEST CIWIAC-
SlMIIOLS Tertlina1, Mo.14- & Mo.5 "ot CIRCUITS TYPE TERISTICS
CHARACTER I ST! CS CA3000
Connected Unless Specified CIIIVES
Fie. [Link], MIx. Units Fig.
STATIC CHARACTERISTICS
Input Offset Volt. VIO - I.' 5 .., 2
Input Offset CUrrent
Input Bias Current
110
lIB
-
-
1.2
23
10
36
,J.
,J.
2
3
TERMINALS
~ 5
Quiescent Operating V8 Me NC -- 2.6 - 4
---
or NC,
Voltage VEE '.2 V 4 2.8K Re
VIO VEE NC - -1.5 V 4
VEE VEE - 0.6 V 4
Device Dissipation
OYIIAMIC CHARACTERISTICS
Po NC. Me - 30 - lflii IIOIIE D,
0,
--
Differential Voltage Gain
Single-Ended Input
AOIFF Single-Ended Output f .. I kHz
Double-Ended Output f = I kHz
6
6
28
-
32
38
-- dB
dB
5
5
R"
Bandwidth at -3 dB Point BW V I -10mV, Rs-1 kG - &SO - kHz 7
MaximUM Output Voltage
Swing
Vour(P-P) f = I kHz 6 - 6.~ - yep-PI NiIIIE
Rliistance values 0'" in ohms
Fie.1 SCHEMATtC DIAGRAM
COIIIJIOn-Mode Rejection
Ratio CMRR f· I kHz 9 70 98 - dB 8
Single-Ended Input
Impedance
liN f· I kHz 11 7011 I95K - n '0
Single-Ended Output
Impedance lOUT f·1 kHz 13 5.5K 8K 10.5K n 12
Total Harmonic Distortion THO AS·lkf! f ' l kHz VO-42Vp- p - 0.2 5 %
"
AGe Range (Max jaum Vol tage
Ga in to Complete Cutoff)
AGe f = 11kHz 15 SO 90 - dB NiIIIE
STATIC CHARACTERISTICS FOR TYPE CA3000
INPUT OFFSET VOLTAGE AND CURRENT V$ TEMPERATURE INPUT BIAS CIIIlRUT VI TEMPERATURE QUIESCEMT OPERATING VOLTAGE VI TEMPERATURE
POSITIVE DC SUPPLY [Link] (\Iccl- +6 POSITIVE DC SUPPLY VOLTS t'tec;' +1 OSI IVE OC SUPPLY VOLTS tVCC)- +6
NEGATIVE DC SUPPl.Y '\IOLTS tVEE). - I NEGATIVE DC SUPPLY '\IOLTS IVEE) - - I EGAT1VE OC SUPPLY VOLTS I" l - -
o.
o ." -,g -25 25 75 100 125
-75 -~ -~ U !50 15 100 12!i -15 -50 -25 15 100 125
" 00
AMBIENT TEMPERATURE tTA l--C AMBIENT TEMPERATURE: tTA J--C AM81~T TE"MPiRATURE ITA I--C
Fig,~
______________________________________________________________________
Fig.2 Flg.S 59
CA3001
Video and Wideband Amplifier HIGHLIGHTS
.P ...... [Link] I.p.' & Output
o4GC Ro.., • . . . . . . . . . 60 .B ..,.
• De,ip_ lor ••• III Vi .... Sr.'''' ••4 CotI",unlcotlon 1 ... I,...ont • ... oIwhltlo •••••••.••• 2'MH•
01.,.. R.,lstanc•...... l50kO ..,.
• [Link] tI'He,.",I.1 ....,Ufl.r cHfI.u,.,l_ [Link] c••,,.II., [Link]-CU'''''' .oure. oOutput [Link],taneo ..•.. 45 0 ..,.
'rOYi .... DU......4,", .,." ..IIIt)'
• Volte,. Goln ....•.•.. 19 dB .., •
•••IIt-in teMperat.,. [Link]" hlr .,.mlo....... ~55OC to +12SOC olnpu' OH.., [Link],•.••. I.S ..V .., •
• [Link], WI"or In,.t & output
oC..,..,... Application Note fCAN5038 -Applicllfi•••f tho RCA·CA3001 In......... APPLICATIONS
Circuit VI'" A""Ufio,·, co.a, ••IHere.' ."""'" _ ••, •• In eM.,.I, .[Link]., -SchMitt Tri"o, oDC, IF. &
Iwl ... c.,.[Link], 3 .toto ••,lIflo, .... lln,." a [Link] ttl ..., • ...,. o Mi ••r Vid..
·12-Lead Hermetic TO-S Style Package aWulotor AMplifi.r
-, -'0
.,..-"
ABSOLUTE-MAXIMUM VOLTAGE AHO CURREHT LIMITS ot TA = 2SoC
[Link]
Indicated voltlll8 or current limit. tor each terminal can be applied under the _pacified conditioD8 for other terminal•. 2.211 ae in ohms.
All Voltqe. are with respect to around (common tannina1 of Positive BDd [Link]'V. DC Supplies).
'"
VOLTAGE OR VOLTAGE OR *lntem.1 CoMlCtion - DO NOT USE
TERMINAL CURRENT ~IMITS CONDITIONS CURRENT ~IMITS CONDITIONS Fi,.r - Sc......flc DIG..,....
TERMINAL
NEGATIVE POSITIVE TERMINAL VO~TAGE NEGATIVE POSITIVE TERMINAL VO~TAGE
2.6 0 [Link] 0
I -2.5 +I!o5 3.10 -6 3
9 '6 8 2S mA 9 <6 "'
1.6 0 200-fl RESISTOR
2 ·8.5 0 3.10 -6.5 CONNECTED BElWEEN
9 <6 TERMINALSNo.S & No.1
1.2.6
• 9 0 '10
1,2,6,10 0
3 ·10 0 9
10
<6 S
"'0
1.2.6
"'0 10 ·10 0
1.2.6
3 -6
4 ·8.5 0 9 '6 9 '6
10 ·6 1,2.6.10 0
1.2.6 0 3
"'
5
"' 0 3.10
1.2
9
-6
'6
0
11 25 mA
9 '6
200-0 RESISTOR
CONNECTED BETWEEN
...,..,
F;,.2 - 'npllt o'''.t voltap ami curren' VS. temperature.
[Link]&No.l1
6 -2.5 ·>2.5 3.10
9 "'
<6
12
INTERNAL CONNECTION
00 NOT USE
INTERNAL CONNECTION
7 00 NOT USE
CASE
INTERNALLY CONNECTEO TO TERMINAL No.3 I
(SUBSTRATE) 00 NOT GROUNO POSITJY£ DC SUPPlY YOLTS 1VCC)-+6
NEGATIVE DC SUPPLY VOLTS {VEEI--&
'"
OPERATING TEMPERATURE RANGE ..... . ·SSoC to t 12SoC
STORAGE TEMPERATURE RANGE ...... . _65°C to tlSOoC
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max. . ............. . t26SoC
~ 10
MAXIMUM SINGLE-ENDED INPUT·SIGNAL VOLTAGE .. ±4V
MAXIMUM COMMON·MODE INPUT·SIGNAL VOLTAGE ±2.S V i
MAXIMUM DEVICE DISSIPATION:
--nl ~ ·215 0 7S
·SS to 8SoC 4S0mW AMBIENT TEMPERATUftf (TAI-·C
Above 8S oe ................................................ . Derate linearly 5 mWJoe Fig.3 a Input 6;0. cu"ent vs. temperature.
POSITIVE oc SUPPLY VOLTS c"tcl'+f!I
NEGATIVE DC SUPPLY VOLTSCV[eI.-6
I
I 110
0 ~
~» 4
MOOED
il
i~= EC
~~ 2 MOOED
i:>-
u- ,
i -,. 0
-50 -25 . 50 ,. 100 '25 -50-250 n 50 1S
MODE •
12.
AMIIENT TEMPERATURE (TA )-'"C AfMIENT TEMPERATURE (TAI--C
Fig. 4 - O.'p.' off 0.' Yo/Ia". YO. ",,.,..,.Iure. Fig. 5 Qu;escent operating voltage
a ¥s. temperoture. Fig. 6 • Dev;ce Jiss;pat;on vs. temperature.
____________________________________________________________________ 61
CA3001
"cc Vee
.6V
Iro' lIt-lei 'BV
Vee
+6v 11,1+1161
"'--z-
92(;S-15581 '" Separate tuned input circuits are used for 1.75 MHz and 11.7 MHz.
I. Ad,.'" VB fOl' VOVT(DC) =0 to.1 v
' ..... off•• t won ... (VIO) III mV ••
2..........
VB
V. and ...c=ard
Fig. 13 .. Input oR.. , cutrent and input "ias current
Source-resistance matching taps adjusled wilt! clte:"I! tuned to
resonance .,d with 5O-ohm reSistor connected to simulate
noise diode.
vw-iOOO tes' circuit.
Fig. 14 .. Hoise li9ur. fest circuit.
Fig. 12 .. Input oHs.f vo/to,. f.s' circuit.
37-250
"
[Link]
WITH HIGH- GAIN
DIFFERENTIAL.
INPUT
ITEKTRONIX TYPE
510. 5"0. OR 580
____- " " " - - , WITH TYPED "[Link]-IN
TEKTRONIX TYPE 502,
OR
EQUIVALENTI
CONMC)t.I-MODE REJECTION RATIO
CMR-ZO LOG'OI"i~~:~:,31
- .. -SINGLE-ENDED VOLTAGE
GAIN AGe RANGE: 20 [Link] A WITH S IN POSITION X
10 A "fIIITH S IN POSITION Y
Fig. 15 .. Common-moJe rejedion ratio 1851 c/rcuil.
Fig. 16 .. AGe range test circuit.
._ _ _ _ 63
CA3002
ELECTRICAL CHARACTERISTICS, at T A. = 25·C VCC = i6 V. VEE =·6 V POSITIVE OC SUPPLY VOLTS (Vce'· +S
NEGATIVE DC SUPPLY VOLTS tvEE"-6
.,.IENT TEMPERATUR£ ITA,-25·C
TYPICAL LIMITS FREQUENCY If I • [Link] MHr
SPECIAL TEST CONDITIONS TEST
CHARACTERISTICS SYMBOLS TERMINALS No.3 & No.4
NOT CONNECTED
CIRCUITS CA3002
CHARAC·
TERISTICS
CURVES
,
UNLESS OTHERWISE NOTED ! 10
Fig. Min. I Typ. Max. I Units Fig. !
STATIC CHARACTERISTICS:
'"put Offset Voltage
Input Unbalance Current
VIO
lru
• 2.2
2.2 10
mV
p.A
2
2
Input Bias Current I) 2Q 36 p.A 3
MODE TERMINAL
'00 1000 1000 2000
t).Iiescent Opecatina
2~ • SOURCE RESISTANCE (R,I- A
Voltap
A VEEJ HC 2.8 V
• Fig. 7 -- Hoise figur. vs source resistance.
Device DiSSipation
B VEEJ VEE 3.9
SS
V
mW
•
N....
PT
Vee
.6v
DYNAMIC CHARACTER~TICS:
Differential Volta.. Gain VIN= 10mV
(Single-Ended Input ADIFF f .. 1.75 MHz 19 2. da 5 &.5
and Output) As-son
Bandwidth at ·3 dB Point BW As" son. VIN" 10mV 11 MHz 6
Maximum Output Voltaae SWine VouT(p·PI 5.5 Vp.p None
Noise FIII...e NF f = 1.75 MHz RS = 1 k.O. B • 8 d8 1
Input Impedance Compol18flts:
n
=:-:.
Parallel Input Resistance RIN f" 1.15 MHz Non. lOOk Noo. VEE
[Link] Input Capacitate.
Output Resistance
• CIN f = 1.75 MHz
f = 1.75 MHz
Non•
Ie
•
70
OF
n
No..
9a& 9b .!:s
-6V
~e::=: =dl~M=:'V=~ ~'re~s~
ROUT
connected to slmulat. the noise diode.
AGe Ran .. (Maximum Voltage
AGC t .. 1.75 MHz 13 60 60 dB 12 Fig. 8 - Hoise figure.
Gain to Complete Cutoff
POSITIVE DC SUPPLY [Link] IVccl' +6 POSITIVE DC SUPPLY VOLTS lVee)- +S POSITIVE DC SUPPLY VOLTS tyee'- .1
NEGATIVE DC SUPPL'Y \lO\..T$ (VEE} a -6 NE6ATIVE DC SUPPLY VOLTS 1Vn" -I NEGATIVE DC SUPPLY VOLTSIVEE)--.
FRECUENC'Y If) • 1.75 101HZ AMIIE:NT TEMPERATURE IT" ,-n"c FREQUENCY' It) • 1.75 MHr
INPUT AOolUSTED FOrt,I'd
~o dB B£LOW FUNDAMENTAL.
[Link] 1
-75 -~ -25 2!1 50 ." 100
'" 10 15 20 2' 100 12.
FR£OlJ(NCY IfI-Wiz
Fig. 9B • Output ru; stance vs [Link]•. Fig. 9b. Output reaisfanc. vs frequency. Fig_ 10-lnput/weI for - 30 dB intsrmodulBtion
w. temptHatunl
II IVE C SUP LY VOLTS lVee'. +S
MUATIVE DC SUPPLY VOt..TS tVEElo - .
[Link] TlMf'UAT\IRE ITA' -,15-c
1) Increase both input......... toMS until tha 2fJ-n and 211-12 output-
lignal voltegn an 30 dB below tha '1 and '2 outpUt..ign81 vol~_
2) M......n rms v"u. of tha Input and output Ii..,
"01.....
3) The m....nd input Ii...' volt... is that ,,"ua wilen .... 3nI-har-
1015202S50
I'1t£QU1"NCY CfI- .....
1) Set Ittenuator at 80 dB attenuation.
2) Sel [Link] de supply '101_ at 0 V.
3) Inctl.... lanll Inpulvolta.. untll RF V.T.V.M. indicates SIIIV
... ""......
monic intermodulatia" products an 30 dB below the fundamen- output.
Fig. 12· AGe range vs frequency. 4) Set _iable de supply volta.. .t -6 V•
5) Adjust attenu.r until RF V.T.V.M. qaln indicates 5 mV output.
Fig. 17 • Intermodulation Test Circuit.
6) Ch ..p in attenuator seninl in dB Is tot.,
AGe Ran...
FIg. 13· AGe ""'ge.
-------------------------------------------------------------~
CA3004
INPUT OFFSET VOLTAGE TEST CIRCUIT
ELECTRICAL CHARACTERISTICS, at TFA = 25° e, Vee = i6V, VEE = -6 V unless otherwise specified
LIMITS TYPICAL
TEST CHARA(}
SPECIAL TEST CONDITIONS TYPE TERISTICS
CHARACTERISTICS SYMBOLS CIRCUIT
Terminals No.4 and NO.5 Open CA1I04 CURVES
Unless Otherwise Specified Fig. Min. I Typ. Max. I Units Fig.
STATIC CHARACTERISTICS
Input Offset Voltage VIO Fig.4 - 1.7 5 mV FII.2
Input Offset CUrrent - FII.2
""""
110 FI&-5 0.125 5
Input Bias Current II Fig.5 - 21 40 FI&.3 I. ADJUST RI FOR VO UT-O:6:[Link]
2. RECORO VIO
TERMINALS
4 5 -6V
VEE
Quiescent
Operating
19
or
NC NC Flg.8 - I - mA Fia.6
Fig."
Current
III VEE NC fig.8 - 2.7 - mA Fil.6
NC VEE Fla.8 - 0.145 - mA Fig.6
VEE VEE Fig.8 - 1..25 - mA Fia.6 INPUT OFFSET CURRENT AND BIAS CURRENT
TEST CIRCUIT
Quiescent Operating
Current RatiO "/lll Fi a.8 - 1.1 - - FIg.7
Vee
+IV
Device Di ssipatlon PT Flg.S - 26 - mW NONE
DYNAMIC CHARACTERISTICS
-
Power Gain
Noise Figure
Gp
NF
f = 100 Me/s
f = 100 Me/s
Fil.11
FI&.11
10
- ..,
12
9
d8
d8
Fi e.9
Fig..)O
WPUT OFfSET
CURR£NT 1Xxo)oolX12 - :r,,1
COmmOfl Mode
Rejection Ratio
(lIIR f '" 1 Kc/s Fig. 13 - 98 - d8 FI&.12 ~::E:~~IIJ·~
AGe Ranee (Max. Voltage
Gain to COmplete Cutoff) AGe f = 1.75 Mc/s FIg.14 -60 - - d8 NONE
DEFINITIONS OF TERMS
Input Offset Voltag. Powe,.Gain
The difference In the lie voltaps which must be applied 10 the input The ratio of the signal power developed at the output of the device Fig.5
terminals to obtain equal quiescent ope,atinl voltages (zero output to the signal power applied to the input, expressed in dB.
offset voltale) at the output terminals.
Noise Figur.
The ratio of the total noise power of the device and a ,esistive QUIESCENT OPERATING CURRENT VS TEMPERATURE
Input Offset Current
signal source to the noise power of. the sienal !IIoUlce alone, the
The difference in the currents at the two input terminals when the signal source representinl a generator of zero Impedance in series
quiescent operatinl voltqes at the two output terminals are equal. with the source resistance.
Common-Mode Rejection Rafio
Input BiGS Cu,rent The ratio of the full differential voltage lain to the common-mode
The average value (one4talf the sum) of the cunents at the two vcltaae gain.
input terminals when the quiescent operatina voltaps at the two
output terminals are equal. Common·Mode Voltage Gain
The ratio of the signal voltaps <levelOpe<l between the two output
Quiescenf Operating Current terminals to the slanal voltage applied to the two input terminals
connected In parallel for ac.
The average (de) value of t~e cunent in either output terminal.
Differential Volta,e Gain
Qui . .cent Operating Current Ratio The ratio of the chalge in output voltaae at either output terminal
with lespect to around, to a chanae .in inpul voltaae at either input
The ratio of the Quiescent operatin, cUllents in the lWO output terminal with respect to ground, With the other input terminal at
terminalS. ac gt'ound.
Device Dissipation AGe Range
The total change In voltap aaln (tram maximum gain to complete
The total power drain of the device with no sianal appl led and no ex- cutoff) which may be achieved by application of the specified ranee
ternal load current. of dc voltage to the AGe input terminal of the device FI,.6
TEST CIRCUIT FOR TYPE CA3004
QUIISCINT OPIRATING CURRINT, QUIISCINT
OPIRATJr:I~~~:::':~IW~Y'~I~ DIVICI
QUIESCENT OPERATING CURRENT RATIO
VS TEMPERATURE
.'2=e
POSITIVE DC SUP!tt.Y VOLTS 1VCC)- +&
NEGATIVE DC SUPPLY VOLTS tVEE)' -e
f1lttI.
..ct-lllT"
PT • Vee «9 +)10 +)ul + VEE Is
Flg.7
'11·1
------------------------------------------------------------~
CA3005,CA3006
RF Amplifiers • P••h-Pull Input ... 0..... SCHEMATIC DIAGRAM POR CAJO.5 AND CADI
•
•
•
Designed for UII in Communications Equipment
Balanced Di"'[Link] Amplifier Configuration with Controlled [Link],..Current
Source to Provide [Link] [Link]'7
Buil~in [Link]. Stability lor [Link] , _ -55" C 10 +125" C
.-
•
•
Wid. CIIICI N.,... 8... ,-,lIfle,
AGe
.P, IF, . . VIlli..
'_0, C:-~IIi"
Operation ..... DC to lOG MHz
·.........
• MI • .,
• Companian [Link], ICAN5022 "Applicatlan 01 RCA CAlOO4, CA3005,
.d CA3006 Integrated Circuit RF Amplifiers", co••r. [Link] of • [Link],
diHerent operating mod••, noise performance, cross-modulation, ml ...r, AGe ,
limit.r, detector, and amplifier design considera'ions. • Casc" ...1111.,
• 12-Lead Hermetic TO-5 Stvle Package. .......... ........
IN OIM
".'11_
NOTI. C - . ' ......1 ....' ......
Ie ....., _ ..... . - , . ,
[Link],
,... ,
ABSOLUTE-MAXIMUM VOLTAGE LIMITS, at TFA = 25"c
INPUT OFFSET VOLTAGE AND CURRENT
Voltage limit.a shown tor eacb terminal oan be applied under the indicated voltase ccmditions lor other tenninate.
AU voltage. are with respect to GROUND (common terminal of Positive and Ne,ative DC Suppli•• )
VOLTAGE LIMITS CONDITIONS VOLTAGE LIMITS CONDITIONS
TERMINAL TERMINAL
NEGATIVE POSITIVE TERMINAL VOLTAGE NEGATIVE POSITIVE TERMINAL VOLTAGE
7 0 1 0
8 -6 7 0
1 -3.5 .3.5 9 .6 9 .6
10 .6 8 -12 0 10 .6
11 .6 11 .6
12 0 12 0
2 TEST POINT: DO NOT APPLY VOLTAGE FROM 1 0
EXTERNAL SOURCE 7 0
1 0 8 -6
7 0 9 0 .12 10 .6
3 -9.5 0 •
9
-9.5
'6 11 .6 "g.2
10 '6 12 0
II '6
12 0 1 0
1 0 7 0
7 0 8 -6
4 -6 0 •
9
10
-6
'1;
'6
10 0 .12 9
11
.6
.6
INPUT OFFSET VOL T AGE TEST CIRCUIT
II '6 12 0
12 0
1 0 1 0
7 0 7 0
9 .6 8 -6
5 -12 0 11 0 .12 9 .6
-.10 .6
11 .6 10 .6
12 0 12 0
1 0 8 ·9.5
7 0 9 .6
I. AO~UST RI '011 'lOUT aO*[Link]
12 ·9.5 0 10 .6
9 .6 1."EeofIIO'lso
6 -6 0 10 .6 11 +6
- v
11 .6 CASE Inlernall. comecled 10 Terminal No.8 (substrale) va
12 -6 DO NOT GROUND FII·3
1 0
8 -6
9 .6
7 -3.5 '3.5 10 '6
11 .6 INPUT .,1.5 CURRENT
12 0
OPERATING-TEMPERATURE RANGE _55°(' to +115°('
STORAGE-TEMPERATURE RANGE .OSoC to +150°C
LEAD TEMPERATURE (During Soldering)
AI distance 1/16 ± 1/3:! inch (1.5 1):!: 0.7(111111)
J
from case for 10 seconds max.
MAXIMUM SINGLE·ENDED INPUT·
SIGNAL VOLTAGE ±3.5 V
MAXIMUM COMMON·MODE INPUT·
SIGNAL VOLTAGE -1.5 V. +3.5 V
MAXIMUM DEVICE DISSIPATION . ]00 mW
________ ~ ______________________________________________________ oo
CA3005,CA3006
COIlMOM·MODE·REJECTION RATIO COMMON-MODE-REJECTION RATIO
TEST CIRCUIT
OSCILLOSCOPt:
.ITH MIIH-IUIN
OIFFER£NTIAL
INPUT
tTEKTItOMIX T'f1'l
SSO, 540,011: '.0
.ITH TYPE 0 1'[Link]-IN
@-_-'---<[Link] T'I'P£ 502,
EOUIVc:.II!NT)
COMMC* IIOD[ R£,II!CTIQIf lIaTIO
.ZOLOGIO~
VDlF" talllSl
'11. 13
'1,.14
AGe RANGE TEST CIRCUIT
S1~~SO :i~
.1.11
_____________________________________________________________ 71
CA3007
ABSOLUTE·MAXIMUM VOL TAG! LIMITS. at TA • 25° C
TYPICAL DYNAMIC CHARACTERISTIC
Indicated vollqe limit. ror each terminal can be applied under the specified operatinc co~[Link]. ror other terminala.
An voltales are with respect to llOund C-¥CC. +VEE. or common termmal of Positive and NeIBtive DC supplies), AND TEST CIRCUITS FOR CA3OO7
VOLTAGE LIMITS CONDITIONS VOLTAGE LIMITS CONDITIONS
TERMINAL TERMINAL POWER GAIN AND TOTAL HARMONIC DISTORTION
NEGATIVE POSITIVE TERMINAL VOLTAGE NEGATIVE POSITIVE TERMINAL VOLTAGE TEST CIRCUIT
2 0 2 0 Vee
3 ·6 3 ·6 .IV +"0'1
6 0 6 0
I ·2.5 +2.5 7 .0 8 ·2 0 7 0
9 <6 9 <6
II 0 II 0
3 ·3 2 0
6 0 3 ·6
2 ·8 0 7 0 9 0 .10 6 0
9 <6 7 0
II 0 II 0
6 0 2 0
7 0 3 ·6
3 ·10 0 9 <6 6 0
II 0 10 -2 0 7 0
6 0 9 <6
7 0 II 0
4 ·8.5 0 9 <6 1 0
II O· 2 0
2 0 3 ·6 T (Output TriWIsformer):
II ·2.5 .2.5 6 0 Primary Impedance "'20000 C.T.
3 ·6
6 0 7 0 Secondary Impedance'" 16 n
5 ·2.5 .2.5 7 0 9 <6 Efficiency =4sr. approx.
9 <6 2 0 (STANCOR TYPE TA-1O OR EQUIVALENT!
i1 0 3 -6 Fi'll"
2 0 6 0
12 ·2 0 7 0
3 ·6 INPUT IMPEDANCE TEST CIRCUIT
6 ·3 0 7 0 9 <6
9 <6 II 0
II 0 CASE INTERNALLY CONNECTED TO TERMINAL
1 0 No.3 (SUBSTRATE) DO NOT GROUND
2 0
3 ·6
7 ·2.5 <2.5 5 0
6 0
9 <6
- V
VEE
FI,.7
COMMON·[Link] REJECTION-RATIO TEST CIRCUITS
[Link] REJECTION RATIO vs TEMPERATURE Vee "ce
.1 V .IV
POSIT IV! DC SUflP....,. [Link]) 0 ....
NEGATIVE DC SUPPLY VOLTS 'VEI)·-.
COMMON-MODE REJECTION RATIO
CMIt.2O LOGIO A:!~!~~~ v~
+ .( *A-SINGLE-£NDED VOLTAGf: GAIN
-2$ 0 H ~." 100125
(A) Sin,I.-End" Din.,.ntlol Volt.g. Goin (8) Common_Mod. Voltag. Gain
fAn-AIR TIEMPlJtATURE IT,AI-ec
Fig•• Fig.'
______________________________________________________________________ 73
CA3008, CA3010, CA3015, CA3016, CA3029,CA3030, CA3037, CA3038
ELECTRICAL CHARACTERISTICS a' TA • 2Sa C • TYPICAL STATIC CHARACTERISTICS AND
TEST CIRCUITS
Special Test CondiliOlls
INPUT OFFSET VOLTAGE AND CURRENT
Terminal No.8 (CAJOIll, Test CA30111 CA3016 Typical
CAJ0I6, CAJ029, CAJ030, Cir· CAJOIO CA3015 Charac·
Characteristics Symbols CAJ037, CAJ038) cuit CA3029 CA30l0 Units teristic
Terminal No.5 (CAJOIO, CAJ037 CA30l8 Curves
CAJ0I5) Not COIlnected r--
Unless Otherwise Specilied Fie. Min. Typ.] Max. Min. Typ. IMa•. Fie.
STATIC CHARACTERISTICS:
Input Offset Vottaee VtO VCC' ",V, VEE' ·6V 4 1.08 5 mV 2
• +12V • -12V 1.37 5
Input Offset Current 110 • +6V • -6V 5 0.54 5 2
[Link]
• +12V • -12V 1.07 5
Input Bias CUllent - +6V • ·fN 5.3 12
liB 5 [Link] 3
• +12V • -12V 9.6 24
tnput Offset Voltaee 0.10 I AMBIENT TEMPERATURf {TAI-·C
LlVtO/LlVCC • +6V • -6V
Sensitivity: Positive • +12V • -12V 0.096 0.5
4 mV/V none
• +6V '-6V 0.26 I Flg.2
Negative LlVIO/LlVEE
• +12V • -12V 0.156 0.5
• +6 V • -6 V :ro
• +12V • -12V 175
Device Dissipation Po [[ishorted to [ID VCC • +6V 4 102 mW nOlle
VEE' ·6V
8 shorted to 12 VCC' +12V, 500
V"F • -12V INPUT BIAS CURRENT
DYNAMIC CHARACTERISTICS: All tests at f • t kHz except BWOl
[Link]\/E DC SuPPLY VOLTS tVeel
NEGATI\If. DC SUf't"LY VOLTS IVa}
Open-loop Oillerenlia' VCC • +6V, VEE' -6V 8 57 60 dB 6&7
AOl
Vollaee Gain • +12V • -12V 66 70
Open-loop Bandwidth BWOl • +6V • -6V 8 200 300 kHz 6&7
al -3 dB Point • +12V • -12V 200 320
70 94
·
Common-Mode Rejection CMRR VCC' +6V, VEE' -6V 11 dB 12
80 103
•:: I'
Ralio • +12V • ·12V
Mallmum Output-Vollaee • +6V • ·6V 4 6.75 Vp_p 9 & 10
• ,.
VOIP-P) 8 ~
Swing • +12V • -12V 12 t4
C-+'2\f Vi r--'2V
Input Impedance ZIN • +6V
• +12V
• ·6V
• -12V
14 10 14
5 7.8
kll 13 C··.v ·-6V
Output Impedance ZOUT • +6V • -6V 15 200 n 15 25 50 75 100 125
• +12V • -12V 92
AMlENT TEMP£RATUAE fJA)-·C
0.5
-
Common-Mode
tnput·VoUaee Ranee
VICR
• +6V
• +12V
• ·6V
• ·12V
11 -.
to
- 0.65
to,
-8 '
V none Flg.3
LEAD TEMPERATURE lOuring Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± O.79mm)
from case for 10 seconds max.
'l'C'rminal Numbers in Circles are for CA3008, CA3016, CA3029, CA3030, CA3037, CA3038;
Italic Numbers in Square Boxes are for CA30lO, CA3015
INPUT OFFSET CURRENT AND INPUT 81A5 CURRENT
TEST CIRCUIT
Procedu,.:
s~=rl~Tv?::.S!~Dvg~~tCGEEb:~:'~IT~~:S:ls;~1~~8~T Input Offset Voltage
vee 1. Adjust VE for a DC Output Volta.. (VOUT) of 0 f 0.1 volts.
2. MeasLl'e VE and record Input Offset Voltage In millivolts as
VE/lOOO.
Input Offset Voltoge Sensitivity
I. Adjust VE; for a DC OutPUt Voltage (VOUT) at 0 ± 0.1 volts.
2. Increase IVee I by 1 volt and record output voltaee (VOUT).
I I
3. Decrease VCC by 1 volt and record output voltage (VOUT)'
4. Divide the diference betwMtn VOUT measlA'ed in steps 2 and 3bythe
change In VCC In steps 2 and 3.
~ VOUT (Step 2) • VOUT (SteP 3)
VCC 2 volts
5. Refer the reading to the input by dividing by Open Loop Voltage
Gain (AOL). Fig.S
Procedure:
VOUTIVcc
F19·4 VIC/Vce '" - - - Input Blo. Currenl ond Input [Link] Current
AOL I I
1. Adjust VE for VOUT < 0.1 V DC.
6. Repeat procedures 1 through 5 for the Negative Supply (VEE). 2. Measure and record VE and VIN4.
7. Device Dissipation 3. Calculate the Input Bias CUffent using the follOWing equation:
PT ::: VCCIC + VEEIE . V1N4
IC = Direct Current into Terminal@orl@
114 = 100 kO
I[Link] Direct Cunent out of Termina~ I!J 4. Calculate the Input Offset Current USing the follawing equation:
110 = VE/lOO kO
________________~--------------------------------------------------75
CA3008, CA3010, CA3015, CA3016, CA3029, CA3030, CA3037, CA3038
TYPICAL DYNAMIC CHARACTERISTICS AND TEST CIRCUITS
Terminal Numbers in Circles are for CA3008, CA3016, CA3029, CA3030, CA3037, CA3038;
Italic Numbers in SqUOTe Boxes are far CA3010, CA3015
[Link] INPUT IMPEDANCE .s. TEMPERATURE SINGLE·ENDED INPUT IMPEDANCE TEST CIRCUIT JTPUT IMPEDANCE .so TEMPERATURE
vee
Flg.1 ..
AMBIENT TEW'ERATtR (TA)--C .-NT T£MP£RA1l.M IT",--C
FI,.13 Flg.)5
OUTPUT IMPEDANCE TEST CIRCUIT
vee
~~~~________________~-oS2
1. With ~ In position (e) I adjust VE for VOUT(DC) '" 0 t 0.1 volt.
2. With 51 in position (a), and $2 in position Cd) I record VOUrl (rms).
3. With Switch $1 in position (b),and 52 in position (d), adjust RL until
Flg.16 VOUT2(rmsl '" ~ Record value of RL as ZoUT'
2
____________________________________________________________________ 77
CA3008A, CA3010A, CA3015A, CA3016A, CA3029A,
CA3030A, CA3037A, CA3038A
ABSOLUTE·MAXIMUM VOLTAGE AHD CURRENT LIMITS, TA o 250C TYPICAL STATIC CHARACTERISTICS AND TEST CIRCUITS
Vollfl~(' or currN,r ll1mts shown for each t('rminal cun hE' I'pplied under theo IndICated
v()ltn~e or otht'T circuit conditions for other It'rminnls
Terminal Numbers in Circles are for CA3008A, CA3016A,
All voltllKl'S ar{' with rp"'rwcl to ground (common (('rminal of Positive und N{'[Link]' DC Suppli('s) CA3029A, CA3000A, CA3037A, CA300BA;
Italic Numbers in ~qume Boxes aTe far CA301OA, CA3015A
Termll1al Vo!tageor Current Terminal Voltage or Current
CA3C08A limits Cirelli! ConditIOns CA3016A limits CirCUit Conditions
INPUT OFFSET VOL TAGE AND CURRENT
CA301GA CA3029A Nega POSt CA3015A CA3030A Nega· Posi·
CA3037A live live Terminal Voltage CA3038A live live Terminal IVoltage POSITIVE DC SUPPLY VOLTS (Ved
NfGATlVE OC SuPPLY VOLTS (YEE)
11 DO NOT APPLY VOLTAGE FROM AN EX· DO NOT APPLY VOLTAGE fROM AN EX·
TERNAL SOURCE TO THIS TERMINAL 12 TERNAL SOURCE TO THIS TERMINAL
>.
CA3008A
CA3029A
CA3016A
CA3030A "! 11.25
~II
CA3010A CA3037A CA3015A CA3038A INPlJT OffSET [Link]
4 5 OV 4 5
8V OV 10 13
10 13
I 2 o 1 2 o
4V dV 3 4 o dV 3 4 o
4 6 6 4 5 12
10 13 ,5 10 13 ·12
0.25
I 1 I 2
1 3 dV 2 3
dV
4 6 4 5 25 7S 100 125
10 13 10 13 AMBIENT TEtoFERATUFIE (TA1-"C
NO CONNECTION NO CONNECTION Flg.2
oV I 2 OV 1 2 o INPUT BIAS CURRENT
10 13 10 13 ·12
NO CONNECTION POSITIVE DC SUPPLY VOLTS Ned
NO CONNECTION
NEGATIVE DC SuPf>lY VOI...TS (VEE'
DO NOT APPLY VOLTAGE FROM AN EX-
TERNAL 50URCE TO THIS TERMINAL
DO NOT APPLY VOL TAGE FROM AN EX-
TERNAL SOURCE TO THIS TERMINAL
DO NOT APPLY VOLTAGE FROM AN EX·
TERNAL SOURCE TO THIS TERMINAL
DO NOT APPLY VOLTAGE fROM AN EX·
TERNAL SOURCE TO THIS TERMINAL
.
I 1 I 2
10 oV +7 V 4 6 10 oV +14 V 4 5
10 13 10 13
DO NOT APPLY VOLTAGE FROM AN EX·
11 DO NOT APPLY VOLTAGE FROM AN EX- II TERNAL SOURCE TO THIS TERMINAL
J 5.1.
TERNAL SOURCE TO THIS TERMINAL
I: ll; J ,: 4
40~~' Betwe~~ Termin+a\!
12
12 30 mA 200 " Between Termlilais
5 & 12 (CA3008A,
CA3029A, CA3037A)
4 & 9 (CA3010A)
12 30 mA
6 & 12 !CA3016A.
CA3030A, CA3038A)
4 & 9 (CA3015A)
.,. .
AMBIENT TEMP£RATURE (1AI-'C
000 ,,.
10 13 oV +10 V 10 13 oV +20 V Fig.3
I 2 1 1 INPUT OFFSET VOL TAGE, INPUT OFFSET VOLTAGE
11 14 oV +7 V 4 5 11 14 oV .14 V 4 5 SENSITIVITY, AND DEVICE DISSIPATION TEST CIRCUIT
10 13 10 13
Int~rnally connected to Terminal NO.4, Ifltemally connected to Terminal No.4,
CASE CA3010A (Substrate) DO NOT GROUND CASE CA301SA (Substrate) DO NOT GROUND
CAJOO8A CAJ01OJ.
CAJ016A CAJ015A CA3029A CA3016A CAJOl5A CA3OO8A CA3010A
CA3037A CAJOleA CAJOJOJ. CAJOOOA CA3038A CA3029A CA3037A
OPERATING TEMPERATURE RANGE e
. '55 0 C to +125 0 40°C 10 -IBOoe ·8Vlo+l V ·4Vlo +1 V
MAXIMUM SIGNAL VOLTAGE
STORAGE TEMPERATURE RANGE, , , , ,55°C 10 .2000C ·55 0C to '150 0 C MAXIMUM DEVICE DISSIPATION, 600 mW 300 mW
Flg.4
Proc:edure:
Input Offlet Voltage
1. Adjust Ve for a DC Output Voltage (VOUT) of 0 ± 0.1 volts.
2. Measure VE and record Input Offset VOltaie in millivolts as
VE/lOOO.
INPUT OFFSET CURRENT AND INPUT BIAS CURRENT Input Offs.t Voltage Sensitivity
TEST CIRCUIT
1. Adjust Vi for a DC Output Voltage (VOUT ) of 0 ± 0.1 volts.
I
2. Increase Vce by 1 volt and record output volta,e (VOUT).
I !
3. Decrease Vce by 1 volt and record output \loltall8 (VOUT).
4. Divide the diference between VOUT measured in steps 2 and3bythe
change In Vce in steps 2 and 3,
Proc:edl,lre: VOUT " VOUT (Step 2) • VOUT (Step 3)
Input Bios Current and Input Offset Current Vcc 2 volts
I I
1. Adjust VE for VOUT < 0.1 V DC. 5. Refer the reading to the input by divldin, by Open Loop Voltap
2. Measure and record VE and VIN4 Gain (AOU.
3. Calculate the Input Bias Cuuent usin, the followin, equation: VOUT/VCC
VloNcc 0 - - -
114=~ ADL
6. Repeat procedures 1 throu,h 5 for the Negative Supply (VEE).
100 kil
4, Calculate the Input Offset Current using the followin, equation: 7. Device Dissipation
110 "VE/lOO kO PT '" VCCIC + VEEIE
Fig.S
IC '" Direct Current into Terminal 13 or !ill
IE '" Direct Current out of Terminal 6 or 0
___________________________________________________________________ 79
CA3008A, CA3010A, CA3015A, CA3016A, CA3029A,
CA3030A, CA3037A,CA3038A
COMMON·MODE REJECTION RATIO vs. FREQUENCY
"" FREQUENCY tfl-MHI:
10
Flg.12
[Link] INPUT IMPEDANCE "s. TEMPERATURE SINGLE·ENDED INPUT IMPEDANCE TEST CIRCUIT
POSITIVE DC SLPPU' VOLTS tVeC! vee
N(GATIVE DC SUPf'LY VOLTS tval
-15 -50
Flg.13
.. Flg.U
OUTPUT IMPEDANCE TEST CIRCUIT
vee
1. With 52 in position (e). adjust VE fOl VounDC) "" 0 ± 0.1 volt.
2. With 51 In position (aI, and 52 in position (d). record VOUTt(,ms).
3. With Switch 51 in position (b) and 52 in posltiQn (d) adjust RL II1tll
Flg.15
VOUT2(rms) = ~ Record value of RL as ZOUT.
2
POSITIVE DC SUPf"LY VOLTS Ned
NEGATIVE DC SUPPLY VOLTS tV[El NOISE FIGURE vs. FREQUENCY
POStTf\lf DC SUPPLY VOlTS tVee!
NEGATIVE DC SUPPLY VOlTS IVEE)
SOURCE RESISTANCE" I I( OtiM
20
i~
•
I" -7\1 -25 25 50 ." 100 125
AMBIENT TEl,lP£RA~ tTAJ-·C
6 8 1000
OUTPUT IMPEDANCE va. TEMPERATURE FREQUENCY !fI-Hz
Fig.16 FIII.17
___________________________________________________________________ 81
CA3011, CA3012
ELECTRICAL CHARACTERISTICS DISSIPATIDH TEST SETUP
+~c
TEST CONDITIONS LIMITS
TYPICAL
CHARACTERISTICS DC AMBIENT CHARAC-
SETUP FREQUENCY SUPPLY TEMPERA· RCA RCA
SYMBOL & TERISTICS 50
VOLTAGE TURE CA301I CA3012 UNITS CURVES A
PROCEDURE f VCC TA
Fig. Mel. Volts °c Min. Typ. Max Min. Typ. Max. ~
·55 80 - 66 80 135 - mW
- 6 <25 60 90 133 66 90 121 mW
+125 70 - 65 70 121 - mW
Tot,l ·55 130 - 97 130 190 '- mW TOT&I... DEVfCE DISSIPATION IPTI-VccJ:
Device
Dissipation·
PT 6 - 7.5 +25 95 120 187 97 120 167 mW ncs-IS112
+125 \00 - 95 100 167 - mW Fig. 6
·55 - - -
150 210 275 mW
- 10 +25 - - -
150 190 255 mW
+125 - - -
150 160 255 mW
·55 55 - -
50 55 - dB INPUT-IMPEDANCE COMPONENTS
TEST SETUP
9 1 6 +25 60 66 - 60 66 - dB
+125 61 - -
50 61 - dB
·55 -
59 - 55 59 - dB
9 1 7.5 <25 65 70 -
65 70 - dB
Volt..! Gain·· A +125 - 65 -
55 65 - dB
·55 - - -
55 61 - dB
9 1 10 +25 - - -
65 71 - dB
+125 - - -
55 66 - dB
9
4.5 7.5 +25 60 67 - 60 67 - dB
5
10.7 7.5 +25 55 61 55 61 - - dB
Input·lmpedance
Co_nts:
Parallel Input
Resistance R'N 7 4.5 7.5 +25 - 3 - - 3 - kO 2 Fig. 7
Parallel Input
Capaci tance CIN '1 4.5 7.5 +25 - 7 - - 7 - pF 2
Output Impedance
Com_ts: OUTPUT-IMPEDANCE COMPONENTS
Parallel Output TEST SETUP
Resistance ROUT 8 4.5 7.5 +25 - 31.5 - - 31.5 - kO 3
Parallel Output
Capacitll'lce COUT 8 4.5 7.5 +25 - 4.2 - - 4.2 - pF 3
Noise Filllre NF 10 4.5 7.5 +25 - 8.7 - - 8.7 - dB
Input Limiting
Voltage (Knee) Vi(lim) 9 4.5 7.5 <25 - 300 45 - 300 4IJ( JJ.V
Fig. 8
MOISE FIGURE TEST SETUP
+Vcc
VOL T AGE·GAIN TEST SETUP
PROCEOURES
A - Volt. Gain:
1) Set Input "equency at desired value,
VI =100 iN rml.
2) ReCOI'd vo-
3) Calculate Voltap Gain A "om
A = 20 10110 Yo/v I
4) Repeat Steps 1. 2. and 3 far each
ftequency and/or fo. [Link]. desired.
B - Input Limltln. Voltqe (Knee):
I} Repeat Steps At and A2. uslna
v,=l00mV
2} Decrease Y I to the level at which Yo
..
Is 3 dB below its value for vi:: 100 mY. Ll '" 82 ~, center-tapped
3) Recard VI as Input Llmitln. Volta.. L2 '" 2.36~
("" ). Cl,C2 = Alco TYPe 423 padder, 01 e~ivalent
Fig. 9 Fig. 70
_____________________________________________________________ 83
CA3013, CA3014
VOL TAGE·GAIN TEST SETUP
TEST CONDITIONS LIMITS +Vee
ELECTRICAL TYPICAL
DC AMBIENT CHARAC·
CHARACTERISTICS SETUP FREQUENCY SUPPLY TEMPERA· RCA RCA TERISTICS
(See Page 8 for
Definitions 01 Terms)
SYMBOLS &
PROCEDURE ,
VOLTAGE TURE
VCC TA
CA3013 CA3014 UNITS CURVES
Fig. Mel. volls . °c Min. Typ. Max. Min. Typ. Max. ~
3 6-
·55
+25
80
60 90 133
- - 7373 9080 12t1
llO
mW
mW
Total
+125
·55
70
130
-- -- 10660 13070 llO
170
mW
mW
Device PT 3 -
7.5 +25 87 110 187 106 120 150 mW
--- -
Dissipation • +115 100 90 100 150 mW
--- --
·55 165 110 250 oW
3 10- +15
+125·
~
-
165 190 230
150 160 130
mW
mW
PROCEDURE:
1) Set input frequency at desired value, Vi = 100 JJ.V rml.
4 1 6
·55
+25
55
60 66
- ---
50 55
60 66 ---
dB
dB
2) Record '10'
3) calculate Voltll' Gain A from A ::: 20 10110 vo/vi'
--
+115 61 50 61 dB 4) Repeat steps I, 2, and 3 for each frequency
--- ---
and/or temperllure desired.
·55 59 55 59 dB
4 1 7.5 +15 65 70 65 70 dB Fig. 4
Voltage Gain ** A +125
·55
65 -- - -
55 65
55 61 --
dB
dB
- --
4 1 10 .z5 - - 65 71 dB
VOLTAGE GAIN v •• FREQUENCY
+115 - 55 66 -- dB
~:~
--
4.5 7.5 +25 60 67 60 67 dB
4 10.7 7.5 +15 55 60 55 60 - dB 5
Input·lmpedance 70
Components:
•
Parallel Input
Resistance
Parallel Input
Capacitance
Output·lmpedance
RIN
CIN
6
6
4.5 7.5
4.5
+15
7.5
3
+15
-
- 7
--
--
3
7
-
-
kn
pF
7
7
I ..
~
i ..
~
e
.. '" r\
Components:
••
Parallel Output
Resistance
Parallel Output
ROUT 8
8
4.5
4.5
7.5
7.5
+15
+15
- 31.5 - - 31.5 -
- 4.1 - - 4.1 -
kn
pF
9
9
QI . . .. . . .. . .
I
FREQUENCY CU- Mch
10
Capacitance COUT . Fig. 5
Noise Figure NF 10 4.5 7.5 .z5 - 8.7 - - 8.7 - dB 11
[Link] COMPONENTS TEST SETUP
Input Limiting
Voltage (Knee) vi (lim) 14 4.5 7.5 +15 - 300 450 - 300 400 ~V 13
+ Vee
Recovered AF Vollage vo(a') 14 4.5
6
7.5
+15
.z5
- 155
128 188
-
-
- 155
135 188
-
-
mV
mV 13
10 .z5 - - - - 12t1 - mV
Amplitu.e-Modulation
Rejection AMR 15 4.5 7.5 +15 - 50 - - 50 - dB -
Discriminator
Output Resistance
RO(disc) - 4.5 7.5 +25 - 60 - - 60 - n -
Total Harmonic
Distortion THO 14 4.5 7.5 +15 - 1.8 - - 1.8 - % 12
• Total CUlrent dram may be determined by dlV'ldlnl [Link] Vee. •• Recommended minimum de supply volt... (Vee) IS S.5 V•
[Link] cullent tI~nl into terminal 5.s 1.S rnA at 1.5 V.
Fig. 6
INPUT·IMPeDANCE COMPONENTS n. FREQUENCY OUTPUT-IMPEDANCE COMPONENTS ¥s. FREQUENCY
OUTPUT·IMPEDANCE COMPONENTS TEST SETUP
+Vee RIEQlENCY It) _ Mcll
Fig. 7 Fig. 8 Fig. 9
85
CA3018, CA3018A
General-Purpose FEATURES
~ L
Transistor Arrays • Match.d monolithic ljIeneral purpou kansl_tors
• HFE match.d ~ 10%
TWO ISOLATED TRANSISTORS • YBE matched ~ 2 mY CA3018A (t smY CA3018)
AND A DARLINGTON·CONNECTED • Operation from DC to 120 MH.
TRANSISTOR PAIR • Wiel. operating current range
• CA3018A. [Link]. characteristics controlle4
from 10~ A fa 10mA
For Low·Power ApplicatiDRS
1 Fo'
• Law noi .. flgur. - . 3.2 elB typical at I KH.
at Frequencies from DC • Full military [Link]. ran,. capollility
(-55 to "" 125°C)
Through lbe VHF Rallle • The CA3018 is available in a sealed·junction
°' 7'=
Beam Lead version (CA3018L). For further SUBSTRATE
The CA30lS and CA3018A consist of four general pur- information see File No. 515, "Beam·Lead 00
pose silicon n-~n transistors on a common monolithic Devices for Hvbrid Circuit Applications".
substrate.
Two of the four transistors are connected in the • Supplied in the hermetic 12-lead TO-5 Fif. ,. Sclte... "'ic Di09"'''' fa, CAJOl8 and CAJOl8A
Darlington~configuration. The substrate is connected stvle package.
to a separate terminal fot maximum flexibility.
Maximum Ratings, Absolute-Maximum Val u.s, at TA-2SO'C
The transistors of the CA3018 and the CA3018A are CA3018 CA3011A
well suited to a wide variety of applications in low-
Power Dissipation. P: STATIC CHARACTERISTICS
power systems in the DC through VHF range. They Any ooe transistor . • • . . • • . • 300 300 mW
may be used as discrete transistors in conventional Total package. . . • . . . • • • . • 450 450 mW IO"'! [MITTER CURMNT a J-O
circuits but in addition they provide the advantages Derate at 5 mW;oC {or T A> 85°C
of close electrical and thermal matching inherent in Temperature Range:
integrated circuit construction. Operating. • • • . • • • • • • . . •. -55 to + 125 e55 to + 12SoC
The CA3018A is similar to the CA30IS but features Storage •.•.•••.•••..•••• e65 to + 150 e65 to + ISo-°C
tighter control of current gain, leakage, and offset
parameters making it suitable for more critical appli- LEAD TEMPERATURE (During Soldering)
cations requiring premium performance. At distance 1/16 t Ill:! inch (1.59 ± O.79mm)
from case for 10 seconds max. . .. +265 0 r
APPLICATIONS
The followina: raUngs apply for each transistor in the device:
• General use in signal proceninljl sYltems in DC CA3018 CA301U
thrauljlh VH F range . Col1ector-t..Emitter [Link]' 15 15 V
Collector-ta-ease Voltap. VCDO •• 20 30 V
• CUltam designed differential amplifiers
Collector-la-Substrate Voltage, VCIO. 20 40 V
• Temperature campensated amplifiers Emitter-ta-Base Voltaa;e, VESO ••. 5 5 V
• See RCA Application Nate, ICAN-s296 "Application Collector CUrreot, IC •••••• . • •• 50 50 mA
of the RCA CA3018 Integrat.d·Circuit [Link] "'The collector of each transIstor of the CA3018 and CA3018A
Arroy" for Iuggested Applications. is laolated from the substrate by .n integral diode. The
substrate (terminal 10' must be connected to the most ne,-
ative point in the external circuit to maintain isolation be-
tween tmnsistors and to provide (01" nonna.l transistor action.
'" ~'E~CT~;;R:~~:I.":;~AOE (YCEr SV "
~
V r-- AMBIENT TEMPERATIAtE ITA J--C
U=
Fig.2 - Typical [Link]- To-80S. Cutoff Current vs
i ,: y
II~
VI
,
~f
.~ 5000
V
V Amb/e"t Temperature lor Eoch Trans;stor.
Ilia V I"" I I"E'
iiFiII
IIFEZ OR
..
I: 4000
V
V
la~e ./
15: 3000
V 1/
\,!g
:;!C
t;C
ZO
COLLECTOR-TO-EMITTER VOLTAGE (VCE)-!V
AMBIENT TEMPERATURE (TAI-ZS·C
'0
. BASE CURR£NT (IB).
,.
. ..Ii,
60
....,
'00
..
50
, , 468,
EMITTER CURRENT (I£I- mA
Fig. 3 _ Typical Static Forward Current- Trans'"
, o
92CS-25777
, ,
EMITTER CURRENT IIEI-I'/IA
Fig. 4 _ Typical Static Forwan/ Cur,.em - Trans'er Ratio
, I
•• 0
,
I
9
,0'
10 :
I
'
fIi
~i;
:.o:l
,...u
t
~ti ~~-
Ratio and Beta Ratio 'or Transistors Q,
and Q2 v.
Em/Her Current.
'01" Darlington.r;[Link] Trans/ste"
anJ 04 vs Emitter Current.
03
; ,, ,./'~'/
~ ,
, .f
:i:~T~:~~:U~~!~:~TAG~
, a t'
.
DB VCEI·SV COLLECTOR-TO-EMITTER VOLTAIE (VCE)-5V
I
>
I' I ~ '6' ~~~
II 1)-,/ , ~ ,
~ ~ ,
~
g
0.7
-.6-J
.. J,J~~~
~
"o ..to:
""GE-
,
tI
j 10": LL
L.
.
c
I
,;
,.-' 0
t:::L
. ,
~~ " '00
~
:
"" INPUT OFFSET IIOLTAGE_\"eE.I
,.~ ,
~
~
Fig. 7 - Typical Collector-To-Emmiter CuloHCurrentvs
0
, IIII ,I
4680:1
I
461 1
I , 4 6 8 10
i Z5 50 75 100 IZ5
Ambient [Link] lor Ead Transistor.
EMITTER CURRENT (IEI-mA AMBIENT TEMf"ERATUR[ (TAJ--c
Fig. 5 - Typical Static Base-to--Emitter Vo/toge Fig. 6- Typieal Base. To-Ern;t,., Voltage Clt",."ete,istir::
Characteristic ana Input Off~et Voltage 'or for Each Transistor vs [Link] Temperature
Q, and 02 vs Em;tter Current.
______________________----------------------------------------------87
/
CA3018, CA3018A
ELECTRICAL CHARACTERISTICS, (CONT'D) 100 COLLECTOR-TO-EMlTn" VOLTAGE (VCEl-5V
FREQUENCY {f)-IIIHa
4 AMBIENT TEMPERATUR£!TA,02!1-t
CA30,. CA30'IA
~
DY1WIIC CHARACTERISTICS
Laof, _ _ filon Hf 1·1 KHz,VCE,IV,IC.lll11<A
[Link] 1.15 d8 lllb) ·-:--..... R ci-
I
',,-100
III
"1I·2TU~
....,0 •.18_10-4
}
t ··
atIlIlA._
SllrctresistillCl=lKCl 10
, tto."".e,.MIto
low-Fr....II:',[Link]-5i. .1
t-..... 17
·
Eqrri.....,..circull
!· ,
CMrlCteriltics:
llO 12
/ 're
I
FGIWIId CIlflIll·T'..... Rltio lite llO I
Sbcrt-Cirtuit [Link] h~ 15 1.5 KO 12 , ",
. " . . ..-- . . .. . . ,I .
l-lkHz,[Link],IC·111A 15.6 15.6 12 N
Opet-Cifcuit Ouljllt I~ h..
""'"
OpenoCircuit Reverse
VoU...•y,...f. Ratio
Adllittanct Clllrac:teristics:
're I 1.811&4 - l.1IIl1fl'4
12
..
COLLECTOf' CURRENT (Iel- ......
I
FI,.12. FGrwarJ Current·Tran,fer RGf/o (II,.), SItar'.
I
FarwlldTransfer AdtIitlla V~ lI·jl.5 IHl.5 mh' 13
klputAdtiittllCe Vie - D.3+jO.1M O.3+jO.04 ...., 14
Cireu;' Inpu, Impedance (",.), Open-Circuit
Output Impedance (lloe), find Open-Circuit
DotpulAdllittJllce v,. MIIHI,VCE-rIC.10A - [Link]]tjO.03 - [Link]+jO.03 ..... 15 Rever•• Volt", •. Tron,/e, Ra,;o (liN)
vs Collec'or Cunent
Reverse T'lnsfer [Link]
Gain·Bandwidth Prlliucl
V,.
YCE-3V,![Link]
!HCom
3GfI 500 100
See Clive
500
."""
MHz
16
17
IT
Ellitier-to-Base Call1titince CE8 YE8-3V,IE-D 0.6 0.6 of
Collectar-Io-Bne [Link] CC. VC8-3V,IC-O 0.51 ~51 OF
CoUectCl-to-SUbslflte CaPICitance eCI YCI-3V •IC.() 2.1 2.1 of
1::t~~~:A~fA=ec:1NPUT ~-WJ~A~~NPUT
~ICTOfl-TO-IEMlTTI!" YOLTAIE ",")-n ,~LIECTOR-TO-EIIITTt:1t YOLTME I'tf:).' v
UC1aR CUR"'NT IIe'-'IIIA
Ii LLIECTOR CurtltlENT IIe)-'."
.
~,U
~I i "I-+-++++--+~I+-+-I-I-+-J..o--.+~
f",;
;3 ... ~~
114*-+-+~~~-H+-+-~~~~
;i 4
~}
i~ >
~
"
i]ii;
0 i1~ 2 iW 2r-+-~HH--+-+4H4--r-+444~~
I:" .~ I / §: I~~-H+-+-~H-+-~~~~~
QI I
. 10
FREQUENCY Ul-MHl
, ..
r-...
100
QI
, . " I
,
FRE:Ql£NCY (n-MHz
... 10
:....-
, ... 100
, 0.1
Z 468
I
2 46
10
FREQUENCY(fl-MHz
2' 6
100
'2(:8-2:57.
Fig. J3 . ForWfltJ Tra,..", AJmitfonce (Y f.) F/,.14 - Input AJml1tance (V;.J F;9·15 - Output Admittance (V 08)
COLLECTOR-TO-[MITTER VOLTAGE (YcEI·'V
AMIfIENT TtMPERATURE 1'W-25·C
4 6810 Z 4 6 8 00 2
FREQUENCv(f)-MHz
COLLECTOR CURRENT (leI-iliA HCS-Df9Z
Fig. 16 • R• .,.r.e Trans'., AJmlttance (Y re) FI,.17 - Typlca' Gal.-[Link]' [Link] (fT ) ••
Collec'or CU,,."t
__________________________________________________ ~ _____________ 89
CA3019
DC FORWARO CURRENT IlflolmA OC REVERSE VOLTS (1Ifl1 ACROSS DIODE· " AMSIENT TEMPERATURE TAI-25"C
FREQUENCY IF) • IMHOf
§
I
~O.9
~
~ 0.8
~
g 2
c
-50 -~
AMBIENT TEhl'ERATUM (TAl-*<:
100 . o
-", I 2 ,
DC REVERSE VOLTS (VRJ ACROSS DIODE
Fig_ 2 - DC forward voltage drop (anv diode) as Fig. 3 - Reverse (leakage) current (anv diode) Fig. 4 - Diode capacitance (an V diode) as a function
a function of temperature. as a function of temperature. of reverse voltage.
AMBIENT TEMPERATURE nAI • 25·C AMBIENT TEMPERATURE (TAl· 2$'"(:
FREQUENCY Ifl • I MHI FMOUENCY If) • I MHI
I 2 3 .. I 2 3 ..
DC "£VERSE VOLTS (VftIIiETWEEN TERMINAL 2 OR \0 DC REVERSE VOLTS (VRI BETWEEN TERMINALS !I OR e
AND SUBSTRATE (T£RIllINAL rJ AND SUSS"tRATE (T£RMIHAL TI
Fig. 5 - Diode quad-ta-substrate capacitance as a
Fig. 6 - Diode quad-to-substrate capacitance as a Fig. 7 - Series gate switching test setup.
function of reverse voltage. function of reverse voltage.
___________________________________________________________________ 91
CA3020,CA3020A
[Link] AT TA = 250(:
TEST CONDIT! OIlS
CHARACTERI STI CS SYMBOLS CIRCUIT DC LIMITS LIMITS
UNITS
AND SUPPLY CAJOlO CAJ_
PROCEDURE VOLTAGE
FIG. VCCI VCC2 MIN. TVP. MAX. MIN. TYP. MAX.
CollettOl'-to-Ellilter 18 V
2, 25
Breakdown [Link], Q6 & Q) V(BR)CER
.t lOrnA
Colleclor-to-Emitter
Breakdown Voltap, Ql V(BR)CEO 10 10 V
.10.1 rnA
Idle C..renls, Q6&Q) 14 IDLE 4
I)IOLE 9.0 2.0 5.5 5.5 rIA
L [Link] bnHdawn vol.,. COs • 0,1 circuit
Peak Output Currents, 14PK 4 9.0 2.0 110 180 mA
!ls& Q) I)PK
Cutoff Currents, II CUTOFF 4 9.0 2.0 1.0 1.0 .A
Q6 & Q) I) CUTOFF , - M - r - - - - - VCCI
Differetial Amplifier VeC2
ICCI 4 9.0 9.0 6.3 9.4 12.5 6.3 9.1 12.5 rIA
Current Drain
Tolal Current Dram leCI +
ICC2
4 9.0 9.0 8.0 21.5 35.0 14.0 21.5 30.0 mA
Differential Amplifief V2 4 9.0 2.0 1.11 1.11 V
InputTerminalVollqes V3
Re,ulator Terminal VOltal' VII 4 9.0 2.0 2.35 2.35 V
Q, Culoff (Leak"e) Currents:
CollectQf-to-Emitter ICED 10.0 - 100 100
Emitter·to-Base lEBO 3.0 - 0.1 - 0.1 "A
Collector-Io-Base ICBO 3.0 - 0.1 - - 0.1
Forward CurrentT,.ns'er [Link] 0.01
hFEI 6.0 30 )5 30 )5
.'
..
Ratio. 01 atJrnA
Bandwidth at ·3 dB Point 8W 6.0 6.0 8 8 MHz ,.F
6.0 6.0 200 300' 200 3110'
Maximum Power [Link] PO(MAX) 6 9.0 9.0 400 550· - 400 5541' mW b. Typicll audio ......ifW ctrouit u""unl IN I.OA3020 or
9.0 12.0 800 1000" CA3020A _ ......dio p ....... [Link] ct_ B pow.- •
.mplifi.,
Sensitivity for POUT -400 mW 6 9.0 9.0 35' 55 .V
'IN
Sensitivity for POUT =800 mW 6 9.0 12.0 50b 100 mV Flg.2
'IN
Inpul Resistance·---
Termin.13 to Ground RIN3 9 6.0 6.0 1000 1000 n
Junctioo-to-Case
TIlelrnal ReSistance 8J.C - - - 60 60 'CIW
TYPICAL TRANSFER CHARACTERISTICS
a Rec'" 13011
b Rcc = 2000
rt--_···
'2'
TYPICAL PERFORMANCE DATA
An [Link] RMlafw is Recommend'.d' lw Hlp A. ...W.,., [Link] Opwatlon
CHARACTERISTICS SYMBOLS CA3020 CA3020A UNITS
VCc:.t 9.0 9.0
Power Supply Vollage V
VCC2 9.0 12.0
a. T••t [Link]
Oifl. Ampl. ·ICc:.t 15 15
Zero Signal Currenl Output Ampl. rnA
ICC2 24 24
Dill. Amp!. IC~ 16 16.6
mA
Maximum Signal Currenl Output Ampl. u. 140
ICC2
Maximum Power Oulpul at THO: 10'1> Po 550 1000 mW
Sensitivity elN 35 45 mY
Power Gain Gp 75 75 dB +t ·c
Input Resistance RIN 55 55 kn
Efficiency Tj 45 55 'I>
Signal·to-Noise Ratio SIN 70 66 dB
-25 0 25 50 15
THO at 150 mW level 3.1 3.3 'I> 15 50 H 0 -25
Z40N"-+-Z,"oN-
Test Signal Frequency Irom 600n Generator 1000 1000 Hz DlFf"EI'EN1lAL AMPLIFIER INPUTMILUVOI.:rstVZl) S2CS-t5221S
b. [Link] with R 10 .horted out
Equivalent Colleclor·to-Collector Load ReSistance RCC 130 200 n
F".3
____________________________________________________________________ 93
CA3020,CA3020A
MEASUREMENT OF INPUT RESISTANCE
+VCCI +YCC2 PROCEDURES,
Input [Link]. [Link] 10 t. [Link] (RIM )
1. ~::~rio~eilred value of Vee 1 aad Vee2 and .selDs in
2. AdJu.t 1 ~ kHz input for desired slenal level of mea•
• uremeat
!: ::~~':!t ~::~I~i; :l{:e of Ra. RIN
'0
Input R•• [Link]. Tarmlnal 3 to Ground (RIM)
1. :~:1~0:[Link] value of Vec I and V ec2 .e\ S in
2. Adjuat t· kHz input for desired ailnal level of mea ..
aurement
3. AdJuat R for 2 = 111/2 °
4. Record reaulUne value of R aa RIN 3
Fig.9
MEASUREMENT OF SIGNAL-TQ-NOISE RATIO
AND TOTAL HARMONIC DISTORTION
a. Teat [Link]
+VCCI
DISTORTION
ANALYZER
[Link]-
[Link]
TYPE 302A
"".n OR
EOUIVALENT
BALLANT1N[
'.F MODEL 320
OR
EOUIVALENT
PROCEDURES,
[Link]-Nol •• Rotlo
t. Cloae 8 1 and S3i opea S2 POWER AMPLIFIER COLLECTOR VOLTS (V4, v71
2. Applll deaired valuea of Vec and Vce b. Characteristic
3. Adjust e lN for an amplifierl output o~ 150mW and
record reaultlrll value of ROUT in dB .a e OUT
(reference value) 1 Fig.11
4. Open 9. aDd record [Link] value of eOUT ia dB .a
e OUT2
e OUT
5. Siloal-to-Noise Ratio (S/N) = 2010110 _ _,_
e OUT2
Total HOlmonlc [Link]
I. Close 8, and 8 2 i open S3
2. Apply deaired valuea of VCC and VCC
3. AdJuat e lN for [Link] level JmpUtier oltput power
4. Record Total Harmonic Diatortion (THD) in "!o
Fig.1Q
ZERO SIGNAL AMPLIFIER CURRENT
V8 AMBIENT TEMPERATURE
." I ••
S CLOSED
S eLO ED
.0 N
S CLOSED
-50 -25 . K>O
AMBIENT TEMPERATURE ITAI-OC
,,.
o
-50 o 50 100
AMBIENT TEMPERATURE ITA J _·C
,50
b. [Link] Amplifier Characteristics c. Output Amplifier Characteristic.
o. Test Setup
Fig. 12
____________________________________________________________________ 95
CA3021,CA3022, CA3023
ELECTRICAL CHARACTERISTICS, at T A = 25° e, Vee" +6V. unless otherwise specified
TEST SETUP fOR MEASUREMENT OF AGe
TEST CONDITIONS SOURCE CURRENT
LIMITS
FEEDBACK TYPICAL Vee
TEST SETUP RESISTANCE CA3021 CHARAC' "V
CA3022 CA3023
CHARACTERISTIC SYMBO' AND (R~) BETWEEN FRE· (TA5219) (TA\236) (TA5218) UNITS TERISTIC
_. PROCEDURE TERMINALS QUENCY CURVE vMC· ... ·v
3ANO 7 f'
Fig. il MHz Min. Typ. Max. Mm. Typ. Max. Min. Typ. Max. Units FJL
Device 8 mW 3ad
Dissipation PT 12.5 24 mW lb,d
24 35 48 mW 3c,d
Quiescent 39k 2.2 - V
IAGe IS THE CURRENT fLOWING INTO TERMINAL 2.
Output Vo 10k 1.9 - V
Voltage 4.7k 1.3 Fig ...
~GC Source 0.8 0.8 0.8 - mA
Qmenl IAGC
560k 0.\ 50 56 dB 6a TEST SETUP FOR MEASUREMENTSOF VOLTAGE-GAIN, _3dB
39k 0.8 40 46 dB 6a,d BANDWIDTH, AND MAXIMUM OUTPUT VOLTAGE
Vee
39k 2.5 - 50 57 - dB 6b +6V
Voltage Gain
10k 3 - 40 44 dB 6b,d
18k \ 50 53 dB 6c
4.7k 10 40 44 dB 6c,d
39k 0.8 2.4 - MHz 6a
Bandwidth at
·3 dB Point BW 10k 7.5 - MHz 6b
4.7k 10 16 MHz 6c
39k 4000 - il
Input
tnput· Resistance RIN 10k 5. 1300 - il PROCEDURES
Voltage Gain:
Impedance 4.7k 10 - 300 - il
(a) Set ein = O.S mVat frequency specified, read eout Voltage Gain
Compo- 39k '11 pF 'out
nents Input (AI = 20 LOBlO-
Capaci- CtN 10k 18 - pF Bandwidth: ein
tance 4.7k 10 13 pF (a) Set eout to a ccnvenient reference voltage at f '" 100 kHz and
record corresponding value of ein.
39k 300 - il
~~~~cr~:~r:~~~i~~~' keeping ein constant until eout drops
Output il
ROUT 10k 120 Fig.S
Resistance
4.7k 10 - 100 il
4.2 8.5 - dB
39k VOL TAGE GA,N VS FREQUENCY FOR CA302'
Noise Figure NF 10k 4.4 8.5 - dB
4.7k - 6.5 8.5 dB :~~~yT~~~~~~r:;~AJ'25-C ~~~T~~::=~:~R~RM_
TERMINALS [Link],II,ANO 12 CONNEC- INALS No.3 AND 7
TEO TO GROUNO
33 dB 70
AGC Range AGC 10 33 - dB 60 F ED I TAN R
'!lb
10 33 dB
7 !O .""',
Maximum 39k 0.6 ~m'
OUtput Voltage Vout 10k 0.7 - - V(rm,
(AMS [Link]) Ok 10 - 0.5 - V(rm,)
0.1 , "
FREQUENCY (f J - MHz
6 a 10
Fig.6(a)
VOL TAGE GAIN VS [Link] FOR CA3021,
CA3022, AND CA3023
VOLTAGE GAIN VS FREQUENCY POR CA3022 VOL TAGE GAIN VS FREQUENCY FOR CA3023
AMBIENT TEMPfRATURE !TAl· 2!"C FEEDBACK RESISTANCE (RIJI DC SUPPLY VOLTS !VCCl-+ 6
~~
~~~::i~sVZ~~~:'e~~~~: CONNEC-
CONNECTED BETWEEN TERM- TERMINALS [Link],1 L, AND 12 CONNECTED TYPE
INALS No 3 ANO 7
TED TO GROUNO TO GROUNO CA30el 39 I
10 FEEDBACK RESISTANCE (R.81 CONNECTED CA3022 10 5
.
i
60 FEE
.0
>.CO S NCE
4 K
.'" BETWEEN TERMINALS No.3 AND No.7 CUD23 4.7
! •0 2•
'0
~
g 20
~ 40
~ 3!
4 6 8 I 2 4 6 S 10 4 6 8 100
,
4681 2 46810 -76 -50 -25 25 50 75 12!) IS)
FREOlJENCY(ll-MHz [Link]-MHl AMBIENT TEMPERATURE (TA l-"C
FI •. 6(b) Fig.6(c) Fig.6(d)
__________________________________________________________------____ 97
CA3026,CA3054
Dual Independent For Low·Power a"licllills
FEATURES
• Two cliff..antiolomplifi.,s on a ComMon lu~.trote
Differential Amplifiers II Freqlencies hi DC
.[Link] [Link]. inputs and outputl
• Maximum input aH••• volta, ••• t 5 mV
• Full military tempera'u,. ran,. capa"ility -550(: ta
TheCA3026 and CA3Q>4 each consista 01 two independent
differential amplifiers with associated coostant-current
to 120 MHz +125°e
80
transistors on a common monolithic substrate. The six • Limited ..... ,.'[Link]. ,an,... ooe to 8SOC for CA305.c
APPLICATIONS
n~p-n transistors which comprise the amplifiers are
general purpose devices which exhibit low 1 If noise and • Dual I~n,e amplifiers • The CA3064 is available in a sealed·junction
a yalue or fr in excess or 300 MHz. These features • Dual Schmitt tlillen Beam·Lead version ICA3064L). For further
make the CA.1026 and CA:J05,4 useful from de to 120 MHz. • Multifunction combination.·· RF 'Mix., Osdlllltor; information see File No. 515, "Beam-Lead
Bias and load resistors have been, omitted to provide Con..,.rt.r,IF
maximum application nexibilily. Devices for Hybrid Circuit Applications".
• IF IImplifien ([Link] atu' a' cucade)
The monolithic construction of the cA3m6 and CA:lOO4 • Prod"ct deteclars • CA3026-Hermetic 12·lead TO·5 package
provides close electrical and thermal matching of the • [Link] "lanced mad"latars one! clemachllotors
amplifiers. This feature makes these devices particularly • CA3054-14-lead dual·in·line plastic package
useful in dual channel applications where matched per- • 8010ncad CII"ad,at",. d.'act.,s
formance of the two ehaMets is required. • Cncode [Link]
• [Link] [Link]
a Pairs of Itolanced .. hlers
• $ynthesi •• , mi ••,s
• Balanud ([Link]) cu;ad. ampliti."
MAXIMUM RATINGS. ABSOLUTE·MAXIMUM VALUES. AT TA =25·C Fi,.Ja. Sdemaf/c Diagram'ot CA3026.
L o~ ~~"
power m.. ipatlon, P: CA3026 CA30~ The foUowin, ratiDp appl,. for each trensistor in the devJee:
Afy one [Link] .•..• 300 . , . . 300 mW CoUector-to·Emltter Voltap. V CRO ' • , .••.• IS V
Total packqe • . . . . . •• 600
ForTA > MOe" •. Derate at5....
.... 750
6.67
mW
mW/OC
Collector·t...Base Volta... Vcao' ••••••••. 20 V y'
CoUector-to-Substl"llte Voltaae. VClO0' ••••.• 20 V
Temperature Ranp: . 0,
Elldtter-to·aa.e Volta •• V EBO ' ..•••••••• 5 V
[Link], . . • . . . . • . •.... -55 to + 125 °c Collector ClllTel\t. Ie' .... '.' ........... SO mA
Storale . . . . . . . . . . ••... ~5 to + 150 °c • rn
SUBS1IU,l[
LHd Temperature (During Solderlngl: Fit.'" - Sdemafic DiagraM lor CA305~.
At distance 1/16 t 1/32 inch (1.59 t 0.79mm)
from case fOf 10 seconds max. . . . . . . . +265 °c CAUTION: Substrate M15T be maintained negative with
o Tha collector of each transistor ot the CAS026 and cA3054 il respect to all collector terminals of this device. See
(ar fIOf'fIGJ [Link] action. The suNtrate Mould be maintained at
Isolated from the lubstr* by an Intlltal diode. The [Link] must s4fnal (A(]I woIIId bJ' meana 0( tJ .uilable ~ cttpQCilar. to ovoid Maximum Voltage Ratings chart. .
be connecled co II uolttJIIII ulaich u IID'II' "_We tIaJ. ~ colleceor .....iTed coupling between buuistors.
uolkIaV in order to mIIintain ilfOlation between w.-uwra and prouide TYPICAL STATIC CHARACTERISTICS
10il! EMITTER CURMNT II '-0
Maximum Volta,. Ratin,.
The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed horizontally. For example, the
voltage range between verticallenninal 1 t and hcrizoolallerminal 3 t i. +15 to -5
volts.
t For CA3026jcorrelpondilll terminale for CA3054 are vertical
terminal 2 aDd horizontal terminal 4.
CA3054
TERMINAL NO. - 13 .. 1
• 7 8
• 11 12
MoximulII
Current Ratin,1
•..
CA302_
TERMINAL 10 11 12 1
.15
• S
• 7
Note 1
• •
Note 1 CA30s.c
[Link]
NO.•
CA3026
TERMINAL
N•.
"N
mA
lOUT
m'
13 10 0
·20 "
·5 ·5 13 10 0.1
.20 '20
I' 11 0 I. 11 SO 0.1
0
'20 '20 .20
12 0 0
'IS
·5
0 12 SO 0.1
0.1
,a<
. 50
AMBIENT TEMP£RATUR£ ITA)--C: -
'00 ..
,
IleS-ItIM
.1
'5 0.1
For CAS054: use data from ric to 'SOc anty
0.1 ·50
FI,.2 • [Link]-to-H•• clltoHcurre"t nam6;e","..,.,•
•
·20
.5
·S
• IS
'S 0.1 • ture lor eaclt tra"sistor•
.20
0 SO 0.'
.20 .20
0 0 SO 0.1
·15
·5 •. 1
..
1,.'1111/'' ' ' 11
11 .1
'S 11 0.1
I' 12 0.1 SO ~
R., :
ii
.
Sob-
~
stlate
:v V
.J
~::~=: =pe~n:~:!!:e:~:: ~eer~::i8 t~?iii t!:r=~:I:r • Tenpinal [Link] ofCA3054 i. not used
~:e:.r:[Link] limits between all ott.r terminals are not
Mot. h In the CA3026 terminal No.9 iac:onnectedto the emitter 0.' • Ii. I 2 • '10
(te'
~~~d ~~ re~re.::,.:~~tra+~::!~aC:la9·~i~.:no:(~~O~~
COllECTOR MILLIAMPERES
~Croribo!~~t-.J::z6a!:l th:aC~'05:."Wh~tre~er·a~O:::i~k FI,.3 • ',.put 6/0. cur,..,.t cltorac,.,;.tic v. collector
i • •bown in one column 9 and a ratin, is shown in the other
column 9, the .steriak .hould be ipored. curre,.t I. each [Link].
____________________________________________________________ 99
CA3026, CA3054
TYPICAL DYNAMIC CHARACTERISTICS
COMMON MODE REJECTION RA TIO
Terminal Numb.r. In Circl•• ar.
for CA3026 POSITIVE DC SUPI'LY VOLTS !Veel .... 2
NfGAT,V£ DC SUl'PLY [Link] {VEEI • -6
:r:-~~~A~05~.r. In Square Box•• CD 110 FREOUENCY If I • I ilHz
i
i•
I
V,N'Q3vlfl'l'Il'
~IOO
j ~
-I -2 ·s -4
DC liAS VOlTS ON TERMiNAl @ []i] (Vxl tICS-IU53I"
(0) Test setup Fig.8
(b) Characteri"stic
SINGLE-STAGE VOLTAGE GAIN
----.,--,----
T:.'C~;~~umber. In Clrcl•• a...
Terminal Numb.,. In Square Box••
ON for CA3054
(a) rest setup Fig.9
TWO-STAGE VOL
Terminal Number. In Clrcl•• are
for CA3026
Terminal Number. In Square Box••
or. for CA30S4 'I'F
'.F
(aJ rest se'up Fig,lO
TYPICAL DYNAMIC CHARACTERISTICS FOR EACH TRANSISTOR
[Link]~·TO-'ASE ~TS IVcel-'
AMBIENT TEMPERATURE ITAl-2S·C
,/
I I
0.01 10.1 2 I 4 8 '10
COLLECTOR MILLIAMPERES IIel nC$-I!I'~AI
Fig." Forward current-transfer ratio
8 (h,."
shOl'f.c;rcuit [Link] MUIAMPER£S lIe)
Input Impedance (h;.), open-circuif output [Link]
(I,oe)' anJ open-circu;I rents. vo/[Link]"., ratio F;g.J2 - G,,;n-banJwiJth proJuct ('r) V.t collector
(II,.) vs collecto, current 'or ."cll trons/stor. current.
____________________________________ ~ __________ ~ _________________ 101
CA3028A, CA3028B, CA3053 Types
APPLICATIONS
DlFFERENTlAL/CASCODE • RF and IF Amplifiers ([Link] or Cascod.)
FEATURES
• Controlled for Input Offset Voltage,
AMPLIFIERS • DC, Audio, and [Link] Amplifiers
• [Link].r in the [Link] FM Band
Input Offset Current, and Input Bias
Cumont' (CA3028B)
• ...nced Differential Amplifier
Far Comllulicatilas and • uscillotor • Mixer • Limite,
Configuration with Controlled
Industrial Eqlipment at • Companion Application Note, ICAN 5337 "Application
Constant-Currant Source to Provide
Unexcelled Versatility
of til. RCA CA3028 Integrated Circuit Amplifier in the
Fre~uencies from DC to 120 MHz HF and VHF Ranges." This note covers characteris- • Single- and Dual-Ended Operation
tics of different operoting modes, noise ,.rformonce,
The CA3028A and CA3028B are differential/cascode ampli· mixer, limiter, and amplifier desi,n considerations. • Operation from DC to 120 MHz
fiers designed for use in communications and industrial equip· • Balanced-AGC Capability
ment operating at frequencies from de to 120 MHz.
• Wide Operating-Current Range
The CAJ028B is like the CA3028A but is capable of premium
performance particularlv in critical de and differential ampli· Th. CA3028A, CA3028B, and CA3053 aro availablo in tho pack_
fier applications requiring tight controls for input offset voltage, shown below. When ordering_ davie.., it i. important to add tho
input offset current, and input bias current. appropriate suffix letter to tho device.
The CA3053 is similar to the CA3028A and CA302eS but is Pocko... Suffix
recommended for I F amplifier applications. B-Laod T()'5 Lottor CA3028A CA3028B CA3053
T()'5 T ..; ..; .j
ABSOLUTE MAXIMUM RATINGS AT TA = 250 C With [Link].
DISSIPATION: Formed Loads S .j ..; .j
At T A up to 55°C (DiL-cANI
(CA3028AF, CA3028BF,
CA3053FI. • . . . . . . • . . . . . . . . . . . . . . . • . . . 750 mW
Beam·L_ L ..;
AtTA> 55°C Chip H .j
(CAJ02BAF, CA302BBF,
C~3053FI ...•........... Derate linearly 6.67mWfOC
At TA up to 85°C
(CA3028A, CAJ0288, CA30531 .•.•.•.....• 450 mW r;MA=XrIM_U_MrV_OL-,-T_A_GrE_R_Arn_"_GS,..-at_Tr.._=--r2_50_C.------:"..,-,-,-,....-,....-_ _.., CURR~"~MR'!'TI"GS
At TA> 850 C ~~ This cbarl gives tile range TER...
liN lOUT
IHAL
(CAJ028A, CA3028B, CA30531 .Derate linearly 5 mW/OC No. of voltages which can be applied No. mA InA
AMBIENT· TEMPERATURE RANGE: 0 0 0 +5 +20 10 the termina-Is listed hOfizootally
to I
Operating. . .. . .. .•... ... .... .. .. -55°C to +1250 C to •
.15 .\~. -\\. -6
to
0
With respect to the terminals
listed vertically. F« example.
0.6 0.1
Storage..... . . .. .. ... .. ....... .. -650C to +15()OC
+5 +5 t~5. +15
LEAD TEMPERATURE CDuring Soldering):
At distance 1116 ± 1/32" 11.59 ± 0.79 mml
to
.Il
to
·1 0
to
0
the voltage range of Ihe horizontal
lerminal4 with ItSll'c! to terminal
2
• 0.1
from case for 10 seconds max. ............... +2650 C +10 +15 +30e +15 +30 21s -I to +5 volts.
to to to to to 3 0.1 23
0 0 0 0 0
+15
t.
0
t Termlnal"3 is connected to the sub-
strate and case.
, 20 0.1
+.<Us
to
* ~~~~':: t:~~~:~"t:I~:~i:: be- 5 0.6 0.1
0 l'
appea, ina between these terminals
will be safe, the specified volt·
age limits between all otter termi-
nals .e not eltceeded. 6 20 .0.1
Limit IS ·12V for CA3653
Limit is +15Y for CA3053
limit is -t12V to, CAJ053
7
• 0.1
• limit is +24V fOf [Link]
+1av tor CA3053 8 20 0.1
ELECTRICAL CHARACTERISTICS at T A = 25"C
CHARACTERISTIC SYMBOL
• ~
curr
SPECIAL TEST
CONDITIONS
LIMITS LIMITS
TYPE CAl028A TYPE CAl028B TYPE CAl053
LIMITS CHARAC·
UNITS TERISTICS
s. .
CURVES
Fla. IMin. Typ. [Link]. Typ. [Link]. Typ. Max. Fi .
FIg.' _ Sehemafic Jiogtom (01 C,430284, CA30288 onJ CA3053. ATIC CHARACTERISTICS
+VCC -VEE
Input Offset Voltap 6V 6V 0.98
Vr. 12V 12V 0.89 mV
6V 6V 0.56
Vee Input Offset Current Iro 3. 12V 12V 1.06 ~A
3a 6V 6V 16.6 70 16.6 '0
12V 12V 36 106 36 80 Sa
Input Bias Current Ir 9V 29 85 ~A I---
3. 12V 36 125 5.
Is 3. 6V
12V
6V
12V
0.8
2
1.25
3.3
I 1.25 1.5
2.5 3.3 , 6a
Quiescent Operatina
Current
or
3. 9V 1.2 2.2 3.5
mA
r---2----
6.
ra 12V 2.0 3.3 5.0
12V VAGC =+9 1.28 1.28
8a 12V 8.
AGC Bias Current V AGC '" +12 1.65 1.65
~to Constant-Current I, mA I---
urceTerminal No.7) 9V 1.15
12V 1.55
InputCurrent{Termlnal I, 6V 6V 0.5 0.85 I 0.5 0.85 I'
No.]) 12V 12V I 1.65 2.1 I 1.65 2.1 InA
3. 6.V 6V 2' 36 54 24 36 42 9
12V 12V 120 175 260 120 175 220
Device Dissipation PT
9V
r,g,
",.
r--
Fig.2 • Input oHse, volfop test circuit 'Ot CA3028B. 3. 12V 11£
103
CA3028A, CA3028B, CA3053 Types
POSITIVE DC SUPPLY VOLTS(VCCI DIFFERENTIAL -AMPLIFIER CONFIGURATION
75
r~: VCC-+12V
·
0375
~
·•
i "
o I.'
-'" e 50 75
AMBIENT TEMPERATURE ITA1--C tUS.I!l141
·50 -25 0
ANlllENT TEMPERATURE ITA1--C
-'" .!IO -25 0 ~ 50
AM8I[NT TEMPERATURE (TA)--C
100 125
Fig.56 - Input bias curtent vs. ambient [Link] for FIg.6a. Quiescent operating current vs. ambienftemper. Fig.6b - Quiescent operating current [Link];ent temper.
CA3053. .tu,.I., CA3028A ••d CA30288. oturelor CA30S3.
3 DC COLLECTOR SUPPLY \I'OLTS1\t:Cl> 6
-5 -10 [Link] - AGC bias current 'est circuit (differential·
OC EMITTER SUPPLY VOlTS (VEE) amplifier configuration) lor CA3028A and C.4.30288.
Fig.7 - Operating current vs. VEE voltage for CA3028A Fig.8b • AGe bias current vs. bias volts ([Link] No.7)
• ndCA30288. I., CA3028A a.d CA30288 .
CASCOOE CONFIGURATION
DC COLLECT SUPPLY 'Io'OLTS (Vecl AMSIENT TEMPERATURE (T A I =25 G C
DC EMITTER SUPPLY VOLTS (VEE)
.l "'1----- ~.,..
g *----~--_+--+-4-4_+-~~~~~J~.-~
! ~~---+--~--~t-t-~_+-+-+_+~
~ 't----4---+--t-4-4-+-~-4--~_+1
100 3-30 3-30 O.l-o.2S JS<I.
..
.. FOR POWER GAIN TEST
.. FOR NOISE [Link] TEST
Fig. JOa • Power gain and noise figure test circuit (cascode 10 t 3 4 S .; , I 9100
120 FREQUENCY (f! -MHz
AMBIENT oTEMPERATURE (TA1-·C
" e •• ligu,.'; •• ' I", CA3028A, [Link] CA3053*.
Fig.9 - Device diSSipation vs. temperature for CA3028.4. * 10.7 MHz Power Gain Test Only. Fig. lOb - Po",.rgain vs. frequency(cflscoJe confi'lurotion)
.nd CA30288. I", CA3028A a.d CA30288.
CASCOOE CONFIGURATION
AflBENT TEIFEAATUtE IT., )-2'·C
FREQUENCY ('1-100 ..HI: TYPICAL NOISE FIGURE AND POWER GAIN TEST CIRCUITS AND CHARACTERISTICS
I
~
~
;;; .9
[Link] - Powergfl;n ond noise ligure test circuit (Jillerw
9· 10 II 12 entia '-amplifier conli gurat jon and terminal No.7 connected
DC COLLECTOR SlM'lY [Link] 1"teI M~l c~ c~ ;~ ~
107 30-60 20-!50 3-6 3-6
t. VCC) I", CA3028A, CA30288 ••d CA3053*.
Fig.10c - 100 MHz noise figure vs. collector supply 100 2-15 2-~ 0.2-0.5 .2-0.
• FORI POWER GAIN TEST
* 10.7 MHz power Gain Test Only.
volts (cas code COlI figuration) for CA3028A anti CAl0288. .. FOR NOISE FIGURE TEST
________________________________________ ~-------------------------105
CA3028A, CA3028B, CA3053 Types
TYPICAL TEST CIRCUITS AND CHARACTERISTICS
OIFFEAENTIAL-AMPLIFIER COWlG\RATtoN r--~~--r--~-r--~
AMBlE",l TEMPERA1URE ITA)' :!!5-C CONSTANT POWER NlUTo211W
'",
a\(~c~-t:: "
~
t-- :rJ.~~ ~~~~r-~~O~f
c,
I
~o 'it ~r, VOLTMETER
,
I, f;CA
" ·i·lI~ t--
E
a 1- .b..
FI,.20a • Output power telt circuit for CA3028A and
.'0
FREQUENCY IO-MHr
H~" 100
CA30288. Fi,.20b . Output power vs. frequency - 50 n inpu, and Fi,.2'a • AGC ran,. test circuit (dlfferen"al ampUI'er)
50n OU'put ([Link] configuration) lor I., CA3028A and CA30288.
CA3028A and CAJ0288.
.0
our"..,.
'------t--<J
DC lIAS VOLTS ON TEJtIIIIIAL. .... 7 "CS-I4!101i INPUT VOLTS I "I.. )
HCS- .....ltl
FI,.2.b. AGCcharacferllticllor CA3028A anJ CA30288. F;g.22a. Transfer cltorocterl't/c (voltage gain) tes' FI,.22b - Trans/[Link] (cascoJe conliguration)
circuit 00.7 MHz} cascoJe configuration lor CA3028A, I., CA3028A, CA30288 and CA3053.
CA30288 and C A3053.
Vee
OSCILLOSCOPE
WITH HIGH-GAIN
DIFFERENTIAL
INPUT
(TEKTRONIX TYJlE
530. 540. OR 580
.0 WITH TYPE 0 PLUG~IN
.R
TEI(TRONIX TYPf 502,
EQUIVALENT)
VEE
• For R ·l.6kfl-(VcC -12V, VEE' .J.2V1
ForR-2kfl -(VcC' 6V,VEE··6VI
___ "'507
Fi,.22c • Transfer characteristic (Yolta,e ,ain) [Link] Fig.22J - Transfer characteristics (Ji/ferentlal-amplilier Fl,.23 - Dillerentlal voltage ,ain, maximum pealc~to~"HIc
circuit (10.7 MHz) J iHeren,[Link]"lilier conllguratior. • anligura,lon) lor CA3028A, CA30288 and CA3053. output voltage, and bandwidth test circuit lor CA30288 •
lor CA3028A, CA30288 and CA3053.
For Input common-mQde yolt. . ranae test: 51 to Vx
Common mode .ejectlon ratio =20 10110 (A·) (2) (0.3)
VDlFF(RMS)'
• A =5inlle--ended voltap lain.
Fi,.24 - Comman-maJe [Link] ratio anJ common~"e
in"[Link]/tage range te.,
circuit lot C"'30288.
____________________________________________________________________ 107
CA3039
Diode Array APPLI"A T/ONS
• Balanced modulator. or d_aclulators
Six Matched Diodes on a Common Substrate
• Ring modulators
ULTRA·FAST FOf Ap,licatiDls il • High .,.H diode gates
LOI·CAPACITANCE ea•••• icali••s a.~ • Analog switch ••
lATCHED DIODES [Link]~ill Systells
Fig. r - Schematic Diagram lOt C4JOJ9
The RCA-CA3039 consists of six ull1'&-188t. low capac- FEATURES
itlllce diodes on a common monolithic substrate. Inte-
grated circuit construction assures excellent [Link] and • [Link] rever•• recovery .i,.. _1 ns typo
dynamic matching of the diodes. making the ..ray ex- • [Link] .onolithic construction_
tremely useful for 8 wide variety of applications in ABSOLUTE MAXIMUM RATINGS AT T A - Z6 a c
communication and switching systems. VF match" within S.v
• Low diode copocitenn_ DISSIPATION:
Five of the diodes are [Link] accessible. the CD .. 0.'5 pF typical at VR " _ 2 V Anyone diode unit . . 100mW
sixth shares a COImlOll [Link] with the substrate. Total for device .
. . • • . .• 600mW
ForTA>SSoC . . . c\eratalinearly 5.7 mWfDC
• The CA3039 is available in a sealed-junction TEMPERATURE RANGE:
For applications such 8S balanced modulators or ring Beam-Lead version ICA3039Lt. For further
modulators where capacitive balance is important, the Operating . . . . . -55 to +1250 C
information see Fila No. 515, "Beam-Lead Stonge . -65 to +1SOOC
substrate should be returned to a DC potential ¥Alich is Devices for HVbrid Circuit Applications".
significantly more negative (with respect to the active LEAD TEMPERATURE lOuring Soldering):
diodes) than the peak signal applied. At distance 1/16 ± 1/32 inch 11.59 ±O.79 mm}
from case for 10 seconds max. • • • • . + 2650 C
PEAK INVERSE VOLTAGE, PIV for: 0,-05. 5V
06· . 0.5 V
PEAK DIODE·TO-SUBSTRATE VOLTAGE, VOl
for D,-D5Iterm. 1,4,5,8 or 12 to term. 10) . +20,-1 V
DC FORWARD CURRENT, IF • • • . • 25mA
PEAK RECURRENT FORWARD CURRENT, If 100mA
PEAK FORWARD SURGE CURRENT. If(SUra.} l00mA
ELECTRICAL CHARACTERISTICS, at TA = 250 C TYPICAL CHARACTERISTICS
Characteristics apply lor each dlocl. un", un/en otherwise .pecUieJ.
CHARACTERISTICS SYMBOLS SPECIAL TEST CONDITIONS
LIMITS CHARACo
TERISTIC
UNITS CURVES
.. AMBIENT TEMPERATURE ITAI·~II
II~·
~
6 f
IF·50pA
MIN.
-
TYP.
• 0.65
MAX.
0.69 V
~
!
~ 0>
/
.~
l~"~ ., !
5 _~
DC Forward Vollage I)op VF
ImA
3mA
-
-
0.13
0.16
0.78
0.80
V
V
2
I 0'/
V t, ~
tt
lOrnA 0.81 0.90 V ~ 2
DC Reverse Breakdown Vollage V(BR)R IR' -10pA 5 7 - V - ~<If.' , ~
DC Reverse Breakdown Vo~age
Belween any Diode Unit and Substrate V(BR)R IR' -1O/'A 20 - - V - - ,-- , ... , ...
... ~'f-~;"!rr'!..:r
DC FORWARD MILLIAMPERES II",
DC Reverse (Leakage) Currenl IR VR' -4 V - 0.016 100 nA 3
Fig. 2 • DC 'o..,a,d yo/fag. drop (any diod.) and diode
92CS-I5261
DC Reverse (Leakage) Currenl oHse, vo/top vs DC IorwarJ cu"ent
Between any Diode Unit and Subsbale IR VR·-l0V - 0.022 100 nA 4
Magnitude of Diode Oflset Voltage
(Difference in DC FINward Voltage
I)ops 01 any Two Diode Units)
I VFl - VF21 tF·l mA - 0.5 5 mV 2 DC REVERSE VOLTAGE IV J. 4V
Temperature CoeffiCient of f Fl- VF21
L'lIVFl - VF21
IF·l mA - 1 - [Link]"C 5
.."
L'lT
i /
Temperature Coefficient 01 Forward Orop
L'l VF
L'lT
IF -I rnA - . ~1.9 - mVI"C 6 i .
0.1:
DC Forward Vottage I)op lIN
Anode-la-Substrate Diode (OS)
Reverse Reoovery Time
VF
Irr
IF·l rnA
IF • 10 mA, IR • lOmA
..
-
0.65
1
-
-
V
ns
-
-
~
•
~
Q~
.
:
,
- /'
Diode Resistanct
Diode Capacilanct
RD
CD
I. I kHz, IF' 1 mA
VR ·-2 V, IF'O
25
-
30
0.65
45
-
n
pF
7
8
0.00'
." ... ." " ..
AM81ENT TEMPERATURE [Link]--C " "'"
...
Fig. 3 - DC revers.· (lealcap) current (diodes 1,2,3, ..,5J
Diode-ta-Substrate Capacitance COl VOl • +4 V, IF ·0 - 3.2 - pF 9 vs temperature
This device is supplied in the hermetic 12·lead
TO·S style package.
___________________________________________________________________ 109
CA3040
Video and Wideband FEATURES
• High Dlffe,ential Push,PIIII Valtage Gain •••.•• 37 dB typo
t".
Amplifier •
•
Singl •• End.d Voltog. Goin.................... 31 dB
Wid. (3dB) Bandwidth................................ SS MHz
Balanced Inpllt ond Output
typo
• High Input R•• lstanc. ............................... 150 kO: typo
for [Link]! .d •
•
Low Output R•• [Link] ............................... 1250:
Bias Option. for Temp.,ature [Link]:
typo
Commercial Equipment at Bia. Mod. A: "Constont" Voltoge
Bias Mod. B: "[Link]'" Goin
• Supplied in the hermetic 12-lead TO-S stvle
frequencies up to 200 MHz package
The RCA CA3040 is a monolithic silicon integrated APPLICATIONS
circuit designed. to meet the requirements of a wide • Video Ampllfi., • Modillator • "'b:er
• SchmlH Trigger • IF Ampllfi., • DC Ampllfi.r
variety of applicaiions requiring high gain and wide band-
width. The cascode-connected differential amplifier • Sense Ampllfle,
achieves a double-ended gain 0(37 dB with a typical 3 dB
bandwidth of 55 MHz. Emitter-Follower input 8nd output
stages provide the desirable high input impedance and
low output impedance for coupling to other circuits. ABSOLUTE·MAXIMUM RATINGS
The CA3040 includes two biasing options, allowing the DISSIPATION· . . . . • • . . . . . . . . . . . . .. 450 mW
user to optimize his design over the entire military Derating factor for TA > SSoC. . . . . . . .. 5 mW/"C
temperature range 0( -55 to +l25"C. BI .. Mod. A yields SUBSTRATE [Link]£
TEMPERATURE RANGE:
a Bubstantially constant voltage at the output tenninals ALL AISISTANCE VALUES IN leO. ·S.
for [Link] using DC coupling to succeeding stages Operating . . . . . . . . . . . . . . . . . _550C to +125°C
or requiring maximum dynamic range over the temperature Storage ••••••••••••••••••• _650C to +15O"C
range. DC output voltage varies less than 0.1 volt (typi- LEAD TEMPERATURE (During Soldering): FI,.I • 'c••matlc 01." ... fo, CA3040
cally) over the entire temperature range while gain v81ies
±2 dB. Bias Mod. B provides extremely stable gain AI distance 1/16 ± 1/32 inch (1.59 ± 0.79mm)
over the temperature range. Gain variation is 0 dB (typi- from case for 10 seconds max. •.•.••..••• +26S oC
cally) in this Bias Mode. DC variation is ±O.S volt. • Limitation imposed by the thermal resistance of package.
Provisions are also made for stabilizing the operating
point for either single or split power supplies.
MAXIMUM VOLTAGE RATINGS.t TA =25·C
The following chart gives the range of voltages which can be applied. to the tenninals
listed vertically with respect to the terminals listed horizontally. For example, the MAXIMUM
voltage range of the vertical terminal 2 with respect to terminal 11 is 0 to +14 volts. CURRENT RATINGS
STATIC CHARACTERISTICS TEST CIRCUITS
TERM- TERM-
INAL 1 2 3 4 S" 6 7 8 9 10 11' 12 INAL lIN lOUT
No. No,' mA mA
I 0
·1'
. . +1'
0
· +10
-10
· · · · +1'
0 1 5 5
2 . '1'
0
+1'
0
+1'
0
· · · +1'
0
+1'
0
+1'
0 2 - -
3 . '5
-3
· · · · · · +5
-3 3 5 5
4 . · +3
-3
· · · · · 4 I 0.1
Fi,.2(.' - Bi.s MaJ. A
,
5"
· +10
-3
· +3
-7
· +
0
Note
I
5 - -
6
· · · · · · 6 I 0.1
7
· · · · +10
-<I
7 5 5
8 +3
-3
· · · 8 5 5
9
· · +7
-3 9 I 0.1
10
· · 10 - 10
1\'
" · 1\ - - Fig.2(.' • BI•• Mod. B
12 12 - 10
... Rer(!f'(>nCt~ [Link] " Voitales are not normally applied between these terminals.
Volta,es appearilll' between these terminals will be safe if
Note 1: External connection required for sroper operation. the specified limits between all other terminals are not
exceeded.
____________________________________________________________________ 111
CA3040
OPERATING CONSIDERATIONS
.
:~
General
The CA3040 is designed to provide flexibility in
the selection of power supply configurations and to
provide the circuit designer the choice between two modes
of temperablre- compensated perfonnance. Mode A,
which provides constant DC output voltage, is recom--
~-~~~-~-
-- -
mended for most applications. Tit!;! control of the oper&- r-
ting point provided by this mode maintains the dynamic
range of the device while gain variation over most of 4
I
the range is less than ±1 dB. Mode 8 provides constant I
'0
gain for applications where this consideration is critical, I
but will exhibit 8 reduction of dynamic range at the
0.4 0.5 400
temperature extreme 8. RillS OUTPUT VOLTS ('0110 [Link] SOURCE RESISTANCE (lIts) -OHMS
Power Supply, Considerations Flg.7 ·3d8 80ndwiJth .s Sing/e·Ended Output Vo/toge Fi,.8 -Hoi.. FilUr. (HF) YS [Link]
Figures 2 and 3 illustrate the use of the CA3040
with balanced dual supplies and single power supplies,
respectively. Both figures demonstrate that the inputs
may be directly referenced to the center point of the
supply (ground in Fig.2) by closing the included switch.
This is the natural connection in Fig.2. This connection [Link] TEMPERATURE ITA'-2.5-C
is optional, however, and need not be made. Use of this MODE A,swm;H [Link].3Ial
connection in Fig.3 implies the presence of another
DC supply or a "stifr' bleeder. If such a source is VIC) OR '01'2 (SWITCH oPtM OR CLOSED)
present its use is suggested in order to maintain maxi~ ...., A
mum common mode range. Dynamic performance and
dynamic range of the output circuit are unaffected by the
choice of biasing scheme used so that in most cases
direct connection of Tenninal No.1 to the center point
of the supply is not recp.1ired. Where direct connection II) (SWITCH OPEN. MODES A OR BI
is oot used, Tennioals No.4 and No.6 must be biased
from Terminal No.1 for proper operation.
High-Frequency Considerations
B 9 10 II 12 1'5 14
-50 -2.5 0 2.5 50 7S 100 125
Stable high-frequency ~peration requires that proper AMBIENT TEMPERATloRE tTAl--C
COLLECTOR SUPPl.Y [Link] IVCCI
high-frequency construction techniques be followed.
The photograph of Fig.6 illustrates the precautions Fig.9 - Output Valts or Input Bias Reference Volts F;,.10 • Collector Supply Current Drain (12)
taken in the construction of the test circuit of Fig.a. vs Am},;en, Temperature '11'5 Collector Supp./y Voltage (Vee)
Extreme caution is required because of the extended
gain bandwidth capability of the device. OscjIlations
have been observed in the 4OO~to~800 MHz range when
precautions were not taken. ~In addition to normal cc:m-:
siderations of shielding. parts layout, and isolation,
the following specific suggestions are made:
1. Use sockets only when necessary. Sockets, when COLLECTOR SUPPLY VOLTS IVcc)-+12
used, must provide shielding within the pin circle. MODE SWITCH [Link].31a)
The socket shown in the chassis of Fig.6 is a
Barnes MJ-l2Ol, or equivalent, modified by drilling
a 1/8" hole in the center and inserting a grounded
brass pin. .
is 10
2. Do not bypass Terminal No.9 in normal operation.
Fig.3 showB the' use of neutralization between 5
Terminal No.9 and one output to balance the amplifier
at high frequencies. Experience shows that stable
operation, while possible, is difficult to achieve
if Terminal No.9 is bypassed to groUnd.
3. In DC testing, 1 kO, V 4 W carbon resistors sbould
be soldered directly to the socket Tenninals No.4 -!IO -2S 0 2! !IO ." 100 '25
AMBIENT TEMPERATURE ITA'--t
and No.6 to suptl'ess parasitic oscillations. All AMBIENT TEMPERATURE (TAI-'"C
current .carrying connections are made at the other
end of the resistors. Direct sensing of Terminal Fig. 1 r - Colfeclor Supply Current Drain (l2J Fig.12 . [Link] Diilerential Voltage Gain
No.4 or No.6 voltage should not be attempted. vs Ambient Temperature vs Ambient Temperature
_________________________________________________________________________ 113
CA3045, CA3046 Types
ELECTRICAL CHARACTERISTICS, at TA = 25°C STATIC CHARACTERISTICS
Characteristics apply lot each translstot In tbe C43045 aoJ CA3046 as speclll.J
LIMITS
CHARACTERISTICS SYMBOLS SPEIliAL TEST CONDITIONS Type CA3045 . UNITS
Typ, CA3046 '0'
MIN. I TYP. I
MAX. f I
DYNAMIC CHARACTERISTICS "£ ?
:; 10 8 "
Low-Ffequency NOise Figule NF 10 1 kHz, VCE' 3V,IC' lDOpA 3.15 dB i :-
Soun:. Resistanc. = 1 kll
Low-Frequency, Small,Slgnal
EQulvalent,Clfcui! Charactellstlcs:
! I·
J --.....
I
Forward Currenl·Translel RatiO hi 110
Short-CircUli Input Impedance hi, 3.5 ~:
Open-elfe"" Output Impedance hoe I =I kHz. VeE' 3 V, Ie = I rnA 15,6 IImho
~"Reverse
Voltage-llaRsfer Rallo
Admittance Characterlsllcs:
hi,
I 1.8,10. 4
Forward Tr3nsfer Admlltance
Inpul Admittance
Output Admlltance
YI,
YI ,
YIII!
' = I MHz, VeE
I
=3 V. IC =I rnA
31'11.5
0.3'10.04
0.001,,0.03 Fig.3 - Typical [Link] cutoll CUllen' vs
Reverse TI3nsfer Admillance Y" ! See curve ambient temperature lor each transistor.
Gain-Bandwldlh Product IT VCE =3 V. IC =3 rnA 300 550
Emitter-to-Base Capacitance CEB VEB =3 V. IE =0 0.6 pF
Collector·lo-Base Capacitance CCB VCS =3 V, IC =0 0.58 pF
Collector-fo-Substrate Capacitance CCI VCS =3 V, Ie ·0 1.8 pF
10 8 COLLECTOR~TO-£MITTER VOLTS (VCE",s
001
:-
4 I; BO.I 4 IS 8 I " &810 001 2 " 6 '0.1 " f" I
EMITTER [Link] (IE) COLLECTOR MILLIAMPERES IICI
Fig.4 - Typical static lorwarJ [Link] lotio find Fig.S • Typical input ollset curlent 101 [Link] Fig.6 - Typical stotic base-to-emitter yo/toge characte,-
Iteto ratio lot tronsistors 0, and 02 vs emitt., cUllent. tlons;stor poil 0,02 YS [Link]" CUllent, istic anJ Input oHset vo/tog. lor [Link] pair onJ
paired isolateJ transistors vs emitter current.
[Link]-TO-EMITTER VOlTS 'VeE). 3
COlLECTOR-TO-EMlTTER VOLTS I 1-3
Q2.
OA
-75 -50 -~
2. '" 100 12' ·75 -2$02:15075100
AMBIENT TEMPERATURE ITAI--c
Fig. 7 - Typical base-to-emitter voltage charac- Fig. 8 - Typical input offset voltage characteristics
teristics vs ambient temperature for for differential pair and paired isolated
each transistor. transistors vs ambient temperature.
________________________________________________ ~-----------------115
CA3048
Amplifier Array For Low-Noise aid
General AC Applications
FOUR INDEPENDENT In Inoostria! Service
Ae AMPLIFIERS
The RCA CA3048 is a silicon monolithic integrated [Link] high gain amplifier halo; a high impedance non-
circuit consisting of four independent identical AC inverting input, and a lower iml)('dancC' inverting input
amplifiers which can operate from a single--ended power for the application of fCl.'{lback. Two llOwl'r-SuJlply
supply. terminals and two ground tl'rminais arc prO\'ided to n .....
duct' internal and external coupling retwcf.'n amplifiers
The amplifiers includc internal DC bias and fcroback
to provide tempL'l'ature-stabil izcd operation. Tht''v may Tht, C'A;J{J.t8 is supplied ill a Ui-It'ad dUlll-ill-lint'
be used in a wide variety of AC' applications in which plastk' pal'kagc. Fig. J • Block diagram for CA3048.
operational amplifiers hay£, previously "('Cn USt'<i.
FEATURES
• Four AC amplifiers on a common substrate
ABSOLUTE-MAXIMUM RATINGS., TA = 2S"C: • [Link] accessibl. inputs and outputs
DISSIPATION, • Operates from slngl •• anded supply
At TA = 55°C . . . . • • . . . . . . . . . . . • . • • . • . • • • • • • • • • . • • . . • 750 mW EACH AMPLIFIER
Above TA = SSoC . . . . . . . . . . . . . • • • • . • . • • . Derate linearly at 7.7 mW/DC
• Noise figure- at 1kHz ......................... 2 dB typo
TEMPERATURE RANGE' • High voltag. gain .............................. 53 dB min .
. Operating •••• • • • • • • • • • • • • • • • • • • • • • • • • • • • • .• •• _40°C to +8So C
• High input resistance ......................... 90 1c~·1 typo
Storage. • • • • • • • . . • • . • • . . . • • • • . • . . . • . . . . . • . • •• -650 C to +l50oC
• Undistortecl output voltage ................... 2 Y rms min.
LEAD TEMPERATURE (During Soldering) • Output Impedance .................. 1 kC typo
At distance 1/16 ± 1/32 inch (159 ±0.79mm) • Open.l_p bandwiclth .. .. ........ 300 kHz typo
from case for 10 seconds max. • •••.•..••••••••.••••••...••••••• +26S oC
POWER SUPPLY VOLTAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . • . • . • +16 V APPLICATIONS
AC INPUT VOLTAGE. . . . . . . . . . • . . . . • . . • . . . • • . . . . . . . .. 0.5 V nns • [Link] or ca5cade operation
• Law.I .... ' preamplifier5
MAXIMUM VOLTAGE RATINGS
• Equalizen
The following chart gives the range of voltaaes which can be applied to the terminals • Linear 5i.,a! mixers
listed vertically with respect to the terminals listed hori,olltally. For eX8lTlpl., the
• Tone generotors
voltage range between vertical terminal 2 and horl,ontal terminal 4 1s +2to-3.6 volt ••
• Multivibrators
TERM- • AC integrators
INAL 4 10 11 12 13 14 15 16
No.
+\6 a
a -\6
+2 +2 -3.6
+16 +2 +16 o
-3.6 -3.6 o -3.6 o -16
+5
-5
+3.6 on
-2
a +2 +2 0 +16 +2 +16
-16 -3.6 -3.6 -16 a -3.6 a
0
-16
+5
-5
+5
-5
10
11
12 o
-16
13 +5 • CONNECT TO ""'IICI"RIATE TI!UIMAl TO II!AD YClLTAGE
-5
14 Fig.2 • Test circuit for measurement of collector
supply vo/tug. anJ currents.
15 +16
o
16
.. Voltages are not normally applJed between these terminals.
Voltaees appearina; between tbese tenninals will be safe if tbe
specified limits between aU other tenninals are not exceeded.
_________________________________________________________________ 117
CA3048
lIT
~ - l-t
INPUT SIGNAL VOLTAGE IE IN " II'IIV RMS LL ORWLYV (Vcc.t!
COLLECTOR 5UPPL Y VOLTS (Vccl •• 12
·
OI'IERATING FREQUENCYltl' I ~H, RMS INPUT SIGNAL MILLIVOLTS (EINI' I
AMBIENT TEMPERATURE(TA)' 2S O C
AMBIENT TEW'ERATURE (TAI'2~'C OPERATING FREQUENCY • 11oH~
· -
--
-
R"
I!I
- f--
r-, (1
· 1\ ~ I
j-I
·
!
--
~-~
DC SUF'PLY VOLTS (VCCI
A1118IE~T TEMPERATURE (T AI-·C
· 10.000 100.000
Fig.7 . Typical amplifier go;n vs DC supply voltage. Fig.9 • Typical open-loop gain ys frequency.
Fig.8 - Typie:ol open-loop gain ys ambient temperature.
'"
I• •
AMBIENt tEMPERATURE (TAI-'C
Fig. 10 - Typical total harmonic distortion
• RESISTORS ARE METALFILM T¥P£.I'Io
vs ambient temperature.
• Ll' 2.5 millihenry inductor, dc resistance 0.3 ohms or less.
To test Amplifiers 1, 2. 3. Of 4, connect terminals as shown in
Table. >I< f:~ii~~t: a~et:~o~i~~n ~:Ie 1%. To test a-nplifiers, connect
TERMINALS TERMINALS
AMPLIFIER AMPLIFIER
OUTPUT INPUT BYPASS OUTPUT INPUT BYPASS
1 1 4 3 1 1 4 3
2 6 8 7 2 6 8 7
3 11 9 10 3 11 9 10
4 16 13 14 4 16 13 14
Fig. F1 - Test circuit lor measurement of broadband Fig. 72 • Test circuit for measurement of "weighted"
noise characteristic. output noin yoltoge characteristic.
C.""'''''''''''.'''''''''']I J 1111 I II
OP1![Link] FREQUI!NCY III- 1 kH. OOS.F
OPERATING CONSIDERATIONS
-'--'"""" [~ Economical Ga in Control
.
~o 14 - The CA3048 is designed to permit flexibility in the
methods by which amplifier gain can be controlled.
r-. """}.'" ""
GEN
I • I .11.
-.F 11 PTYPE
~oo 0
Fig.14 shows a curve of the gain of an amplifier when
t-.. RFB (OR EQOI~I
the internal resistive feedback of the device is used in
" II I
conjunction with an external resistor. Although meas-
ured gain of various amplifiers will not be unifonn,
.
10
because of tolerances of internal resistances, this
l'il method is very economical and easy to apply .
II Stability
", 10.000 100.000
The CA3048, as in other devices having high gain-band-
RESISTANCE IN FEEDBACK CIRCUIT (RFSI
'" V.T.V.M.· Hewlett-Packacd Model 4000 or equivalent. width product, requires some attention to circuit layout,
Procedure:
design, and construction to achieve stability.
Fig. 74 . Typical amplifier gain vs feedback resistance.
1. Adjust Sl,nal Generator fOr 0 dB output at leference terminal. Should the CA304B be left unterminated, socket capaci-
2. Read voltage at other output terminals (Figure shows terminal #1 tance alone will provide sufficient feedback to cause
used as reference). high frequency oscillations; therefore, all test circuits
Fig. 73 • Test drcu;t for measurement of inter-amplifier in this data bulletin include loading networks that pro-
audio separation "cross talk" characteristic. vide stability under all conditions _
____________________________________________________________________ 119
ELECTRICAL CHARACTERISTICS ot TA • zli"c
CA3049T, CA3102E
TEIT
CIR- CAJIMIT LlII,TS
CH_
TYI'tCAL
TEST CONDlnONB CUlT TEIIIITICS
CHARACTERISTICS SYMBOLS CUIIYU
FIG. MIN·I TYP. IMAX. UNITS ',G.
STATIC CHARACTERISTICS
For EtlCh Dln.,.."I., Am IIf....
0.2. -,
Input Off..t Vo....
Input Offld [Link]
V,O
',0 0., .A
'3-'9- 2m"
13.5 32 .A
Input B 1M Current
T.m.-,.tur. Co-'fk:"nt M... IIAVIOI
nlNcHlo' Input-Oft.t VOltaQII .b.T
liB
... I/oV,·C
I
F •• hT,.",1stor COllECTOR CUfRENT {lei-iliA
DC Fgrw...d 8_to-
EmltterVol..- Va.
AVSE
Vce- ev
Ie'" rnA ".
TempwiItUre COeffk18nt of mY/oC
VeE" 6V, Ie· 1 mA -0..
._.to-Eml«.. Vol....-
.
AT
Collector-Cutoff Cu,,.n, I Vc .. 10 V,le" 0 0.0013 '00 nA
Collector-to-Emitur 2. V
VIBR)CEO Ie" 1 rnA. la" 0
B,..kdoWn VolUtlll
ColI..::tor-to-a... 20 60 V
VIBRICBO Ie" 10 JoIA, 'e '" 0
atellkd\)wn Volt_
[Link] 20 60 V
VIBAlelO Ie" 10/olA, '8 = 0, Ie ,. 0
8'Hkdown Volt...
Emituor-to-8_ B,. .kd_" V
Ie'" 10 ",A, Ie ~ 0
VOigt.' VIBRIEBO
DYNAMIC
CHARACTERISTICS
1/f Nola FlguHl (For
Sin I. Tr.n.,tor'
~~in-aandwld1h roduct
NF
f = 100 KH3_ AS '" 500 H
IC'" 1mA
..• dB 12
IT Vce - 6 [Link]" 5 mA 1.36 GH,
(For Singl. Tr.,.linorl
0.28 pF
Collector·a ... [Link] eeB IC" 0 Vca" 5V pF
0.20
Collector·Sub,tr••• C~.c:i'.nc. CCI Ie'" 0 VCI = 5V 1.65 pF
F:~_~~.~iff....nti.1
Common-Mod. R.jR1ion Aa,lo
A .n•• On.S....
CM"
AGC
13'" 19- 2 rnA
Bia, Voltll... -6V ,.
'00 dB
dB
Volt. . [Link]. Sing.. Endad Bia, Volt.... '" -4.2V 22 dB 9.10
A
...
OUtDut f'" 10MH:
InMrtion Po_r Gain t'" 200MH: [Link]. 2. d8
[Link]...r. NF VCC" 12\1 CalCoda dB
For Cascod. 1.5'" j 2.46 14,16.18 100 -." 150 -2' 0 25 150 75 100
Cascode
Configuration mmho
Input Admit1llnc:. v" .. 16.17.19 AMBIENT TEMPERATURE ITAI-·C .rCS-2Q7'II
13 = 19" 2 rnA [Link] . 0.B78'" j 1.3
Fig. J-Co/lector-cutoff cummt va. ,."",.",ru,..
For Oifl.
Ampllli... CatcOd. 0- j 0.008
Rev.... Tren"'.r Adminanc::. v.2 mmho
Configuration
13= 19" 4mA [Link]. 0- j 0.013
(each Ca..:od. 17.9 - j 30.7 28,28.30
Forward Transf.r Admlnanc:. v2. mmho
c:ollec:tor
IC:2mA) Diff. Amp. -10.6. i 13 27.8.31
Cesc:CId. -0.503-115 20.22.24
Output Admittllnc:. V22 ",mho
[Link]. 0.071 + j 0.52 21.23,25
"T..minal,l • 14. or 7"8. ICA3102EI ' . 12 or 6"
7 ICA3049T1
··T..minel, 13 .. 4. or 6 .. ,,_ (CA3102EI 10 ... 11 or"'" 5 (CA3049T1 AIBENT TEflW'ERATURE ITA'. 215-<:
POSITfYE DC SlPPLY VOLT_ IV·)· .IV
NEGATIVE DC StM"PL'f' VOLTAGE (Y-)_-IV
FREQUENCY cn-11IHlI
0.01 2 4 & aOJ :2 '" 6 II Z '" 6 110 61100
FREQUENCY (f) - MHz
DC lIAS VOI.1AIE ON 1"I!MIJMI..S 2AHO 10-V Fig. 10-Voltllgegllinv... frequency.
Flfl. 9- VCJI,.,.,.n n. de bia Il0l,.,,..
DC 81AS VOLTAGE IVBI-v
,
Fifl. B-CapecitlltlU w. de". ~
AMBIENT TEMP£RATURE (TAI= 25"C
RSOURCE • soon
AIB!NT TEMPERATLM (1A) ·25·C 3D
"
~'tft
20
/'"
,./"
~
// Vf"
/'"
'V --
::-1- I--
V
~ ~ V-
COLLECTOR QJRRENT IIc)- InA
001
~
4 6 801
COLLECTOR CUflfIENT (lCl-mA
---4 6 8 I
loOKHl
~
00' & 110.1 '"
COLLECTOR CURRENT (!cl-IIIA
6 II
92C$:2080!l
Fig. t I-Gllln-bllndwldth product liS. colteCtor curIYJnt. Fig.. , 2-1 h noise figure vs. collsctor current. Fig. 13-7# noise figure vs. colltICtorcurrent_
----------------------------------------___________________________ 121
CA3049T, CA3102E
Typlcll Output AdmittllllCl Chor_ri..... for CA304IT ond CA3102E
'"
22
-6
10 6 '",2 • '00'
-2
I. " '0' • 'r} 10 20
COLLfcTOR SUPPLY VOLTAGE (Yccl-V
10 4.
FREQUENCY 1'1 - MH~ FREQUENCY tf 1 - MH.
ft1S-M41
I!i
10 20
COLLECTOR SUPPLY VOLTAGE (VCC'"V
30 40
EIIITTER CURRlNT a,.IgI- lit" I.
Ir.lT1!R CURRENT
I. ••
TVIIicll - . . Tro _ _ _ for CA304tT oncI CA310n
CASCOIlE AMPLIF'IEft
j ~:;~o:.L~~=~R~1~ ~~i~'I:J:
i
iW"'; ..••
AIle£NT TEWER"TURE (TAl' 25"C
Ii ~
18 '11
~~
"
~o
I.
I.'
~~
~ I. \. ~
I • •
e -I.
. , .,,'r-!21 , . , .
_20'"
-2.
10
,
FREOUENCY I' 1 - .. H,
1-40
10 " '10 2
FREQU£NCY If I - MHI
•
'ISS-St4.
r} I. . .
Pif. 21-FotvMld [Link]» (y2tJ .... frItIWnt:r. FIf. 2B-Forw.t'd UtHJI'" MJmlfWtCtl fY21J ..& h//a:tOr I11/III'"
..".,..
."
IFFERENTIAL AMPLIFIER
COLLECTOR SUPPLY VOLTS CI,"lglo.
OPERATING FREQUENCY (fI- zoo MH,
AMIIENT TEMP£RATUREITA,-2"C
-0
COLLECTOR SUPPLY [Link]'-V
.. •
EMITTER CURRENT [Link]-mA
I
-2.
• II
'MI'fER CURfl£NT lI"ltl-1IIA
..
Fig. 29-Fo,..«1 [Link], .[Link] (Y21J VI. coll«:[Link]"yvo/,.
.p-
________________________________________________________________ 123
CA3050, CA3051
ELECTRICAL CHARACTERISTICS ot TA = 2SoC 60 AMBIENT TEMPERATURE ITA).U.C
aoo
i ..
TEST TYPICAL t!
CIft.. LIMITS CHARAC-
CHARACTERISTICS SYMBOLS TEST CONDITIONS CUlT CA30SOlCA31l51 UNITS TERISTICS
CURVES
FIG. MIN. I TYP. I MAX. FIG. ! '0
STATIC ~
--
zo
Amplifi., Characteristics ~
Input Offset Voltage VIO - - 1.5 5 mV 2a,b I '0
II
Input Offset CURent
Input Bias Current
110
IIIl
-
-
-
-
7
200
70
500
nA
nA
aa,b
4a,b
0
ru
, . ..
II I I , . II
I(14~12)
I 10 '00
Quiescent Operating Cllrent [Link] - 0.9 1.00 1.13 - 5.,b QUIESCENT 81AS MILLIAMPUES (131
VCC-+ 6V,13- 2mA
(16+17) Flg.3(a} - Typical Input [Link] current
t-
'IS
'-13- quiescent bias c",ren'.
5O~A - - 0.645 0.700
DC F......rd ea...[Link] VQltage VBE VCE' 3V ~: -- -- 0.725
0.760
0.800
0.B50
V 6
10 nil - - D.l105 0.900
[Link] Coefficient of B....t.. l;V BE
Emitter Voltage '"Tr'"" VCE - 3 V, IC - 1 mA - - -1.9 - mVI"C 7
Transistor [Link]
Collect..-Cutoff Cllrent ICBO VCB - 10 V, IE - 0 - - 0.002 100 nA 8 =",
Collector·tD-Emitter Breakdown Voltage
Collector-t.. ease Breakdown Voltage
VBREEO
VCBRlCBO
lc - 1 mA, 18 - 0
Ie - 10,.A, IE - 0
-
-
15
20
24
III -
- V
V
-
- L
i
Collector·t..Substrate Breakdown [Link] V(BR)CIO Ic - 10 ,.A, ICI - 0 - 20 III - V - Ii 25 I 2
Emitter·tei-Base Breakdown Voltage V(BR)EBO IE - 10,.A, Ic - 0 - 5 7 - V -
DYNAMIC ~ ~ ~ 0 e ~ ~ ~
AMIIENT TEWERATURI: IT"--C
Transistor Characteristics
Emitter·t.. Base Capac it..... CEB I VEB - 3 V,IF - 0 I - I - I 0.7sl - I pF I 9 FI,.3(6) - Typicv/ Input ." •• t c""nt ••
Collect..·t..ease Capacitance teR I VCR-3V,Ir,-0 I - I - I 0.471 - I pF I 9 odie'" tempe",ture.
Collector-t..Substraie [Link] I CCI I Vcs - 3 V, IC - 0 I - I - I 1.92 1 - I pF I 9
".plifier Characteristics
[Link]-Bandwidth Product
(F.. Single Transistor)
IT VCE - 5 V, IC - 3 mA - - 1Il0 - MHz 10
Forward Transadmittance VCC - 10 V, 13 - 2 mA 11 7 9 11 mmho 11
(With single-ended input .nd output) IY21 1 f· 1 MHz
Bandwidth at·3 dB Point BW VCC - 10 V, I - 2 mA 11 - 4.3 . - MHz 11
Input [Link] Zt VCC - 10 V,I3 - 2 mA
f - 1 KHz
12 '- 460 - kO 12
i , V
Output Impedance 13- 2mA,f-IKHz 13 - 170 - 13
I.
Zo kO n'
COIlllllOO-Mode Rejection Ratio CMR ~- 2mA,I- 1 KHz - - 65 - dB -
~e~:"~N!.; ~~ - - - , ,/ I
AGC Range AGC 11 III dB
001
. . .,
/' , • II
INPUT BIAS NANOA. .ERES II II
, . I .....
I
Flg.4(a) - Typical ."escent "a. cU"enl va
Input "as cuttent.
~
,..~I. AMBIENT TEMPERATURE (T.I-2!5-C
~~~ {!I COLLECTOR SUPPL.Y VOLTS (Vee l -. S
'·'f---H-l-++t-+--++++-+-+-HH
: 0.01
; n'
a
I -I--
oof---H-l-++t-+--++++-+-+-HH
'0
j o.8'f-+--i-+++-t--++++-t-++H
5
IDO ,.. o n7
0.01 "6 0.1 " 68 1 .. 5 8 10 -75 -50 -25 2. so '00
QUIESC~T BIAS MILLIAMPERES (13) AMalENT TEMPERATURE IT,Al-·C
Fig.4(6'· Typical normallzeJ Inpul "'a. currenl vs Fig.S(o) - Typical qulescenl ope""lng cu"en' Fig.S(b} - Typical quiescent operating current
amlllen, temperature, ral'o vs quiescent hios cur,enl. ,atio V$ ambient temperature.
___________________________________________________________________ 125
CA3058, CA3059, CA3079
Zero-Voltage Switche.
For 50/60 and 400 Hz Thyristor Control
Applications
The RCA-CA3058, CA3059, and CA3079
zero-voltage switches are monol ithic silicon
integrated circuits designed to control a
thyristor in a variety of AC power switching
applications for AC input voltages of 24 V,
120 V, 2081230 V, and 277 Vat 50/60 and
400 Hz. Each of the z~ro-voltage switches
incorporates 4 functional blocks (see Fig. 11
as follows:
1. Limiter-Power Supply-Permits operation IEUTIVI TlMHIIIATUM Cor:"ICIINT
directly from an AC line. AC Input Voltage Input Series Dissipation Rating NOTE:
2. Differential OnlOff Sensing Amplifier- (50/60 or 400 Hz! Resistor IRSI for RS Circuitrv. within shaded areas, not included in
Tests the condition of external sensors or VAC kn W CA3079
command signals. Hysteresis or propor- • See chart
tional-control capability may easily be im- 24 2 0.5 • IC = Internal Connection - . DO NOT USE
plemented in this section. 120 10 2 (Terminal Restriction applies only
3. Zero-Crossing Detector-Synchr~nizes the 208/230 20 4 to CA30791.
output pulses of the circuit at the time 277 25 5
when the AC cycle is at zero voltage point;
thereby eliminating radio-frequency inter- Fig. '-Functional block dillflram of CA3058, CA3059, and CA3019.
ference (R F II when used with resistive
loads.
4. Triac Gating Circuit-Provides high-current Features CA3058 CA3059 ~
pulses to the gate of the power controlling _ 24V, 120V, 208/230V. 2nV at 50 6O,or
thyristor. 400 ttz operation ................... .. ..; ..; ..;
In addition, the CA3058 and CA3059 pro- _ DiHerentiallnput .•.•..•...•.......•• ..; ..; ..;
_ Low Balance Input Current (max.) iJA •.•.. 2
vide the following important auxiliary func- _ Built-in Protection Circuit for
tions (see Fig. 11: opened or .horted senSOr ITerm. 14) .... . ..; ..;
1. A built-in protection circuit that may be • Sensor R..... (RX) - kn ............ .. 2to 100 2to1OO 2to60
actuated to remove drive from the triac if - DC Mod. ([Link] 12) •••..•.•...•...•.•. ..; v'
the sensor opens or shorts.
2. Thyristor firing may be inhibited through
• [Link] Trigger ([Link]. 6) •.••••••••.••. ..; ..;
the action of an internal diode gate con- - External Inhibit ITerm. 11 ............•• ..; ..;
- DC Supply Volt. (max.) ............. .. 14 14 10
n~cted to Terminal 1.
_ Operllti.,. Temperllture A..... - OC ••.•••. -66 to +125
3. High-power de comparator operation is
provided !ly overriding the action of the MAXIMUM RATINGS,
zero-erossing detector. This is accomplished Absolute-Maximum Values at TA = 25°C
by connecting Terminal 12 to Terminal 7_ POWER DISSIPATION: "
Gate current to the thyristor is continuous DC SUPPLY VOLTAGE IBETWEEN TERMS. 2 Up to TA =750C - CA3058 •••..••..•• 700 mW
AND7): 0
Up to TA=55 C - CA3059,CA3079 ... 700 mW
when Terminal 13 is positive with respect
to Terminal 9. CA3058,CA3059 ................... 14V Above T A=75 o C - CA3058
CA3079 ...•...•..•.••.••...•...... 10 V . . • . • . • • . .. Derete Lineerly 8 mWfOC
For an explanation of these functions see
DC SUPPLY VOLTAGE (BETWEEN TERMS. 2 Above T A=55 0 C - CA3059,CA3079
Operating Considerations_ For de-
tailed application information, see companion AND 81; . . . . . . . •. Derete linearly 6.67 mW/oC
Application Note, ICAN-6182, "Features and CA3058, CA3059 ............... ~ . .. 14 V AMBIENT TEMPERATURE RANGE:
Applicatiolls of RCA Integrated-Circuit Zero- CA3079 •..•..............••..••... 10V Operating .••........•..... '. -55 to +125°C
PEAK SUPPLY CURRENT (TERMS. 5 AND 7) Storage .................... -66 to +1500 C
Voltage Switches (CA3058, CA3059, and
CA3079)". ........................ :!SOmA LEAD TEMPERATURE (DURING SOLDERING):
OUTPUT PULSE CURRENT (TERM. 41 Ala distance 1/16" ± 1132" 11.59 ±0.79 mm)
The CA3058 is supplied in a hermetic 14-lead 150mA from case for 10 seconds max . ...... +266 o C
dual-in-line ceramic package. Types CA3059
and C.A3079 are supplied in 14-lead dual-in- PULse 10k
line plastic packages.
Applications:
- Relay control - Heeter control VI·
- Valve control - Lamp control "'"' !
- Synchronous switching of flashing lights
- On-off motor switching
- Differential comparator with self-contained
power supply for industrial applications
- Photosensiti"e control 'IC.~IIO"
- Power one-shot control Fig. 2(b)-DC supply voltage vs. ambient
Fig. 2(8)-DC supply voltage test circuit for
temperature for CA3058, CA3059
CA3058, CA3059, and CA3079.
andCA3079.
________________________ ~ ______ ~ ___________________________ 127
CA3058, CA3059, CA3079
ELECTRICAL CHARACTERISTICS (For all types, unless indicated otherwise) v+
All voltages are measured with respect to Terminal 7.
TEST CONDITIONS
TA s 25 0 C
CHARACTERISTIC (Unless Indicated Otherwise) LIMITS UNITS
Min. Typ. Max.
For Operating at 120 V rms, 50·60 Hz (AC Une Voltage)-
DC Supply Voltage. Vs
Inhibit Mode
At 50/60 Hz RS = 8 kn. IL = 0 6.1
-
6.5 7
-
V .:=r"'"
11
OSOLLQSCOPE
GIJN
At 400 Hz
At 50/60 Hz
RS= 10kn, ll-0
RS = 5 kU. I L = 2 mA -
6.8
6.4 -
V
V ......
....LII!SlSTMC!
YALUI!SAII!
Pulse Mode Fig. 6,.)-_ output CUrT""t (puIMJd) with-'
eJCterlfll1 power supply tftt circuit for
At 50/60 Hz RS=[Link] =0 6 6.4 7 V CA3058and CA3D59.
At 400 Hz RS 10kU,Il -0 6.7 v
12I1YR",5G/tIHI,OPeItATIOtI
At 50/60 Hz Rs = 5 kU. Il = 2 mA 6.3 V AMIIEMTTElII'!ItATtIItIITAl- D'C
GAT! nlGGH YOL TAG( IV ,I- 0 v
At 50/60 Hz (CA3058) RS=[Link] =0
See Fig. 2 TA = -55 to +125 0 C
5.5 - 7.5 V
Gate Trigger Current. IGT (4 ) Terms. 3 and 2 connected.
See Figs. 3,5(a) VGT= 1 V
- 105 - mA
Peak Output Current (Pulsed). Term. 3 open. Gate Trigger
IOM(4) Voltage (VGT) = 0
50 84 - mA
With Internal Power Supply Terms. 3 and 2 connected.
Gate Trigger Voltage (VGT)=O
90 124 - mA
Term. 3 open. V -12 V. VGT=O - 170 - mA 5 10
EXTUtW. POIt!II SUPI"LY VOLTS (y +)
IS
With External Power Supply Terms. 3 and 2 connected.
V+=12 V. VGT = 0 - 240 - mA Fig. 6(b)-PelJk output current (pulllld) ...
See Figs. 5, 6 • [Link] power .upply volt.
for CA3058and CA3069.
Inhibit Input Ratio, V9N2
All Types Voltage Ratio of Term. 9 to 2 0.465 0.485 0.520 -
CA3058 TA - -55 to +125 0 C 0.450 - 0.520
See Fig. 7
Total Gate Pulse Duration:·
For positive dv/dt. tp
50·60 Hz CEXT =0 70 100 140 tJ5
400 Hz CEXT - O. REXT - 00 12 lIS
For negative dv/dt. tN
50·60 Hz CEXT =0 70 100 140 lIS
400 Hz CEXT - O. REXT - 00 10 tJ5
See Fig. 8
Pulse Duration After Zero
Crossing (50·60 Hz):
For positive dv/dt, tpl CEXT= 0 - 50 - lIS
For negative dv/dt, tNl REXT = 00 - 60 - tJ5
See Fig. 8
Output Leakage Current, 14
Inhibit Mode:
All Types - 0.001 10 IlA
CA3058 T A - -55 to +1250 C - - 20 IlA
See Fig. 9
Input Bias Current, II
CA3058, CA3059 - 220 1000 nA
CA3079 - 220 2000 nA
See Fig. TO
9l!CM'18064
Fig. 6(c)-PelJk output current (pul..d) vs.
smbien t temperature for CA3058
andCA3059.
___________________________________________________________________ 129
CA3058, CA3059, CA3079
I
.100 220 V RMS, 50/60-HI OPERATION
y+. 6V INPUT RESISTANCE tRS)d20.n
I
~
-- .--
~
i~ 400
~ f-~
i~r--T--~~~~=-~
--
c
iii
::- r- I-- ;--
,&. ~
0
~
§200 -
~ :;::::. F-
CURVE FREQUENCY
.,Y\J"-"J----. ~
A
860Hz
P!,PtFOR POSI-
TIVE d¥/dt\
~ C
o
50 HZ} 'N(FOA NEGA- -
60Hz TIVE liv/lit)
0 0.02 0.0. 0.06 0,"
EX"TERNAI.. CAPA(liANCE-,..F
0.02 0.04 M. 0.1
EXTERNAL CAPACITANC[-~F fb)
.......,
INCI-IIOII
fa)
Fig~ to-Input biBS current ten circuit for CA3058, 220VRMS
CA3059, and CA3079. 50~iO'H' OPERATION
600 INPUT RESISTANCE
.-I~.
UO "RMS. 5Q/60-Hz OPERATIOM
INPUT RESISTANCE tRsl >10 iii); IRSI'20kR
'
seNSOR RESInANCE ~ 5 114 • '00
i~
~~
TUMS.1ANDllCOtlM£CTEO JrdIO~9l
DC GATE CURMNT iM)O£\~
0.08
EXTERNAL. CAPACITANCE-~'
EXTERNALCAPoI,CITANCE-,..'
(c) fd)
Fig. II-Relative pulse width and location of zero crossing for 220-volt oparation for CA3058, CA3059,
and CA3079.
~ ~ ~ 0 H ~ ~ ~ ~
AMIIENT TElIIHlUTUIIlECTA'--C OPERATING CONSIDERATIONS
HCI-II01t
Power Supply Considerations for CA3058, 2. Set the value of Rp and sensor resistance
Fig. 12-s"".itivity VI. ambient tamparBtUI8
for CA3058, CA3059, and CA3079. CA3059, and CA3079 (RX) between 2'kn and 100 kn.
The CA305S, CA3059, and CA3079 are in- 3. The ratio of RX to Rp, typically, should
tended for operation as self-powered circuits be greater than 0.33 and less than 3. If
with the power supplied from an AC line either of these ratios is not met with an
through a dropping resistor. The internal unmodified sensor over the entire antici-
supply is designed to allow for some current pated temperature range, then either a
to be drawn by the auxiliary power circuits. series or shunt resistor must be added to
Typical power supply characteristics are given avoid undesired activation of the circuit.
in Figs. 3(b) and 3(c). If operation of the protection circuit is de-
Power Supply Considerations for CA3058 sired under conditions other than those
and CA3059 specified above, then apply the data given
The output current available from the internal in Fig. 13.
supply may not be adequate for higher power External Inhibit Function for the CA3058
applications. In such applications an external and CA3059
power supply with a higher voltage should be A priority inhibit command may be applied
used with a resulting increase in the output to Terminal 1. The presence of at least +1.2 V
level. (See Fig. 5 for the peak output current at 10 I1A will remove drive from the thyristor.
-25 Z5 SCI
.....1i!MTTeIIPI!ItATUIIE-<
characteristics). When an external power This required level is compatible with DTL
supply is used, Terminal 5 should be con- or T2L logic. A logical 1 activates the inhibit
Fig. 13-OpSlBting ragions for built·in protection nected to Terminal 7 and the synchronizing function.
circuit for CA3058 and CA3059. voltage applied to Terminal 12 as illustrated DC Gate Current Mode for the CA3058
in Fig. 5(a). and CA3059
Operation of Built-in Protection for the Connecting Terminals 7 and 12 disables the
CA3058, CA3059 zero-crossing detector and permits the flow
A special feature of the CA3058 and CA3059 of gate current on demand from the differ·
is the inclusion of a protection circuit which,ential sensing amplifier. This mode of opera·
when connected, removes power from the tion is useful when comparator operation is
load if the sensor either shorts or opens, The desired or when inductive loads are switched.
protection circuit is activated by connecting Care must be exercised to avoid overloading
Terminal 14 to Terminal 13 as shown in the internal power supply when operating
Fig. 1. To assure proper operation of the pro· in this mode. A sensitive gate thyristor
tection circuit the following conditions should be used with a resistor placed between
should be observed: Terminal 4 and the gate in order to limit the
1. Use the internal supply and limit the ex· gate current.
ternal load current to 2 mA with a 5 kS2
dropping resistor.
______________________________________ ~---------------------------131
CA3060, CA3060A Types
ELECTRICAL CHARACTERISTICS (CA3060DI -cIOOOa AMBIENT TEMPERATURE ITAI-Z5-C
For each amplifier at TA • 250C. v+ • 6 y. y- • -6 Y ... IS SUPPLY VOLTAGE :Vt.6V,Y'·6V
I
TYPICAL LIMITS i
CHARACTER- Amllll..... _Curren, I
CHARACTERISTIC SYMBOL ISTICS
r---I-Aac--'-'-~----~Ir=I=Aac~'='=D~~~~Y-I-'A-ac--'-'OO--~--~UNln
STATIC CHARACTERISTICS
...
CURVES
MIN. TYP. MAX. MIN. TYP. MAX. MIN. TYP, MAX.
Input Offset Voitege VIO 5 mV
' 'put Offset Current 110 14 3Il 100 260 1000 nA
Input Bias Current
Peek Output Current
Peek Output Voltage:
".
10M
".b
",b 1.3
33
2.3
70
15
3IlO
26
5. .
150
- 2500 5000
240
nA
IJA
4 'I 4' 8
10 100 1000
Positive 4.6 4.5 4.8 4.5 4.1 AMPLIFIER eiAS CURRENT IIABCI-... "
r--5-.•~-5.-95-+--~r-5~B-+5-.•-5+----+-.-.7-+-5B~r-~V
F;g.'6a-Pesk output cu"ent vs. ampli-
Amplifle, SuPPly
fier bias CU"Mt.
Current leech amplifierl IA ".b 8,5 14 85 120 850 1200 IJA
Power Consumption
leech amplifierl 0,10 0.17 1.45 10 14.5 mW
Input Offset·Yoltage -cIOOO SUPf'\.Y VOLTAGE·Vt'6V,Y---6V
Sensitivity';
Positive I!!VloIAV + 1.5 120 120 120 p,V/V
Negative 20 120 20 120 3Il 120
Amplifier Bias Voltage- V ABC 9 0.54 D... - 0.66 V
DYNAMIC CHARACTERISTICS (at 1 kHz unless specified otherwise)
Forward Transconductance
U.... signall
Common·Mode Rejection
92' 1Qa,b 0.3 1.55 I. 30 102 mmt.o
Ratio CMRR 70 110 70 110 70 90 dB
Common·Mode Input- 4.4 to -5.1 mIR. 4.3to -5 min. 4,310 -5 min.
Voltage Range 4.7 to -5.3 typo 4.610 -5,2 typo 4.6 to -5.2 typo V
S1ewRaleITeslckt.,
Fig. 13 SA 0.1 VIlA
" "
AMBIENT TEMPERATUREITA)-·C UCS-IMOI
'"
()pen-Loop (921)
Bandwidth SWOL 11 20 45 110 Fig.6b-Peak output current vs. ambient
temperature_
Input Impedance
Components:
Resistance 12 800 1500 90 170 10 20
Capacitance at 1 MHz CI 2.7 2.7 2.7 OF
Output Impedance
Components:
Resistance RO 14 200 20
Capacitance at 1 MHz Co 4.5 4.' 4.' OF
ZENER BIAS REGULATOR CHARACTERIsTICS (I' TA' 25DC.12· 0.1 mAl
MIN. TVP. MAX.
Voltage Vz 15 Temp. Coetf. '" 3 mV/OC I 6.2 I 6.7 I 7.9 V
Impedance 1 Zz 1 1 1 1200 13IlO ~:3 VOM-tNINIWUM1[t15V SUPPL YQM-ITVPICALIt;'6V tU~PL~
-14 VQM_ITYPICAL) !15V SUPPLt
Temperature-coefflclent; -2.2 mV/oC lat VABC" 0.54 [Link]· v+ IS reduced to 5 VOllS for v+
sensltlvltv
1 IJA.; ·2.1 mY/DC lal VAK .. 0.060 V, 'ABC - 10 pAl; -1.9 V' is reduc:ed to ·5 \lOllS for V- Mnsitivity 4' I 4 • a
mV/DC (at VABC = 0.68 V, 'ABC '" 100 IoIAI (bl ~ sensitivity in P.V/V = Voffsat· VoH... [Link]'~ V and -6 V supplies 10 100 1000
• Conditions for Input Offset Voltage and Supply Sensitivity: AMPLIFIER BIAS CURRENT [Link]-,..A
la. Bias current derilled hom -.he regulator with an appropriate
V· sensitivity in [Link] = Voffset - Votts.. t:~~t V and +6 V supplies
resinor connected from terminal No. 1 to the bial terminal on Fig.7-PtJak output IIOlt. vs. amplifier
the amptifier under test - bias current.
10.0001 AMIIIENT TEMPEMATURE I TA )Ol!l·C
• SUPPLY VOLTAGE y-+o6Y. Y-o_6Y
,~o
.- AMPLIFIER BIAS CURRENT ClAScl olOOJoI-A
·j.,A-f--
I: 4 ••
10 100
AMPLIFIER 81AS CURRENT UA8CI-JoI-A
... '000
f
I: SUPPLY VOLTAGE'V o6V.V-o-6V
-15 -50
V+oI5V.V-o-1 V
-25 0 25 50 75
AMBIENT TEMPERATURE ITA )--( .tCS~I"OI
100 ..
, 10
4.
100
a
AMPLIFIER BIAS CURRENT IIABC1-,.,A gaCS-I'6I7
1000
488
FiI/-Bb-AmpJlfIBt' Wpp/y curreflt leach Fig.9-Amplifier bias voltage lIS. ampli·
[Link]-Amplifier supply currsnt (tNlCh fler billS current
IImp/iffer} lIS. ambient tempera-
lImp/ifief') K lImp/ifier bi", cur-
rent.
ture.
_________________________________________________________________ 133
CA3060, CA3060A Types
921 = AOl/Rl
8 SUPPLY VOLTAGE Y+.6Y, Y-.-6Y
4 Y.'15Y,V-'15Y
FREQUENY III· 1kHz = 100/18 kG
i '·~-r--r-rrr--r--t-~+--+--+-t1H ~ 5.5 mmho
~100/' (R L :: 20 kG in parallel with 200 kG
~
! L.·'.I" L' !',-:'" '" 18kll)
~
2. Selection of suitable amplifier bias current.
.,1' '.,. U·
·Ii,· r i The amplifier bias current is selected from the minimum
value curve of transconductance (Fig. lOa) to assure that
the amplifier will provide sufficient gain. For the required
g21 of 5.5 mmho an amplifier bias current IABC of 20 IlA
46' 4 6. 4 I' is suitable. .
10 100 1000
AMPLIFIER BIAS CURRENT IIA8C1-.. A
!tl!CS-".20 BIAS RE<[Link] CURRENTUZ).. A '''''' 3. Determination of Output Swing Capability.
For a loop gain of 10 the output swing is to.5 V and the
Fig. 14-Output resistance liS. amplifier bias current. Fig. 15-8ias regulator voltage V.J. bias regulator current. peak load current 25 IlA. However, the amplifier must
also supply the necessary current through the feedback
r---~------~---r------~-o.+ resistor and for RS '" 20 k!l than RF :: 200 kil if AOL ::
10_ Therefore, the feedback loading'" 0.5/200 kG '" 2.5J-1A.
The total amplifier current output requirements are,
therefore. ±27.5 p,A. Referring to the data given in Fig. Sa
we see that for an amplifier bias current of 20 J-IA the
amplifier output current is ±40 IJA. This is obviouslY
adequate and it is not necessary to change the ampl ifier
bias current IABC.
4_ Calculation of bias resistance.
For minimum supply current drain theampHfier bias current
IABC should be fed directly from the supplies and not
from the bias regulator. The value of the resistor RABC
may be directly calculated using Ohm's law_
t-----------~ ~2 R _ VSUP • VABC
ABC - IABC
0,
COMPLETE OTA CIRCUIT :: 568.5 k!l or =:! 560 kG
Fig. 16 - Complete schematic diagram showing one of the three operational transconductance amplifiers. 5, Calculation of offset adjustment circuit.
OPERATING CONSIDERATIONS In order to reduce the loading effect of the offset
&djustment circuit on the power supply, the offset control
The CA3060 consists of three operational amplifiers similar In addition, the high output impedance makes these
should be arranged to provide the necessary offset
in form and application to conventional operational ampli- amplifiers ideal for applications where current summing is
current_ The source resistance of the non-inverting input is
fiers but sufficiently different from the standard operational involved.
made equal to the source resistance of the inverting input.
amplifier lop-amp) to justify some explanati~n of their
The design of a typical operational amplifier circuit (See Fig_
characteristics. The amplifiers incorporated in the CA3060 i.e. 20 x 200 x 106 ohms =: 18 kn
17) would proceed as follows:
are best described by the term Operational Transconductance 220 x 103
Amplifier (OTA). The characteristics of an ideal OTA are
similar to those of an ideal op-amp except that the aT A has Because the maximum offset voltage is 5 mV and an
an extremely hlgh output irr.;:-edance. Because of this additional increment due to the offset current (Fig. 4)
inherent characteristic the output signal is best defined in flowing through the source resistance
terms of current which is proportional to the difference
between the voltages of the two input terminals. Thus, the I i_e. 200 x 10-9 x 18 x 103 [Link].
transfer characteristic is best described in terms of transcon- the Offset Voltage Range '" 5 mV + 3.6 mV '" ±8.6 mV
ductance rather than voltage gain. Other than the difference
given above, the characteristics tabulated on pages 3 and 4 of The current necessary to provide this offset is
this data bulletin are similar to those of any typical op-amp.
8.6 x 1~~3 or 0.48 ~A
The OTA circuitry incorporated in the CA3060 (See Fig_ 16) lBx 1U'"
provides the equipment designer with a wider variety of
With a supply voltage of ±6 V. this current can be provided
circuit arrangements than does the standard op-amp; because
Fig. 17-20-dB amplifier using the CA3060. by a 10 MO resistor. However, the stability of such a resistor
as the curves in the data bulletin indicate, the user may select
is often questionable and a mora realistic value of 2.2 Mn
the optimum circuit conditions for a specific application Circuit Requirements
was used in the final circuit.
simply by varying the bias conditions of each amplifier. If Closed loop voltage gain'" to (20 dB)
low power consumption, low bias, and low offset current, or Offset voltage adjustable to zero OTHER CONSIDERATIONS
high input impedance are primary design requirements, then Current drain as low as possible Capacitance Effects
low current operating conditions may be selected. On the Supply voltage '" ±6 V
The CA3060 is designed to operate at such low power levels
other hand, if operation into a moderate load impedance is Maximum input voltage '" ±50 mV
that high impedance circuits must be employed. In designing
the primary consideration, then higher levels of bias may be Input resistance '" 20 kG
such circuits, particularly feedback amplifiers, stray circuit
used. Load resistance = 20 kSl
.:apacitance must always be considered because of its adverse
Device: CA3060
effect on frequency response and stability. For example a
Bias Considerations for Op-Amp Applications Calculation 10-kO load with a stray capacitance of 15 pF has a time
1. Required transconductance 921- constant of 1 MHz. Fig. 18 illustrates how a 10-kO 15-pF
The operational transconductance amplifiers allow the circuit
designer to select and control the operating conditions of the Assume that the open loop gain AOL must be at least ten load modifies the frequency characteristic.
times the closed loop gain. Therefore, the forward
circuit merely by the adjustment of the input bias current
transconductance required is given by
IABC. This enables the designer to have complete control
over transconductance, peak output current and total power
consumption independent of supply voltage.
______________________________________________________________ 1~
CA3060, CA3060A Types
output waveform with the multiplier adjusted. The voltage
CA3060 waveform in Fig. 27a shows suppressed carrier modulation of
1-kHz carrier with a triangular wave.
2.
2.
210: STROBE
2.
2.
2.
ST=~?n:~:v STROBF,
RESISTANCE VALUES ARE IN OHMS
Fig.23- Thf'fJfrchannel multiplexer.
Flg.25-Four-quadrant multiplier using the CA3060.
Fig.24- Two·quadrant multiplier circuit using the CA3060
THREE CHANNEL MULTIPLEXER Figures 27b and 27c, respectively, show the squaring of a
with associated waveforms.
triangular wave and a sine wave. Notice that in both cases the
Fig. 23 shows a schematic of a three channel multiplexer
outputs are always positive and return to zero after each •
using a single CA3060 and a 3N138 MOS/FET as a buffer
cycle.
and power amplifier. Four·Quadrant Multiplier
When the CA3060 is connected as a high·input impedance
The CA3060 is also useful as a four-quadrant multiplier. A
voltage follower, and strobe "ON," each amplifier is
block diagram of such a multiplier. utilizing Amplifier Nos.
activated and the output swings to the level of the input of
1. 2. and 3. is shown in Fig. 25 and a typical circuit is shown
that amplifier. The cascade arrangement of each CA3060
in Fig. 26. The multiplier consists of a single CA3060 and. as
amplifier with the MOS/FET provides an open loop voltage
in the two·quadrant multiplier, exhibits no level shift
gain in excess of 100 dB, thus assuring excellent accuracy in
the voltage follower mode with 100% feedback. between input and output. In Fig. 25. Amplifier No.1 is
connected as an inverting amplifier for the X-input signal.
Operation at ±6 volts IS also possible with several minor
The output current of Amplifier No. 1 is calculated as
changes. First, the resistance in series with amplifier bias
follows:
current (I ABCI terminal of each amplifier should be
decreased to maintain 100 ~A of strobe-"ON" current at IEq.31
this lower supply voltage. Second, the drain resistance for the
MOS/FET should be decreased to maintain the same value of Ampi. No.2 is a non-inverting amplifier so that
source current. The low cost dual-gate protected MOS/F ET,
RCA·40841, may be used when operating at the low supply IEq.41
ALL RESISTANCE
VALUES ARE IN
voltage. O~MS
Because the amplifier output impedances are high, the load
The phase compensation network consists of a single 3900
current is the sum of the two output currents, for an output
resistor and a l000-pF capacitor, located at the interface of -=- 270
voltage
the CA3060 output and the MOS/FET gate. The bandwidth Fin. 26- Tvoical four-Quadrant multiplier circuit.
of the system is 1.5 MHz and the slew rate is 0.3 volts/J,[Link]. VO=VXRL[921121·921111! IEq.51
The system slew rate is directly proportional to the value of The transconductance is approximately proportional to the
the phase compensation capacitor. Thus, with higher gain amplifier bias current; therefore, by varying the bias current
settings where lower values of phase compensation capacitors the g21 is also controlled. Amplifier No. 2 bias current is
are possible, the slew rate is proportionally increased. proportional to the Y-input signal and is expressed as
NON LINEAR APPLICATIONS IV-I + Vy ~'
AM Modulator (Two·Quadrant Multiplier)
Fig. 24 shows Amplifier NO.3 of the CA3060 used in an AM
IABCI21 ~ --R-1-- IEq.61
,-
modulator or 2·quadrant multiplier circuit. When modulation Hence,
is applied to the amplifier bias input, Terminal B, and the
921 121 ~ k IIV·I + Vy I. IEq.71
carrier frequency to the differential input, Terminal A, the
waveform, shown in Fig. 24. is obtained. Fig. 24 is a result of Bias for Amplifier No. 1 is derived from the output of
adjusting the input offset control to balance the circuit SO Amplifier No.3 which is connected as a unity"gain inverting
that no modulation can occur at the output without a carrier amplifier. IABC(1), therefore, varies inversely with Vy.
b.
input. The linearity of the modulator is indicated by the And by the same reasoning as above
solid trace of the superimposed modulating frequency. The -- , T ~ (1 , "
maximum 'depth of modulation is determined by the ratio of
the peak input modulating voltage to V-:
921111 ~ k [IV-I- Vy!.
Combining equation 5, 7, and 8 yields:
IEq.81
. L.L::. ~ V\\i~ 1/ I)
The two-quadrant multiplier characteristic of this modulator
is easily seen if modulation and carrier are reversed as shown
in Fig. 24. The polarity of the output must follow that of the Vo~Vx· k - RL IIIV.I + Vyl [IV~I Vyl! or
differential input; therefore, the output is positive only Fig.27-Voltage waveforms of four-quadrant multiplier
VO~2k RL VXVy
during, the positive half cycle of the modulation and negative circuit.
only in the second half cycle. Note, that both the input and Fig. 26 shows the actual circuit including all the adjustments
output signals are referenced to ground. The output signal is associated with differential input and an adjustment for
zero when either the differential input or IABC are zero. equalizing the gains of Amplifiers No. 1 and No.2.
Adjustment of the circuit is Quite simple. With both the X
and Y voltages at zero, connect Terminal 10 to Terminal 8.
This procedure disables Amplifier No. 2 and permits
adjusting the offset voltage of Amplifier No.1 to zero. by
means of the 100-kS2 potentiometer. Next, remove the short
between Terminals 10 and 8 and connect Terminal 15 to
Terminal 8. This step disables Amplifier No.1 and permits
Amplifier No.2 to be zeroed with the other potentiometer.
With AC signals on both the X and Y input, R3 and Rl1 are
adjusted for symmetrical output signals. Fig. 27 shows the
__________________________________________________________________ 137
CA3075
ELECTRICAL CHARACTERISTICS at TA = 25°C
LIMITS TEST
CHARACTERISTIC SYMBOL TEST CONDITIONS UNITS CIRCUIT
MIN. TYP. MAX. FIG. NO.
Static Cbaracteristics
DC Voltage:
At Termonall VI - 6.1 - V
At TerminalB V" 11.2 V - 5.4 - V 6
VB
At Terminal 12 V12 - 5.2 - V
DC Currenl (into TerminalS):
AtV·,B.5V B.5 IS - rnA
At V·, 11.2 V 15 - - 11.5 - rnA 6
At V', 12.5 V - 19 29 rnA
Dynomlc Cbaroc,.,;sf;cs at y+ = J J.2
~ 10' 10.1 MHz
Input Limiling Vollage VI(lim) f(Modulalion),400Hz - 250 600 p.V 3
(knee. - 3dB point) Deviation' ±IS kHz
fO , 10.1 MHz
f(Modulatioo)·400Hz
AM Rejection AMR
FM: Oeviation • ±15 kHz - 55 - dB 5
AM: Modulatioo ·30% [Link]"IOO ..VRIlS [Link]·ZYRIlS
[Link]"OYo 2. RUO DISTORTION I... '.
Input Impedance Componenls:
Parallel Resistance
Parallel Capacilance
RI
CI
fO·IO./MHz
VIN • IOmV RMS
- -
-
4.5
4.5
-
-
kO
pF
-
[Link]/V,
Fig.4 - Tnt circuit for audio preamplifier voltaga gain
and total harmonic distortion
DETECTOR
~F Vollage (al fO • 10.1 MHz
Terminal 12) VO(Af) I(Modulalion). 400Hz - 1.5 - V 3
Total Harmonic Distortion THO Oeviation • ± 15kHz - I 2 %
AUDIO PREAMPLIFIER
Voltage Gain A(Af) VIN • 100mV. fO' 400Hz - 21 - dB 4
Total Harmonic Dislortion THO Vour' [Link] • 400Hz - 1.5 5 % 4
Li-
Z. ~T I • IIU lI'h.~, • \M ..~.
ICMODULIoTIOMI.4!»H •. UDEy,ATIOO·!7BH,
).TUNEW"'YEANAL'I'l!:lIfOAPEAI(IIUDIIIGA,.ooH.
[Link] [Link]
5. QIKONHECTFIIOEHERA'QR
[Link]"TQIITOIN,UTOFCA)07S
[Link]·."t· 1OO ......
IIIIODULATlONI • .ooH,WlTNJQ'OoKlDULATI(JN
8. TUNEWAVE ....LYZEIIFDRPI!AKIIEo\l)IHCA,«MIH.
"""EJECTIClt.I'OLOGIO~
Fig.6 - Test circuit for AM rejection Fig. 6· [Link] circuit 'or static characteristics
_______________________________________________________________ 1~
CA3076
y.
Tenninol No.5 wire·connect" to the case.
Terminal. N•• 3 Clnd' which .re t ......etH to the subst,at.
should tI. [Link] to 'he "'a•• "It,.'i"o point in the circuit.
The resiltonu .. lues jftclud • .t Oft the Ich .....tic dio'r....
ha... be" supplied as a cDn"ollience '0 assist Equipment
Mon,,'ac •.,re,', in optimilinl the .[Link] of "oulboonl"
comp.n.,.'. of equip",e"t clui,"s. The "alu.s shown mo,
vary os much as .!. 31m,
RCA ,.s.,.,e. to
'he rith. m.~. an, chon,a. in the Rui .1-
ance Volues provided such chantal clo not ad".,.el,. affect
.he publish.d [Link] [Link] of .he cI • .,ice.
,
y-
Fig. 4 ·Scbemot;c J/agram 01 CA3076.
MURUAFILTfA
TYPICAlYALUES
IIIN' RouT ·l30n
INSERTIQH LOSS' '~B TYP.
BANOWIOTH(AT_)dl),ZlOkH.
(lUTI'UTYOLTAGE:
I. SET ATTIEMUATOR TO a.1
Z.S!T Rf'GI!!MEftATOR TO 10,.., cw
l.t!AOVOIN.,V
OUTPUT MOISE VOLTAGE·
I. SET ATTENUATOfII T06U8
1. IIfAO Vo 1M."
Fig. 5 ·10.7 MHz voltage ,Gin GnJ noise test circuit
________________________________ ~ _____________________________ 141
CA3078, CA3078A Types
SUPPLY YOLTS V+o+6,Y-0_6
AMBIENT TEMPERATURE ITA '0 25.C H--I-+++-I
SOURCE RESISTANCE IRS' ~ 10 I<A
~
i
OJ
i
~ 2. t-+-Hrf-t-rf--+--f-t+---+-+--++1
~ I.B~~~11~C~"~0~"~T~tH:EllE
! 12
CA3078AT
0.6 I
. ,. 10 100
TOTAL QUIESCENT MICROAMPERES CIQ}
. .. '000
Fig.3 -Inpur offset voltllfl6 vs. total quiescent current.
Fig.2·Schematic diagram of the CA3078T and CA3078A T.
TypiCiI Values Intended Only 'or Design Guidance atTA" 250Cand V+ - +6 V, V- = 6V
CA3078AT CA3078T
TEST
CHARACTERISTICS SYMBOLS CONDITIONS RSET '" 5.1 M!J: RS ET " Mf! RS ET ' 1 Mf! UNITS
' 0 ' 20jJA ' 0 ' 100 jJA ' 0 ' 100 jJA
I 4.. 2 4 •• 2
10 100 1000 I000O
Input Offset VOltage Drift t.V, 01 dT H", ...... 10 Kn 5 6 6 /iV/oC TOTAL OUIESCENT MICROAMPERES tIOI
Input Offset Current Drift [ <>V'OI"TA RS ',10 K•• 63 70 70 pAloe
I upen-Loop tsandwldth aWOL JdB Ul VJ 2 < kH, Fig.4 - Input offse' cUTnmt vs. tolill quillSCllnt curr.",.
I Slew Rate:
Unltv Gain Sec Figs. 0027 0.04 0.04
SR V//iS
Comparator 20.21 05 15 1.5
10"., to 90"~
TranStent Response Rise Time 3 25 2.5 /is
Mll
I nput Resistance
Output Resistance
R
AlL
7.4
1
1.7
OS
0.S1
O.S K!!
v
Equiv. Input NOise Voltage eN(10Hll RS 0 40 - 25 nV/yH,
EqtHV. I nput NOise Current 'N I1OHz ) RS 1 M~! 02. I pA/yH,
-;tf-
ELECTRICAL CHARACTERISTICS, It T A = 2SOC
Typical Values Intended Only for Design GUidance 2 -I-... +-
a 468 2461 2 4 .. 1
j
2468
r-:- T
TYPICAL VALUES 10 100 1000 10000
CA3078Al C~ 30781 TOTAL QUIESCENT MICROAMPERES 1I01
CHARACTERISTICS Y+=.[Link], y+ '" +0.15V. V· '" +1.3V. v+ = 0.75V.
V-=-1.3V V-·-0.15V V-= -[Link] Y-"'-0.75V UNITS Flg.5 - I"pur bias current vs. total quiescent current.
SYMBOLS
RSET ' 2 Mr! RSET ·,0Mfl RSET'" 2 Mn RSET"0Mn
, 0 . , jJA
' 0 ' 10jJA IQ=1JJA ' 0 ' 10jJA
V ,n 0.1 0.9 1.3 1.5 "'v
10 V.J v.v,. 0.5 nA
J. uqo nA ~f-+--+~H--+-r+~-I-~t-H~
18 1.3
Am
.'J:l
S4
.u
65 SO
.u
GO dR
jJA
; a
D 2"
14
1.5
0.3
Lt.
14
'"
0.3
/iW
v
126r-. t+1-~-++ H-+-+~-I'"
VOpp lOB LOAD R£SISTANCE IR 1'1 MA
-O.S -0.2 -O.S -0.2 .0
~ ~ :r n:~•.: . ~
VieR '0
+1.1
to
+0.5
to
+1.1
'0
+0.5
v
CMRR 100 90 100 9D dS
--t---i--+++--if-+-+-fl"
10M! 12 05 12 0.5 mA
dVlO/dv' 20 50 20 50 J.1V:v
"o
.,.
+-H-t-+-++ft--+-H-fl
10 100
TOTAL QUI£SCENT MICROAMPERES IIQI
. .. '000
Fig.6 - Open·/oop vo/rll!lfl gain v.s. totlll quiftC6fll current.
__________________~------__------------------------------------------143
CA3078, CA3078A Types
~t
ti-t i
SUPPLY VOLTAGE: Y+-SV,V---6Y
II AMBIENT TEMPERATURE tTAI-ZS-C
: ,\i I
, • I\.. RESISTOR-CAP'ClltlR
~, J.L~..JJLL
~ Iii - 125
t
COMPENSATION
RI-CI BETWEEN
I TERMINALS 19;8) CAPACITOR
! 'f\. ~ I
COMPENSATION
(BETWEEN TERMINALS I 81
r---
~
!I
~
.
0.'
'r- 20,.A - 1----
--1-
~0.75
S 0.5
IUI'I'LYVOL".V· .... V· •
[Link]$CE~Teu""E~TlIol.,OO~ ...
MlIIENTfEM",[Link].I!IT... [Link]·C
'r--
."
LOAOIMl'EOANCE:AL·[Link]·'lIIIpF
FUDIlACKRUI$'... NlCIIRFJ·o.,.J
OUTf'UYVOLTAGEIV"",I"OV
§
j .. 4 68 10" " 4 6 er;s 2 4' I 2 4 (; 'If?
~
e
'i-
, 4 68 10 , ... , 4 68 10 , I
t
46811i'
o 00 ~ ~
:~S~:M~~~ :':A~~':':~
ONA1OOmVDUTl'[Link]
IA,. C, ~ 2.5 .,0ill
~ 60
CI..OSED-LOOP NON-INY!:ftTtNG VOLTAGE OAIN- ""
ro ~
'0
FREQU£NCV (')-HJ; 92C5-2026' FREQOENC'I' (fl-HI
Fig.,9 - EquiWllent input noi,e cumlnt VI. ftwqUtmcy. Fig.20 - Slew rate ~_ closed-loop gain
Fig. IS - Equiwtlenr input noile voltage vs. freqlAncy.
lor 10 = '00 jJA - CA3078T.
...• M
lOA
3i
~=~ITOR (R,-C. BETWEEN CAPACITOR
.... TERMINALS 1&8) COMPENSATION
(BETWEEN TERMINALS Ie 8)
~ 03
SUNIL'I'VOlTS,y·· ... V-··. ...
~ QUIUClNT ctJRR~NJ IIQI-
_ENTTEMnRATUREfT,t,I_Zfj"c
ao~
iii Q2 [Link]",IIP£IIIWC£:RL-l01CItCL-'eo ••
fU"'CIt~UIS"'MCt:IR,I-all11il
OUlPUTVOLTAGE!YOfPI-'1V
0.'
:sE~~:~::~~~~
(A,. C, .. ~.II1"1
• 00 ~ ~ ~ ~ • ~ ~
CI..[Link]" NON-INVERTING VOLTAGE GA~ dB RI IOPTIONAL
06 liJ 29:7 40 50 80 76 86 RZ-CZ ICOMP.
CLOSEQ-LOOP IN\'ERnNG VOLTAGE GAIN- dB
921=5-17554111
Fig.27 - Si8w [Link] w. clos«J./oop gain Fig.22 - Transient response and slew·rate, Fig.23 - Slew, rate, unity gain (non-jnYfH"ting} test circuit.
fDr IQ .. 20 pA - CA3078A T. unity gain (inverting) test circuit.
Table I - Unity-glln sa.w nit. VI. compHUtion - CA3078T and CA3018AT
SUPPL V VOLTS: V+ - 6. V' =- .. TRANSIENT RESPONSE: 10% OVERSHOOT FOR AN OUTPUT
VOLTAGE of 100mV
OUTPUT VOLTAGE IV O) - ±6V AMBIENT TEMPERATURE ITAI - ftOc
LOAD RESISTANCE IRLI • 10 kG
~
i
/ '-
I: ~~~fg~TOR
COMPENSATION
TECHNIQUE ., UNITV GAIN !INVERTING. Fig. 22
Cl .2 C2
SLEW
RATE
.,
UNITY GAIN (NON-INVERTINGI Fig. 23
Cl .2 C2
SLEW
RATE
i
I 4 (RI-C, BETWEEN
TERMINALS I a 8)
'\.1 II I
CA3Il78T-I Q =1001JA
Single Capacitor
kG
0
.F
750
kG
~
/6'
0
VIP.
0.0085
kG
0
.F
1500
kG
~
/6'
0
VIP.
0.0096
I 'l\. I I I I Resistor & Capacitor 3.5 350 ~
0 0.04 5.3 500 ~
0 0024
20 '0 40 50 60 70 80 90 Input 0.306 0.87 n 0.311 0.45 0.67
~
0 0.25 ~
CLOSED-LOOP NONINVERTING VOLTAGE GAIN - dB CA3078AT - 10 .. 20 pA
06 ~ ~ ~ ~ ~ • 00 m Single Capacitor 0 300 ~
0 0.0095 0 800 ~
0 0.003
CLOSED-lOOP INVERTING VOLTAGE - dB
Resistor &: Capac:itor I. 100 ~
0 0.027 34 125 ~
0 0.02
Input ~ 0 0.644 0.156 0.29 ~
0 0.77 0.' 0.'
F;g.24 - Phase compensation capacitance
I'$. closed-loop gain - CA3078T.
".0
[Link]
510kG ~AA"CELL
::;}-®------+,
"
.'
o moo. ~ .00. .
CLOSED-LOOP MOHINVERTING VOLTAGE GAIN'- dB
~
191 29.7 40 50 60 70 90
CLOSED-LOOP INVERTING VOLTAGE - dB
Fig.25 - Phase compensation capacitancs Fig.27 - Inverting 2O-rJB amplilisr circuit. Fi9.28 - Non-inverting 2O-dB amplifier circuit.
VI. closed-loop fIlIin - CA3078A T.
----------------------___________________________________________ 1~
CA3080, CA3080A Types
ELECTRICAL CHARACTERISTICS TYPICAL CHARACTERISTICS CURVES AND
For Equipment Dasign
TEST CIRCUITS (Cont'dl
TEST CONDITIONS CA3080
..
10: SUPPLY VOLTS:V+'+15.V-=-15
v+= 15V. V --15V CA3080E
CA3080S
IABC=500IJA
CHARACTERISTIC LIMITS UNITS -;. lOll
~
TA a 250 C ~
(unless indicated II! •
otherwisel Min. Typ. Max.
I nput Offset Voltage VIO
- 0.4 5
mV
TA = Oto 700c - - 6
Input Offset Current 110 - 0.12 0.6 p.A
-,,-,
i
- 2 5
.:
I
Input Bias Current II p.A
TA=Ot0700C - - 7
0.1
Forward Transconductance 6700 9600 13000 2 .. II "'1
gm IJmho
Oarge signall TA = Oto 700C 5400 - - 0.1 I 10
AMPLIFIER 81AS ,.ICROA"PERES (.IABCI
100 1000
'2CS·1711~
RL = 0 350 500 650
Peak Output Current 110M I RL = O. TA = 0 to 70 0C 300
IJA Fig.5 - Input bias current as a function of
amplifier bias curren t.
Peak Output Voltage:
Positive V+OM
RL =~
12 13.5 - IO~
V _ SUPPLY VOLTS:V+·+I',Y-.-15
Negative V OM -12 -14.4 -
Amplifier Supply Current IA 0.8 1 1.2 mA
Device Dissipation Po 24 30 36 mW
Input Offset Voltage Sensitivity:
Positive ;"VI O/;"V+ - - 150
IJV/V
Negative ;"VI O/;"V - - 150
Common·Mode Rejection Ratio CMRR 80 110 - dB
Common·Mode Input·Voltage 12 to 13.6 to
Range
VICR
-12 -14.6
- V
Input Resistance RI 10 26 - kU
2 "'1 .. I I
I 10 100 1000
CA3080 AMPLIFIER BIAS MICROAMPERES I IAliel
ELECTRICAL CHARACTERISTICS CA3080E ueS·,7l1,.
Typical Values Intended Only for Dasign Guidance CA3080S Fig.6 - Peak output current as a function of
amplifier bias current.
I nput Offset Voltage VIO IABC= 511A 0.3 mV
IABC = 500IJA to SUPPLY VOLTS: Y--+15, Y-·-15 I
Input Offset Voltage Change I;"Vlol IABC = 5IJA 0.2 mV _14.5 ~;E:;s~;~=:~!~~.E~rA )"2S·C H-tt--t-Htl
Peak Output Current 10M IABe = 511A 5 IJA ~~14'r:l=~!t~t:~~::~~~~V~~~M'~~
!;;,a.5~ V"'OAI
Peak Out'put Voltage:
Positive V+OM 13.8
> i 1!iJ-+-+++f-+-+-f+l-f-H-f+--1-H-H
Negative V OM
IABC=5I1A
-14.5
V ~~ °r-t-rttr-r-r~r-r-rttr-r-rtH
Magnitude of Leakage Current
IABC - O. VTP = 0 0.08
nA ~ ~'::f-+-+i-f+-+-++I+-++++f-+-+-!+I
~ t':~=!=!~~+::t::t:~~:~~:~::~~v.~o.~;~~
IABC = 0, VTP = 36 V 0.3
Differential I nput Current IABC = 0, VOIFF - 4 V 0.008 nA
.V-CMR
Amplifier Bias Voltage VABC 0.71 V
I 2 4 'I 2 4 I' 2 4 III
Slew Rate: 0.1 I 10 100 1000
AMPLIFIER BIAS MICROAMPERES (lABC'
Maximum (uncompensated I 75 92CS-17592
SR V/IJs Fig.7 - Peak output voltage as a function of
Unity Gain (compensatedl 50
amplifier bias current.
Open· Loop Bandwidth BWOL 2 MHz
Input Capacitance CI f= 1 MHz 3.6 pF 10: SUPPlY YOLTS: "'+.+15,"'- __ 15 +W
Output Capacitance Co f= 1 MHz 5.6 pF
Output Resistance RO 15 MU
Input·to·Output Capacitance CI-O f = 1 MHz 0.024 pF
461 4.1
0.1 I 10 100 1000
AMPLIFIER BIAS MICROAMPERES (:IA8)~CS_I7!i9l
Fig.S - Amplifier supply current as a function of
amplifier bias current.
______________________________________________________________________ 147
CA3080, CA3080A Types
TYPICAL CHARACTERISTICS CURVES AND TEST CIRCUITS (Cont'dl
SUPPLY VOLTS; II ·.'5,V-'-15
SUPPLY YOLTS:V+.+I!5,V --15
AMBIENT TEMPERATURE (TA'=25°C
/
..
d
~ :~
100
10
/ !:
; I
..,
2
~
0.1
0.01
I 2 3 4 ... , .. 61 2 .. SI .. 61
INPUT DtFf'EREHTIAL IIOLTS 0.1 I 10 100 1000 0.1 I 10 100 1000
92CS-ln•• AMPLIFIER BIA!; MICROAMPERES ! IAeC~2CS_17'99 AMPLIFIER 81AS MICROAMPERES (:rABe'
92CS-17100
Fig. 13 -Inputcurrentasa function of Fig. 14 - Transconductance as a function of Fig. 15 -Input resistance as a function of
input differential voltage. amplifier bias current. amplifier bias current.
=~TVl?hT,:,;:;~;:t:Y;~;--~!5ec ~
SUPPLY VOLTS:V ••• 'S, '1-'-15 7 SUPPLY VOLTS: ,,+,+15,""'-15
~'~.-.-rnr-r-'-nT--~+i~~--rt~
AMIIENT f'tMPERATURE ITA" 25'C ":Sk:-
FREQUENCY ttl' 1111Hz
~;~~~~~~~~~~~~~~~~
U
l800'~+-~~~t-+d~~~~~~==~~
T
~ roo'~+-~FRr-+-+-Hi~~+i~~--~~
v
~
~~'I--+-~rH~~~H1~I--t11t-1--I-t~
~
;~O,~:~--:~=~~~=~=~:~~=~~~~~~~:~::~~~
ii 400r -
~ 10',
~
i I(jll
.
~ 300'~~~~F-+-+-Hi--~+i~~--rt~ ~
! ~'I-~-+-1-+H--+-+-H+--+-+11+-+-~+H §
10
,1!I-!IIII!I"!!lII'I'IIII--!-I1il
...
loo~+-+t-tlr-+-+-Hi--~+i~-+--rt~
I
2 .. , . 2 4 '8 2" sa 2 • ,. 11 .. IS. I .. al 2 .. I I
0.1 I 10 100 1000 0.1 I 0 KlO 1000 I 10 00 1000
AMPUFrER [Link] MICROAMF'ERES I IA8C~2CS_I7IOI AMPliFIER elAS MICROAMPERES (IAeel AMPLIFIER 81AS MICROAMPEIIES (:lAScl
Fig. 16 - Amplifier bias voltage as a function of Fig. 17 -Input and output capacitance asa Fig. 18 - Output resistance as a function of
amplifier bias current. function of amplifier bias current amplifier bias current.
AMBIENT TEMPERATURE (TA'-Z50C
v· ... FREQUENCY(f'-IMH,
~M6
::;
; ODS
60D4
§
10 "
SUPPLY [Link]-tV~Y-1
Fig. 19 - Input-to--output capacitance test circuit. Fig.20 - Input-fa-output capacitance as a
function of supply voltage.
v+.t5v APPLICATIONS V+"15V,V~=-15V
LOAD
(SCOPE PROBE I
$In
.OOI~F nC5-24034
Fig.21 - Schematic diagram of the CA3080 and CA3080A in a unityllain voltage follower
configuration and associated waveform.
___________________________________________________________________ 149
CA3080, CA3080A Types
ALL. RESISTORS 1/2 WATT
UNLESS OTHERWISE SPECIFIED
TOP TRACE; OUTPUT
(SO mY/DIY. AND 200ns/DIY.)
BOTTON TRACE·· INPUT
150 mY/DIY. AND 200 ns/OIY.)
92CS-226!9R!
92C5-27883
Fig.28 - Input and output response for Fig.29 - Thermocouple temperature control with CA3D79 zero voltage switch as
circuit shown in Fig. 25. the output amplifier.
+7.5
.,
INPUT 2 K
SAMPL.E O Y l r . - .
STROBE 15 K
HOL.D -7,5
Fig.3D - Schematic diagram of the CA3080A in a sample-
hold circuit with SiMas output amplifier.
TOP TRACE: OUTPUT-5y/01". a 2jA-S/D1V. TOP TRACE: OUTPUT-2DmV/OIV. a IOOns/DIY.
BOTTOM TRACE: INPUT-200 mY/OIV. a lOOns/DIY.
CENTER TRACE: 01 FFERENTIAL. COMPARISON OF
INPUT a OUTPUT-2 mY/OIV. a 2 fu/OIY.
BOTTOM TRACE: INPUT-5 VIOl". a 2 fu/DIV.
Fig.31 - Large-signal response for circuit shown Fig.32 - Small-signal response for circuit shown
in Fig. 30. in Fig. 30.
______________________________________________________________________ 151
CA3081, CA3082 Types
ELECTRICAL CHARACTERISTICS at TA - 25°C
For Equipment Design
TEST CONDITIONS LIMITS
Typ_
CHARACTERISTIC SYMBOL Char. UNITS
~
Fig. No. Min. Typ. Max.
Collector-to-Base Breakdown Voltage VIBR)CES IC - 500 [Link], IE - 0 - 20 60 - V
Collector-ta-Substrate Breakdown Voltage VIBR)CIO ICI - 500 [Link], IE - 0, IB - 0 - 20 60 - V
Collector-ta-Emitter Breakdown Voltage V BR CEO IC - 1 mA, IB - 0 - 16 24 - V
Emitter-to-Base Breakdown Voltage VIBRIEBO [Link] - 5 6,9 - V
DC Forward·Current Transfer Ratio hFE
VeE -0.5 V,le"" 30 rnA - 30 68 -
VCE - 0,8 V,IC- SOmA - 40 70 -
Base-ta-Emitter Saturation Voltage Vse sat Ie - 30 mAo 18 - 1 mA 3 - 0,87 1.0 V
Collector-ta-Emitter Saturation Voltage:
CA3081, CA3082
VeE sat
I[Link] 30 rnA, fa:: 1 rnA - - 0,27 0,5
V
CA3081 IC - 50 mA, 18 - 5 mA 4 - 0,4 0,7
CA3082 Ic' SO mA, IB - 5 mA 4 - 0,4 0,8
Collector·Cutoff·Current ICEO VCE -10 V, IS - ° - - - 10 ~A
Collector-Cutoff Current ICBO VCB -10V,IE-O - - - 1 ~A
TYPICAL READ-OUT DRIVER APPLICATIONS
~
'~SE'.,",'"
INCANDESCENT DISPLAY
III:CA-0II:2000 SERIES
OR EQUIVALENT I
FAOM 1/7 CA30al
DECODER' {COMMON [MIT TEA)
-THE R£SISTANCE FOR II: IS DETERMINED BY THE RELATIONSHIP
11:. Vp-:a~l-E\/~:LEDI WHERE: VP'~~~~~LSE
92C5-ITM]
R-O FOR Vp~VaEtVFILEOI VF'~8r:BJ~'\'EE
FIg.6-Schematic diBfTsm showing one tranlistor of Fig.7-SchemBtic dillfTBm showing one trIIfJIistor of
the CA308' driving one regment of an incMJ· the CA3082 drllllnq s Hght-emltting diode
descent disploy, (LED),
____________________________________________________________
~
-
-
-
1
5
3
CA3083
I. SET DC fORWARO-CURRENT TAAr4SfE!'r !'rATIO (lifE" 10 I SET DC fORWARO-CURRENT TRANSfER RATIO (IIfEI • to'
:=T~[Link] (_"+"..,"'_"_'_+--_+*--+..,
i AMBIENT TEMPERATURE (TAl' 25°C -r--r-+-+-l
I
c------ r--- / ! 0.9-- -_._----
0_8r-----'-- - ----"--
I--- -" -" - f-"" II Z 0"'f--f---t---+-+-+::::7"4V
--t-t-t--1
06f------ --- -
O"'f--t--+ -+-+-+-V--7'/'+-/Tt--t-+-1
/
/
J i~
~
O"'I---+::;....!l~"'··r'~=--Ic-:++"::;;>-4/'--I--+-+-I
-- r---
t1PIC/loL
*
'0 '0
COLLECtOR MILLIAMPERES !Ie I COLLECTOR MILLIAMPERES !ICI
Fig.6- VSEsatvslc
TYPICAL STATIC CHARACTERISTICS FOR DIFFERENTIAL AMPLIFIER
i : i~~;:~T O~E~~~!:;~~~R ,;~~~~~~~E )-3 V
I
~
.. ,
COLLECTOR NILLIAMPERES (ICI
, • 10 ,
COLLECTOR MILLIAMPERESlIc) 92C5-17169
Fig.7 - V 10 vs Ie (transistors at and 02 as a d;fferential F;g.8-l lo VI Ie (trans;stors at and Q28$ a differential
ampii/;tH). amplifier).
______________________________________________________________________ 155
CA3084
ELECTRICAL CHARACTERISTICS at T A' 26"c STATIC CHARACTERISTICS FOR EACH TRANSISTOR
For Equipment DesIgn
TEST CONDITIONS
Typ.
Charac- LIMITS
CHARACTERISTICS SYMBOL UNITS
mis'ics
~ Min. Typ. Ma)f.
Fig. No.
For Each Transistor:
Coliector·Cutoff Current IcaO Vca'" -lOV,I E :: 0 -0.055 -100 nA
Collector-Cutoff Current ICEO Vce - -10V,'B- 0 -0.12 -100 nA
CoUector·to·Emitter Breakdown Voltage VIBRICEO ICE = -l00jAA, IS = 0 -40 -10 V
Collector·to-Base Breakdown Voltage VISRICBO ICB = -l00jAA, IE = 0 -40 -80 V
Emitter-to-Base Breakdown Voltage IES=-l()()pA,IC- O -40 -100 V
o ° .. 68 t .. 68 I 2 .. 6810
VIBRIESO 0.001 0.01 0.1
EMITTER MILLIAMPERES IIEI
Emitter-to-Substrate Breakdown Voltage VISRIEIO IEI - l00j<A 40 100 V
Fig..7-h FE VS'E"
Collector-to-Emitter Saturation Voltage VCEsat Ie = lmA, '8 - la~A -0.125 -0.25 V
Base-to-Emitter Voltage VSE -0.50 -0.59 -0.68 V STATIC CHARACTERISTICS FOR DIFFERENTIAL AMPLIFIER
IE = l00jAA, VeE = -10V
DC Forward-Current Transfer Ratio hFE 15 40
COLLECTOR-TO'EMITTER VOLTS (VCEI~-IOV
For Transistors 01 and 02 (Asa Differential Amplifier): AMBIENT TEMPERATURE ITA'"2'·C
~:~~~--~~~--+--+-+++--+--+-+-H
Magnitude of Input Offset Voltage I Viol IE = l1JOJ.1A. VeE = -lOV 0.422 6 mV
Input Offset Current 110 -0.6 0.6 ~A
For Transistors 03 and Q4 (Current·Mirror Configuration):
\++I---I---+--++I--+---+-t--H
~ osl-f>r-+
Collector Current (Normalizedl lelI5 VCE = -5V, VCIO = -5V, 10 0.85 1.00 1.15
~ O"f--+--TI\+t-+--+--t-+-t+---t-H-ti
~~I--+--+-~r--r-+-+-t+---t--+-rH
Magnitude of Collector Current Ratio Term. 13'" Gnd. 11 0.90 1.00 1.10
IleI031f1c10411
IS'" -l00IAA, ,l
I=or Transistors 05 and 06 (Darlington Configuration):
~MI---r--~-+t~~t--t-+tt--t--t-t-H
Collector·Cutoff Current
Base-ta-Emitter Voltage
ICEO
V8E
VCE '" -10V, 18 '" 0
IE = l()()pA, VCE = -10V
13 0.92 1.01
-1.0
1.20
~A
V 10
r---..
100
. ..
COLLECTOR MICROAMPERES (lci
...
9:lCS-11Sll
1000
DC Forward·Current Transfer Ratio hFE 15 100 1230
Ftg.8-VIO VI Ie. (transistors al and
02 as a differential amplifier~.
ELECTRICAL CHARACTERISTICS at T A· 26·C
Typicll [Link] Only For Design Guidance VCE " 10V
Magnitude of Temperature Coefficil!!nt:
VSE (for each trwIsistorl I"'VBE''''T I IE = l00jAA, 6 -1.18 mVf'C
V10 (as a differential amplifier) I"'Vlo''''TI VCE = -10V 9 0.54 Ilvf'c
VSE IDar1ington configuration) I"'VsE''''TI 14 -3.1 mvf'e
For Each Transistor:
Input Resistance RI f'" 1kHz, VeE'" -10V, 19 9 kG
Output Resistance RO Ie =-l00j<A 20 - 600 - kG
Forward Transconductance 11m -
22 - 3 - mmho
...
_80_
Coliector·to·B_ Capacitance
Coliector·tg·Emltt. Capacitance
Copoci......
GeSO
,GeEO
ltalo
lea'" 0
ICE" 0
ICIO' 0
....
i
I
23
23
23
-
-
-
3.3
2.5
4.6
-
-
-
pF
pF
pF
-7' -50 -25
Fig.9-VIO YS
215 '0 75 100
AMBIENT TEMPERATURE ITA}-"C
TA (transistors 01 and
02 as a differential amplifier~.
1215
9,CS-I7I8S
STATIC CHARACTERISTICS FOR CURRENT-MIRROR CONFIGURATION
AT TA"Z~·C AND 't:E~-IOV"
I5' 3 """,II2-3.I'J£A
IS ·IO,.A, 112,"1O.5J£A
a
~
.
.". COLLECTOR-TO- EMITTER VOLTS IVCEI • -IOV
AMBIENT TEMPERATURE ITAI,. 25·C
10
AMBIENT TE. .ERATURE (TA'- 25"C
~~
1,,"IOO,.A. I I2-IOO ,.A
} "h"I<"'r-.-,--,-n-,-------,,,-r-r-rrf-t----t--1
~ [Link]-H+-+~+++!!J·A~."-. l+H--+-1+++-+--i
~
i
I
cou."roR-TO-E.'TTER
-'0,\
"7
-!OV
~
S ~i 0.1
,HtH!
iG 0,91-H+--+"...I--I++.!!.!!!+f++-+--+++-f--H
~
~
",
~
~ 0.01
~~
'e' 1 \'OV
-, V
. .... . ..
0.8
- _ _ ° "
0.'
~ n ~ ~ , ... 2 ....
I
2
0.01 '0.1 2 .. I II :2. .. 68 10
10 I 0.1 0.01 0.001 0.001
AMB'ENT TEMPERATURE ITAI........C '210:1-17186 CURRENT AT TERMINAL 5 {I,I- iliA S2CS'IT.n ~RENT AT TERMINAL 5 (lei-iliA
Fig.l0-Normalized Ie vs TA (transi..
.,n Q3 and 04 in a current·
SOr configuration.
Fig.l1-le ratio V5 15 (transistors Q3
and Q4 in a current·mirror con·
figuration.
Fig. 12 -Ie VB 15 (transistors 03 and Q4 in a
current·mirror configuration).
_____________________________________________________________________ 157
CA3085, CA3085A, CA3085B Types
Positive Voltage Regulators TV ..
VIN
Range
VOUT
Range
MalC
lOUT
Max. Load
Regulation
COMPfHUTIQHAHD
EXTfRNALIHH1IIT
For Regulated Voltages from 1.7V to 46V V V mA %VOUT
at Currents up to l00mA CA3085 7.51030 1.8t026 12' 0.1
CA3085A 75t040 1.7t036 100 0.15
R CA·CA3085. CA3085A, and CA3085B are silicon
CA3085B 7.5t050 1.7t046 100 0.15
monolithic integrated circuits designed specifically for service
as voltage regulators at output voltages ranging from 1.7 to • Thl' value may be elttended to l00mA; however,
regulation IS not specified beyond 12mA.
46 volts at currents up to 100 milliamperes.
These types are supplied in the B-Iead TO-5 style package
A block diagram of the CA30BS Series is shawn in Fig. 1. (CA3085, CA3085A. CA3085B. and the B·lead TO·5 with
The diagram shows the connecting terminals that provide dual-in-line formed leads ("01 L-CAN", CA3085S, CA3085AS,
access to the regulator circuit components. The voltage reo CA30858S), The CA3085 is also supplied in the 8-lead dual-
gulston provide important features such as: frequency in-line plastic package ("MINI·DIP", CA3OB5E), and in chip
compensation, short·circuit protection, temperature· fo'm (CA3085H).
compensated reference lIoltage, current limiting, and booster
FflBturtll
input. These devices are useful in a wide range of applications Fig. I-Block diagram of CA3085 Srie$.
for regulating high-current, switching, shunt. and positive and • Up to 100mA output current
negative voltages. They are also applicable for current and • Input and output short-circuit protectton
dual-tracking regulation. • Load and line regulation: 0.025% MAXIMUM RATINGS. ABSOLUTE-MAXaMUM VALUES.t TA - aoc
POWER DIS$IPATlON:WITHOUT HEAT SINK WITH HEAT SINK ITO-6 ONLY)
The CA3085A and CA3085B have output curre!"!t • Pin compatible with LM100 Serin
uptoTA- fi6'»C. . ...... 630mW uptoTC"lilioC ..• 1.6W
capabilities up to 100 mA and the CAJ085 up to 12 mA • Adjustable output voltage 8bo1IeTA. HOC detnelinurly 116.67 mW/'C lbov. TC" 55°C .... ~;;t~~,,:~ly.t
without the use of external pass transistors. However, all the
• Low noise
devices can provide voltage regulation at load currents greater TEMPERATURE RANGE:
Applications
than 100 mA with the use of suitable external pass Operlting . -55 to +125°C
transistors, The CA3085 Series has an unregulated input • Shunt voltage regulatar Storage . -65 to +lSQDC
voltage ranging from 7.5 to 30 V (CA30BS), 7,5 to 40 V • Current regulator UNREGULATED INPUT VOLTAGE:
(CA3085AI. and 7.5 to 50 V (CA3085B) and a minimum re- CA,3085 . JOV
• SWitching voltage reguldOr
gulated output voltage of 26 V (CA3085). 36 V tCA3085A), CA3085A .. . . 40V
• High-current "ottage regulator CA3085B ... 50V
and 46 V (CA3085BI.
• Combination positive .nd neglti"e
LEAD TEMPERATURE (DURING SOLDERING):
The CA308SA is unilaterally interchangeable with the
CA3055.
¥OI_'.......... AldlSIInce'1116! 1132,""" ([Link]' O.79mml
lrooneaoelor to,,!co"[Link]~ .. t1V50C
• Dual tracking regulator
The CA3085 is available in a sealed-junction 8eam·Lead • See Application Note ICAN-6157 "Applications
version (CA3085L). For further information see File No. 515. of the CA3085·Series Monolithic Ie Voltage
"Beam-Lead Devices for Hybrid Circuit Applications", Regulators".
Maltlrnl,lm Voltage Ratlngi
The follOWing chart gives the range 01 voltages which can be applied to the terminals
listed vertically With respect to the term,nals hsted hOrizontally. For e:o:ample. the
IIOltage range between vertical Term'nal NO.7 and hOrizontal TermInal No.1 IS +3 to -10 IIOlts.
MAXIMUM
MAXIMUM VOLTAGE RATINGS CURRENT RATINGS
TEAM· TE.
INAL INAL liN lOUT
No. No. mA mA
-.-. '10
0
• Voltages are not normally
applied between these
termln(lls, however, voltages
10 1.0
1.0 -0.1
appearongbetween these
_3 _3 term'nal~aresafe"f the
speCIfied voltagellml!S 1.0 -1.0
10 -10
~--
-.1
between all ather termmals
are not e:o:ceeded 0.1 10
-10 ~30V lor CA3085 ,.0
20
40V lor CA3085A.
+r SOV for CA3085B ISO 60
+j: ISO 60
Fig.3-Diss;pation limitation (VIN-VOUT vs. lour).
Substrate
& Case
.0
LOAO CURRENT ([Link]- rnA
Fig.2-Schematic diagram of CA3085 Series. Fig.4- Load regulation charactsristics.
_____________________________________________________________________ 159
CA3085, CA3085A, CA3085B Types
TEST PROCEDURES FOR TEST CIRCUIT FOR lOOIJF
RIPPLE REJECTION ANO OUTPUT RESISTANCE
';' ""-"-
" 1. "IrQ- +2!iV,CAEf' O,ShonE,
,J] 2. s.tES2.t1kHllol".. lEt" 4\1rIM
3. Rnd "OUT On • "TVM, _" ... H_IR,.pKklrd.
Hl'4OOOcw_,...I...,
4. [Link].".... AouT"-AoUT~ YOUTII"!./E,)
Ri.... " . . . ion-'
I. VI~' +25V,CAEF' [Link],
2. Set ES'u1 kHz $0 ItlatE," 3V<_
3. AUd "OUT 0"' VTV,.. _" .. I HIwl.",PKkM, HP4QOD
fUO ,uCK~ii :~E:U: O'IqU'~"'1
.. [Link] ....1tI A,ppI. RIje<;I,o""Qm 2OtOllEIIVOUTI
O>----------OC"-C"c'K _leD [Link] -II
&n:1.1.0II-
I. AfI,n,A'[Link]<;I,[Link] '2"f
Fig. 13- Test circuit for ripple ~jecrion and output ,.stance. I--
i !I''<''I)
VOUT
'sc. VpuLSE
GEN.
I,
__ t l,LLs/cm 92CS-t9001
"OUT,IIIY
1000I!SCENT CD OPEN
·ntELlIIITINGCURllErotTIS
--.l. Fi,.14- Tum-on IIIId tum-off recovery time test circuit with
YOUT 'II.U.I "50 • 40 GIOUND CLOSED INVERSELY PROf'OItTIOHAL to
YOUT IIiIN.) 10k • • TO •. MD. 1 ~ RSCp([Link] associated Wllveforms.
Fig. 15- r.t cin:uit for VRE~ 'quiescsnt, Vour/max.). Fig. 16- T.t circuit for #miting CUmtnt
VouTfmin.).
TYPICAL REGULATOR CIRCUITS USING THE CA3085 SERIES
"
STANCORTPl
I
G,
D,
~,llH~''"
BU."
v,. R,·
".n 9-®_~_~~OUTPUT
~lJ BlACKIEtI
.n.
w
'"'
'"
[Link]~F
ALL [Link] "ALUES AIlE IN ~S _
'OUT,lSV .. .lGYfOyO'IG ..".
REGULATION' 0 ftfLIHE AHD LOADI III. IICA·lttl76lA OR EOUt'ALENT
IIPf'LE ~O.S ..V "'T FUlL LOAD OI·IIC ... ·2MSJl1011'EQUJ' ... L£NT
'''1· G.7tLIII.\lq
Fig. 17-AppIiClltion of me CA3085 Seritls in • rypiul power
lUppIy. Fig. 18- Typic" switching regulator circuit.
.~III:IR1)
ALLREmUNCEYALUESAREtNOHIiS
-'OUT
Ot !KAltoIllD10REOUIVALENT
Ol AliT p·N·"S/LICON TRAIiSISTaR
IRC"'1IlSJI10ilEQUIYALEMTI 'ISCp 5HORT·ClltCUtT
OJ ANYN·p·NStLtCONTRANStSTOILTHAfCAN pltOTECTIONRESISTANCE
HANDLE THE OEilREO LOAD CURREHT
(RCA·INl1110REOUtVALENTf
ZOO.A~l(."!!lA
ot ANYN.p.N51L1CONTR ... NStSTOR
Fig.21- Combination positive and negative IIOItage regulator
THATCANHAHDLEA1A circuit.
LOAD CUI RENT SUCH A~
II(A lNJ111 OR EOUIYALENT
Fi,.20- Typical current regulator circuit.
Fig.19- Typlul high-currtlflt voltage regulator circuit.
___________________________________________________________________ 161
CA3086
ELECTRICAL CHARACTERISTICS at T A· 25°C Typical Valu.. Intendod Only for Dotill" Guidance TYPICAL STATIC CHARACTERISTICS FOR EACH TRANSISTOr<
TEST CONDITIONS
Typ.
COLLECTOR-TO- BASE VOLTStVcw'3
Char.- TYPICAL
CHARACTERISTICS SYMBOL teristics VALUES UNITS
Curves
Fig. No.
DC Forward-Current VCE ' 3 V IC' lOrnA 4 100
hFE
Transfer Ratio IC- 1OI'A 4 54
V BE VCE ' 3V IE= lmA 5 0.715 V
Base-ta-Emitter Voltage
IE' lOrnA 5 [Link] V
VSE Temperature Coefficient <1V BE /<1T VCE ' 3V,I C ' lmA 6 -1.9 mVI"C
Collector-to-Emitter
Saturation Voltage VCEsa'
's'" lmA, IC' 10mA - 0.23 V 0.'
oz.
-",
"
AMBIENT TEMPERATURE (TAl-*(;
I ' lkHz,V CE ' 3V,
Noise Figure (low frequency) NF
IC' 100000A, RS' 1 k f!
- 3.25 dB
Low-Frequency. Small-Signal
Equivalent-Circuit Characteristics:
Forward Current-Transfer Ratio hI. 7 100 -
Short-Circuit Input Impedance hie I ' 1kHz, VCE ' 3V, IC' lmA 7 3.5 kf!
Open-Circuit Output Impedance hoe 7 15.6 ,umho
Open-Circuit Reverse-Voltage 7 1.8 X 10-4 -
hr.
Transfer Ratio
Admittance Characteristics:
~ V
Forward Transfer Admittance YI. a 31 -j1.5 mmho
Input Admittance Vie I· lMHz, VCE ' 3V, Ie' lmA 9 0.3 + jO.04 mmho
Output Admittance Vo. 10 0.001 + jO.03 mmho
Reverse Transfer Admittance vr• 11 See Curve -
4680.1 2 "68 1 " 6 810
Gain-Bandwidth Product 'T VCE ' 3V, IC' 3mA 12 550 MHz COLLECTOR MILLIAMPERES (Ie)
Emitter-ta-Base Capacitance C EaO VES ' 3V, IE' 0 - 0.6 pF
Fig.7- Normalized hfti- hie' hOlY hre VI 'C'
Collector-ta-Base Capacitance CCSO VCS -3V,I C ' 0 - 0.58 pF
CoIlector-to-Substrate Capacitance CCIO VCI ' 3V,I C • 0 - 2.8 pF
~=~~U:::A~r,:Ar.:·JM'UT
COLLECTOR-TO-EMITTER VOLTS(VCEl-3
COLLECTOR MILUAMPERES{IC)-I
4
~
1130 ....... ;; boe
!~I i~ 41~+--rttr-+--rttr-+-i-ttrl~
z-. 2
.3
8:e 10 -- ii~i '~+--r++r-+--rttr-+-~ttLLV-~
n
I~
0 t - '-!b
'!~4--+~+--+-1-+tr-i~rti1--~
§~5 I~~~H-~~H+-+~~~~
/ ~
~~
-10
QI
... ... ... , .
2
IFREOUENCY (f)-MHr
"
1'--
2
V
100
.68
I
.68
10
FREQUENCY ill-MHz
468
100 0.1
1 2 1~2"""'681OO
FREQl£NCY(fl-MHz
Fig.8- Yfe lIS f. Fig.9- Yie llS f.
-'--'r=r=r=r=l Fig. 10- Y oe VI f.
CMIION-EMITTER INPUT
AMBlENT TEMPER
COLLECTOR-TO-
COLLECTOR MLL
e
TSIVW-3
'1 I COLLECTOR-TO-EMtTTER VOLTSIVcEI.;'
AMBIENT TEMPERATURE !TAI·~·C L:~~
......... .
> :' ..
i
I' ·.·1<2 .•• ·•·
IN ~E::Ai~A:T~~~~lfS _
800 •••••••••••••••
I~ .i~
'"
"-
if -I
:,lootl.;· ·.B ••••. ,' .••.••.•• :iii i :i
. ·...·.H•.•.•.•·.
···r:. .................
!I~,
ell I·::: ~:::;.
2 . .. , . .."" , .
fREOUENCY(fl-MHI I 2 ;, 4 !i 6
COLLECTOR MILLIAMPERES Ucl
7 8 9 10
Fig. 11- Yre lIS f. Fig.72-f T vsIC·
____~--~------------------------------------------------------------163
CA3091D
ELECTRICAL CHARACTERISTICS. For Equipment [Link]
I
TEST CONDITIONS LIMITS
Circuit
CHARACTERlmcs SYMBOL . TA" HOC. IIS-O.5 mA .,.d/or IM'TS
Min. Ty.. MM.
v+-15V.Y---1I5V Cho<.
c....
STATIC CHARACTERISTICS
INPUT CIRCUIT
Input Balance ICorrectionl Currents:
At x Input x= 0 -20 -2.1 +20 uA
lie
Aty Input y' a -20 -8.7 +20 uA
Feadthrouth linearity Bal,n«
lac -34 -2.9 +34 uA
(Correction) Current
OUTPUT CIRCUIT
OtItput Offut Current 100 x8tV=O, -10 -0.23 +10 uA Fig.3- Test circuit for measure""",t of output current swing
-0.330 -0.0076 V capllbilit'!.
Output Offset Voltage Vaa 100 th,.., RL '" 33kO +0.330
<Attput Peak Current Swing 1101 Thru RL .. 24kn 0.41 0.45 mA
Output Peak Voltage Swing IVai Across RL .. 33kn 12 12.9 V
DC SUPPLIES It BIASING
Current Orain (Idling):
At Term. 4 v- --16V 2.' 4.' mA
At Term. 12 V· .. +16 V 2.0 3.0 mA
V r., Measured aero" Terms, 5.5 •. 1 6.7 V
6lt48"= 1rnA
DYNAMIC CHARACTERISTICS
Output Current 10 With I = O.2mA al each 0.21 0.32 mA
input
11 0." 1.0 1.7
Accuracy 2.6 4.0 ",of
Wont case at 250C
linuritv 1.7 3.0 10V
Fig.4- Test circuit for measurement of output vol,.", swing
FMdthrough Voltage: capability.
Atv",20VH.X'"'O 20 mV
Atx· 20V H.V - 0 20 pop
1 l~ .[Link]".-v... TUTPROCEDuRE
~'-'=-L-L"-L!!!'-'-, b v.~vla. r'--'...!....L!::....L_L.....J..;;J,',QPtfil 'I~ ADJUST V,
TO sn Vo-4V
RI~.I~~~::W"I II: Cl,.ost 's' NINSl ~
TOIlT VO'2:V.
:~':'~!:~:T IIIECOIilD RII
OFV.""DVt ..... D
'-r",-".,-,r-,---r' ~\~ ~ :;ASURt- L,:::oc:--r.:::-t:::-r.--r:::--r.J' DERIVE RO 'ROM ...
+-'----"0
81 IC
Rotlllal'~D
r
Fig.5- Test circuit for measurement of inpuf resistance. Fig.6- Test circuit for tnfNIsu~ment of oufpuf resistance . Fig. 7- Test circuit for measursment of maximum sll1w [Link].
. . . . . .T " ". . . .
I I...l, . l!J. 111\.\·1."
"""'".J ~
TOTAL LOAD R£SISTANCE
~Q
. -. o
.~... "\
r
~
.~.~
f'J \
~ -" \
~
i! -e
-24
-30
10K 2 " . IIIJOt' 2: " ' _ .. " "10M
FREQUENCY III - Hz
Fig.8- Test circuit for measurement of frequency response. Fig.9 v-input fn!quency response chMacteristic curve with associated test circuit.
W
______________________________________________________________________ 165
CA30910
Vref.
Temperature compensated zener connected to the -15 volt
supply to provide a reference voltage as an aid in setting up a
stable liB.
[Link]
The input vol1ilges to be multiplied.
x·Ballnce Circuit
Sets the output to the zero level when the x-input is in
u""- 1/
I'lVt- .....
V
I
i
\
11
..
,
\'\. "\
'~
the zero state.
,/ 1\ ,'\ '<~
y-BllInce Circuit II \ I'
I'\. ....... r-
Ii
Sets the output to the zero level when the y·input is in the
zero state. / !'- ...... r-.. --Me-
Note: See "Contour
Accuracy Map" in "Symbols,
r
Accuracy defines the degree of error encountered in the f--
r-. .... .- e-
Terms and Defini·
~ '\
operation of the multiplier. It is portrayed on a contour map tions" Section.
f-
by isomers (contour lines). Isomers with the highest values
indicate "Iess-accurate" operation of the mUltiplier. (See to\ V/"v .- t-
illustrative Contour Map in Fig. 12.1
\ 1\ ~ f-
Contour Map ~\ i~ ~
The contour map, shown in Fig. 12, is a graphical portrayal
Jt~
of the mUltiplier errors in the x, y input plane. Each contour 'N//.
line, termed "isomer", connects those points whose error ,/
values (in millivoltsl are equal in magnitude. For example, a tlLn 11 'po'il
-20 mV contour line with points at Vx '" 5V and Vy '" -3V
indicates that the output voltage is 20 mV less than the
theoretical output product (kVxVyl. This error voltage,
Jio~~
-00 -. -.
~
-& -! -.·5
./
-2-1 ,
,--.ouT YOLTIoGECV.I-V
..
\ \ l \1 1\1 -'to_~~
00
presented in percent of full·scale input (± 10 VI. defines the Fig. 12-Contour mapping of multiplier accuracy (plotted on i,omer,) and linearity.
"accuracy" of the device. Thus. a 2O-mV error vohage
represents an "accuracy" of 0.2% as derived from the
equation:
Accuracy '" 20 mV/10 x 100% '" 0.2%.
~
Linearity Adjust
A contour map provides a true indication of multiplier
performance in each of the four quadrants. Each CA3091 D is
comprehensively tested and must provide the specified
An external circuit to pro'll ide vernier adjustment for
optimum linearity. This control should be adjusted before
adjusting the y-balance control.
'l vo·, v,v,
accuracy in the four quadrants. Linearity Balance Circuit (Low-Levell
This circuit makes the multiplier's transfer function linear for
Current Convarter
low-level x-input signals.
This portion of the IC combines the multiplier's differential· Fig. 13-Gain-controlled amplifier.
amplifier output currents and converts them to a single- Linearity Compensator
ended output current. Internal circuitry that converts input current into a non-
linear voltage, a requisite for producing a linear output in the
Current Sources The basic multiplier, shown in Fig. 141, is a two· quadrant
differential amplifiers of the multiplier circuit.
These circuits provide the biasing currents for the various multiplier. The input signal (Vxl may have either a positive
Multiplier Circuitry or negative polarity whereas, the external gain·controlling
circuits in the IC. The 118 terminal provides the control
Provides the product of the two inp~t voltages. signal (Vy) must be positive and weater than the base·to·
current for the current·source circuit.
Multiplier Transfer Function emitter voltage (Fig. 14b). The output current (11-12) of the
_through
This function mathematically describes the interaction of the differential amplifier, comprised of transistors Q1 and 02, is
Feedthrough occurs when an output signal is produced even
two inputs and the resulting output signal. The basic transfer related to both the input signal (V x ) and the current source
though one of the input signals is zero. Consequently,
function for a multiplier is III. Since the current source (I) is related to the gain
feedthrough signal characteristics constitute a source of error
controlling signal (Vyl the output current (11-121, therefore,
in the operation of a multiplier. In the CA3091D, for
is related to both Vx and Vy .
example, the feedthrough signal output is specified to be less k(V x + Vxel (Vy + Vyel '" Vo + Voe
than 20 mV Pop when either terminal is set at 20 V p.p and
the other terminal is set to zero. wt,ere: k '" k factor and represents the basic gain of the
multiplier
liB
Circuit biasing control current. Vx , Vy = the external inputs to be multiplied
IIC Vo '" the desired value of the product output signal
See 10C. Vxe• Vye "" the "effective" errors that occur at the inputs
10 of the multiplier and cause an output signal
Output prOduct current (kllxly '" 10), where kl '" kR~ J RL when either input is in a zero state.
[Link] Voe "" the error voltage that develops at the output of '"
Compensatory input and output currents required to correct the multipl ier
unlinearlty alongthe x axis. (Optional for low-1M signal use.)
[Link] '0'
DC correction factors are added to the multiplier inputs and
Input currents to be multiplied. b) Multiplier functional
output to compensate for the errors and offset variations. A
k a) Basic circuit. only in shaded region.
complex linearity error term appears in the transfer function;
Voltage Scale Factor (determines the gain of the rnultiplierl.
however, this term is not included in the above equation for Fig. 14- Two-Quadrant multiplier.
kl the purpose of clarity.
Current Scale Factor (kll '" (R~ J RL)k.
[Link]
This relationship is essentially non-linear; thus an appro·
Scale-Factor Adjustment. OPERATING CONSIOERATIONS priate linearization circuit must be provided in the input
stage to achieve the following linear relationship:
Linearity Oparation of a Multiplier
"Linearity" indicates the degree of multiplier error (i.e. 11-12 = k' Vx Vv (EO. II
deviation from "straight· line" characteristicsl along each of A mUltiplier is. essentially, a gain-controlled amplifier (See where k' is a constant
the four boundaries of the input x, y field. These boundaries Fig. 13) that multiplies the input signal (Vxl with the
are formed when one input is held at one of the two external gain [Link] signal (Vyl to produce the resultant
maximum values (10 volts or -10 volts) and the other input output (Vol. The gain is externally adjustable by a coef-
is swept through the voltage range. (See Contour Map for ficient (k). Stated simply, a multiplier produces an output
additional information.) voltage that is the liner product of two input voltages.
___________________________________________________________________ 167
CA3091D
Tabl. II - Divider Ali",ment Procedur.
....
No.
v,
V.
Sot
Vy
V
Vs
10Vdc
- Vo
Vo
Output
Coupting
de
T...
Equipment
ac-VM
de -VM
"""
Adju..
0,.,.
"belance
N_
Sat all potentiometers to center of range.
Adjust for minimum reading.
Adjust for OV de output.
Vs Vs Vo ac-VM Vbalance • Adjust for minimum reading.
5Vdc 5Vdc Vo de de -VM kadjuit Adjust for 10V de output.
CONNECT V. AND V,
T£RMtNALS F~ SQUARER
OPERA'
'0 b) Terminal connections for multiplying operation.
-IOV!5I1o~IOV
"SEE FIG. II FOR
PERIPHERAL
CIRCUITRY
VI Vo
a) Circuit arrangement for multiplier or squarer operation. c} Terminal connections for squarer operation.
Fig.18-Multifunction circuit-board arrangement with terminal connections for mUltiplier and squarer operation.
.. SEE FIG. II FOR PERIPHERAL CIRCUITRY Fig.19-(b) Circuit to provide offset ac signal for use in
Fig. 19-fll) Divider alignment circuit. dMder alignment procedure.
"
~Y:!iYr S l o Y Q - - - - - c H
1
"
-IO:!iYO:!iIOV
"
v,
"SEE FIG· II FOR
V- .. -I!lV PERIPHERAL
CIRCUITRY
a) Circuit arrangement for divider operation. a) Circuit arrangement for square-rooter operation.
Vo v,
"
b) Terminal confHICtions for divider operation. b) TflTminal connections for SQuare-rooter opBration.
Fig.20-Multilunction circuit-board arrangtlment with rer- Fig.21-Multifunction circuit-board a"angemsnt with ter·
minal connsction. for dividtH operation. minal connection~ for SQuare-rooter operation.
______________________________________________________________________ 169
CA3093E
ELECTRICAL CHARACTERISTICS at TA • 25'C
I. SET OC FORWARO-CURRENT TR~~~FER RATIO !IIFEI'IO
For Equipment Delign
1 =_rMPERfATUR~TAI'70'C
CHARACTERISTICS SYMBOL
TEST CONDITIONS
Min.
LIMITS
TVp· MalC.
UNITS 0'-=:+---+ - - -,
-~.~t-~----t-:-t-1
t---t--L---rt~IL'--H
06- - i - - L L
For Each Transistor:
o.• r---j-----jJ -r-t-t-:;rr-______'t--r-n
Collector-la-Base Ie = 10DltA, Ie '" 0 20 60 v V /
~r--""',:.\~r-
VIBAICBO
Breakdown Voltage 0.2
Collector-Io-Emitter Ie '" 1 rnA, 18 = a 15 24 v ......... r--_1T~PICfo,L
VIBRICEO
Breakdown Voltage
t::: ii
CollectOl-l0-Substrate V(BAICIO lei = 100pA, 'S = 0, 20 60 v 4 I I
'0
"
Breakdown Voltage COLLECTOR MILLIAMPERES IICI
Ie '" 0
Emitter-to-Base V(BA1EBO Ie .. 500pA. Ie '" 0 5.5 6.9 v
Fig. 5- VCEsatvslcat7tfC
Breakdown Voltage
Collector-Cutoff·Current 'CEO veE" 10V, Ie '" a 10
Collector-Cutoff-Current leBO Ves = 10V, Ie = 0
! SET oc FORWAAO~CUARENT TRANSFER RATIO I~FEI' 10'
76 ii ANBIENT T(MP[RATUAE ITAI • 25-C ,--,--t--H
DC Forward Current veE = 3V pc '" lOrnA 40
Transfer Ratio hFE
,lie" SOmA 40 75
': O.9r-- - . __ .. t--
Forward Base-Io-Eminer Voltage veE'" 3V, Ie = fOrn 0.65 0.74 0.85 v
Collector-ta-Emitter VeE,at Ie = 50mA, IS = SmA 0.40 0.70 v ~ o.• r--+---+--+-t--b.,..-<'f-V_-+--t--H
i.. ~
Saturation Voltage
Forward Base-fa-Emitter Ie = lOrnA -1.9
0.'p..~T---+----t----t-+-----t--t--+-H
Temp. Coefficient
For Transistors a, and Q2 lAs a Differential Amplifier)
Absolute Input Offset Voltage 1.2 mV
VCE <0 3V, IC '" 1mA I--f---f---+-----j
Absolute Input Offset Current 0.7 2.5
'0
COLLECTOR MILLIAMPlRES I1c'
Temp. Coefficient of Offset Voltage
Fig. 6- VSEsatvslC
For Each Zener Diode
Zener Voltage Vz IZ = 10mA 6.3 7.7 v
Zener Impedance 'z IZ;; 10mA.f ;; 1 kHz 15 25 n >
Zener Reverse Current 'ZA Vz = +5V
i 6 COLLECTOR-TO-EMITTER VOLT (vCEI'3v
[Link] TEMPERATURE ITAI' 25°C
Zener Voltage Temp. Coefficient llVZIIlT IZ '" 10mA +3.6
~ 5r---
i.e. +.05
Zener-to-Substrate Breakdown VIBRIZIO IZ = 100llA 20 60 v ~ "r---
g
Voltage !Terminals 7 & 91
Dissipation Refer to Example in 250 mW
Application "a"
For Diode 1011
Diode Forward Voltage IC '" 10mA, VCE '" 3V 0.65 0.74 0.85 v
~
.. ,
I
Diode Forward Current 50 mA
Diode Reverse-Breakdown Voltage V(BRIDR lOR = 5Oa",A 5.5 6.9 v
COLLECTOR MILLIAMPERES IIcl
Diode-te-Substrate VIBRlolO loiode = l00IlA 20 60 v
Breakdown Voltage (Terminal 101 Fig. 7- V,Ovslc(transistors01andQ2asa
differential amplifier)
Oieda For.....'d-Voltage 'OF = 5mA -1.9
Temp. Coefficient
AMBIENT TEMPERATURE (TAI'2SoC
t •• COLLEC OR-TO-EMITTER\lOLTS I\lCEI')\I FREOUENCY III'IKHI
-.= AMBIENT TEMPERATURE ITAI-25'C
1 J .1 I
'r--r--t-~"+~--~--r-t-+~
'1 • i .0
J'. J~lNT JMPERAll JJ ~c !~
~ ,
40
~ _25°C !~
! - O"c
6
••• +
m
, ,
COllECTOR l,I'll'AUPERESIICI ~le5-'71n
Fig. 8 - I/O vs IC (transistors 01 and 02asa
0.' '0
Z£NER MILLIAMPERES tlzi
'00
ZENER MILLIAMPEAESllzl " '"
differential amplifier) Fig. 9 - Typical Zener breakdown voltage vs current Fig. 10 - Typical Zener impedance vs current
______________________________________________________________________ 171
CA3094, CA3094A, CA3094B Types
Programmable Power Switch I Amplifier Features';
- DeSigned for single or dual power supply
For Control & General-Purpose Applications - Programmable: strobing, gating, squelching.
AGe capabilities
CA3094T,S,E: For Operation Up to 24 Volts - Can deliver 3 watts (avg.) or 10 W (peak) to
CA3094AT,S,E: For Operation Up to 36 Volts external load (in switching mode)
CA3094BT,S: For Operation Up to 44 Volts - High-power. single-ended class A amplifier will
deliver power output of 0.6 watt (1.6 W device
The CA3094 is a differential-input power- millivolt change at the input will change the dissipation)
control switch/amplifier with auxiliary cir- output from 0 to 100 mA (typical). - Total harmonic distortion (THO) fill 0.6 W in
cuit features for ease of programmability. class A oparation -' 1.4% typo
For example, an error or unbalance signal can The CA3094 is intended for operation up to
be amplified by the CA3094 to provide an 24 volts and is especially useful for timing - High current-handling capability -100 mA (avg.).
on-off signal or proportional-control output circuits. in automotive equipment, and in 300 mA (peak)
signal up to 100 mAo This signal is sufficient other applications where operation up to - Sensitivity Controlled by varying bias current
to directly drive high-current thyristors, re- 24 volts is a primary design requirement - Output: "sink" or "drive" capability
lays, dc loads. or power transistors. The (see Figs.28.29 and 30 in Applications Sec-
CA3094 has the generic characteristics of the tion). The CA3094A and CA3094B are Applications; 'ol.
RCA-CA3080 operational amplifier directly like the CA3094 but are intended for oper- - Error-signal detector: temperaturit control
coupled to an integral Darlington power tran- ation up to 36 and 44 volts. respectively with thermistor sensor; speed control for
sistor capable of sinking or driving currents (single or dual supply). shunt wound dc motor
up to 100 mAo These types are available in 8-lead TO-5 - Over-c:urrent. over-voltage, over-temperature
The gain of the differential input stage is style packages with standard leads ("T" protectors
proportional to the amplifier bias current suffix) and with dual-in-line formed leads - Dual-tracking power supply with RCA-CA3085
(lABC). permitting programmable variation, '''DIL-CAN'' ("S" suffix). Type CA3094 is - Wide-frequencv-range oscillator - Analog timer
of the integrated circuit sensitivity with either' also available in an 8-lead dual-in-line plastic
package "MINI-DIP" ("E" suffix), and in - Level detector _ Alarm systems - Voltage followe
digital and/or analog programming signals.
For example, at an IABC of 100 jJ.A, a one- chip form ("H" suffix). - Ramp-voltage generator - High-power
comparator
- Ground-fault interrupter (G FI) circuits
CA3064 CA3094A CA3084B
DC SUPPLV VOLTAGE:
DUll Supply , ••• ' •.•.••. , ...... ,., ........ ,' .. .12 V .lav '22V V
Single Supply ., ................. ' ........... . 24V 36V 44V V
FUNCTIONAL DIAGRAMS
DC DIFFERENTIAL INPUT VOLTAGE
(T..minals 2 and 3) ........................ ' • ' - - - - - .5"-------- V SINK OUTPUT
(COLLECTOR)
DC COMMON-MODE INPUT VOLTAGE.,.,., ••.••.•. Term. 4 < Term. 2 & 3 <; Term. 7 EXTE;ANAL
PEAK INPUT SIGNAL CURRENT FREQUENCY
(Terminal. 2 and 3) ........... , ............... .
PEAK AMPLIFIER BIAS CURRENT
--------.1-------- mA
COMPENSATION
OR INHIBIT
INPUT
(TerminalS) ................................ . --------2 -------- mA
6
DRIVE OUTPUT
IEMITTER)
OUTPUT CURRENT:
Peek ............ , ..... , .... ,',., .... ' ...... . - - - - - 300-------- mA DIFFERENTIAL
VOLTAGE
.lABe ClJRA[r.1T
Average •................ ---------100-------------- mA INPUTS
DEVICE DISSIPATION: ~PAOGRAMNABL~
INPUT
(STA08£ OR AGel
Up to TA = 55DC: GROUND. Y· IN
QUAL-SUPPLY
Without heat sink •........................ - - - - - - - 630------------ mW OPERATION
With heat sink .......... , ....... . - - - - - - - - - 1.6 - - - - - - - - - - - - - W
NOTE PIN 4 IS CONNECTED TO CAS[
Above TA = 55°C: TOP V'[W
Without heat sink derate linearly - - - - - - 6.67 - - - - - - - - mWfOC
With heat sink derate linearly .............. . - - - - - - 16.7 mWfOC TO-5 Style Package
THERMAL RESISTANCE
(Junction to Airl ••.••..••.•...•.....•.•..•..••• - - - - - - 1 4 0 - - - - - - - - - oe/W
[KTERNAL
AMBIENT TEMPERATURE RANGE: F'REQUEf(CY SINK OUTPUT
Operating ....•.............................. 55 to +125 - - - - - - - - oe COMPENSATION
OR INHIBIT
1 8 (COLLECTOR)
Storage ..................................... . - - - - - -65 to + 1 5 0 - - - - - - - - oe INPUT
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 • 1/32 in. (1.59' 0.79 mm) DIFFERENTIA
VOL.T4GE DRIVE OUTPUT
from case for 10 s max. - - - - - +300-------- OC INPUTS •
IUIITTERI
-Exceeding this IIoltege reting will not damage the device unless the peak input signal current (1 mAl is also exceeded. GROUND. V· IN I"A8C CURRENT
DUAL· SUPPLY
OPERATION
4
• ~PROGRAMMABL.£~
INPUT
CSTROBE OR AGel
TOP VIEW
Plastic Package
________________________________________________________-----------173
CA3094, CA3094A, CA3094B Types
ELECTRICAL CHARACTERISTICS at TA - 25°C For Equipment Design TYPICAL CHARACTERISTICS CURVES
(Cont'd)
..
TEST CONDITIONS LIMITS 10: SUPPLY VOlTS:V o+la,V- __15
Single Supplv V+ =30 V
Dual Supply V+ = 15 V, -;:'105
~
CHARACTERISTIC V- =15 V Min. Typ. Max. UNITS C
ffi
'
•
IABC =100/JA ! ,
~
10 2•
Unless Otherwise 1 •
Specified ~ 10:
+125·C
-I-25"C
I II
= , V) ~.r ~ -5S"C
OUTPUT PARAMETERS (Differential Input Voltage
Peak Output Voltage:
(Terminal No. 61 V+ = 30V
~I
.
0.1 O.•• ,.A I
2 ... 1
10 100
2 .. 68
tOOO
AMPLIFIER BIAS MICROAMPERES I IAsel
With 013 "ON" V+OM RL = 2 kn to ground 26 27 - V
With 013 "OFF" V-OM - 0.Q1 0.05 V Fig.4 - Input bias current VS. amplifier bias
Peak Output Voltage: 0.5 current (IABC. terminal No.5).
V+=+15V,V-=-15V
(Terminal No. 61
Positive V+OM. RL=2knto-15V +11 +12 - V 10,
.
.. AMBIENT TEMPERATURE (TAl. 25·C
Negative V-OM - -14.99 -14.95 V ,
0,.',
Peak Output Voltage: I •
(Terminal No. 81 V+ = 30 V C 2 "
With 013 "ON" V+OM 29.95 29.99 - V
RL = 2 kn to 30 V
With 013 "OFF" V-OM - 0.040 - V
Peak Output Voltage:
(Terminal No. 81 V+=15V.V-=-15V
Positive V+OM RL = 2 kn to + 15 V +14.95 +14.99 - V
Negative V-OM - 14.96 - V ,
I
Collector·to-Emitter V+ 30 V 2 468 .. 661
0,1 I 10 100 1000
Saturation Voltage IC = 50 rnA - 0.17 0.80 V AMPLIFIER BIAS CURRENT fIAacl-,..A
(Terminal No. 81 VCE(sat) Terminal No.6 grounded I
Fig.5 - Device dissipation vs. amplifier bias
Output Leakage Current current /lABe terminal No.5).
(Terminal No.6 to V+ = 30 V - 2 10 /lA
Terminal No. 41
Composite Small-Signal
Current Transfer Ratio (Betal
V+ - 30 V
VCE = 5 V 100,000 -
.f • 10\ SUPPLY VOLTS:V
'
-+!!I,V-·-I!I
16.000 ~IOs
(dr.!and 0131 hfe Ie = 50 rnA
; :
Outpu t Capacitance: f = 1 MHz
Terminal No.6
eO
All Remaining - 5.5 - pF
Terminal No.8 Terminals Tied to - 17 - pF
Terminal No.4
TRANSFER PARAMETERS
2f.---;55-C,+2S·C
V+ = 30 V 0.1
20,000 100,000 - V/V t "'II t '" " I
A IABC = 100/lA 0.1 I 10 100 1000
Voltage Gain AMPLIFIER BIAS CURRENT trABC1-p.A
6V ou t = 20V
RL = 2 kn
86 100 - dB
Fig.6 - Amplifier supply current vs. amplifier
Forward Transconductance bias current /I ABC, terminal No.5).
gm 1650 2200 2750 /lmhos
To Terminal No.1
Slew Rate:
Open Loop:
Positive Slope I ABC = 500 p.A - 500 - V//ls
Negative Slope RL = 2 kn - 50 - V//Js
Unity Gain
(Non-Inverting, I ABC = 500 p.A - 0.7 - V//Js
Compensated I RL = 2 kn
113.!li>--l--I-l-l-I-I--I-I-+l--.+--l+I+-+-++h
z
. . 1'~-+--I-I+l-I-H++-+-f+f+-!Y~-f!!!""'+.j.i
1-14.5 eM)
2. "' • • 2 '" SI
0.1 I 10 100 1000
AMPLIFIER 81AS CURRENT IIABC1-p.A
Fig.7 - Common mode input voltage vs. amplifier
bias current (lASe; terminal No.5).
_____________________________________________________________________ i75
CA3094, CA3094A, CA3094B Types
+3010' TEST CIRCUITS (Cant'd)
10ICn
...v
",)O,l>
l50kfi
I
EOUT + 1 5 1 1 - - - - -.... --------1
e"""'I~ I
I +15\1
E2OUT-ElooT
I
INPUT VOLTAGE .. ANGE FOR CM...., 1 TO 27V
C.... RIIIBI'20LOG I~
E20UT-ElooT
PPISSIPATION'IV+IIII
EOUT
OrrSET CUAAENT ros' 10 6 ~;; Fig~20 - Common-mode range and rejection ratio
Fig. 19 ..- Input bias current test circuit.
test circuit.
Fig. IS - Input offset current test circuit. +15",
..
560tC
,
so EOUT
-15V
Fig.23 - Open-loop slew rate vs IABC test circuit.
120VA(
-15'1
Fig.22 - Open-loop gain
-15'"
frequency test circuit.
'j
Fig.21 - IIF noise test circuit. VI
+15V
COMMON
Cr·O.5p.F 92C5-20405R2
01 ·IN914
CLOSED
RI,o.5IMn=3MIN. .,_-1'-____
LOOP R2" S·' M.D.-30 MIN.
GA'
dO" R3' 22Mn·2HRS. 29Vr---....3V
R4= 44Mn=4HRS.
RS' 1·5 Kn
G> 0----' ,
...-........-
40
'0
'0
R6' 50 KIl
@O
~
TIME-IHR.
R7'[Link]
RS' 1.5K.Q. 52 SET TO R4
*POTENTIOMETER REQUIRED FOR INITIAL TIME SET
TO PERMIT DEVICE INTERCONNECTING TIME VARIATION
Fig.24 - Slew rate VI. non-inverting unity gain WITH TEMPERATURE < 0.3'" I·C.
test circuit. Fig.25 - Phase compensation test circuit. Fig.26 - Presettable analog. timer.
TYPICAL APPLICATIONS IABC, the higher the sensitivity - i.e., a equipment design is sufficiently flexible to
For Additional Application Information, re- greater-drive current capabi lity at the out- !olerate a wide range of these parameters, it
fer to Application Note ICAN-6048 "Some put for a specific voltage change at ·'s recommended that the equipment designer
Applications of a Programmable Power! the input. begin his calculations with an IABC of 100
Switch Amplifier IC". 2. Required Input Resistance - the lower !lA, since the CA3094 is Characterized at
Design Considerations this value of amplifier bias current.
the IABC, the higher the input resistance.
The selection of the optimum amplifier bias If the desired sensitivity and requred input
current (lABC) depends on - resistance are not known and are to be ex- The CA3094 is extremely versatile and can
1. The Desired Sensitivity - the higher the perimentally determined, or the anticipated be used in a wide variety of applications.
______________________________________________________________________ 177
CA3094, CA3094A, CA3094B Types
TYPICAL APPLICATIONS (Cont'd)
l}PP[R THR[SHOI...O' v+
.--r---~(I!5 vI
IQOKn
(a) DUAL SUPPLY (bl SINGLE SUPPLY
Fig. 34 ,- Comparators (threshold detectors) -dual-
and single-supply types.
R"
TYPE
DI20lF
10
60 Ht
20V
6O,HI
ALL RESISTANCES IN OHMS -1/2 WATT
Fig.35 - Temperature controller.
MAl{ LOUT':t 100 mA
003,.r
I. ALL RESISTORS IN OHMS, 112 WATT. !IO'l'. S INPUT I~PEDANCE FROM 2T03
EQUALS 800 K.
l,~goS~~[CTEDFOR 3db POINT AT
-15 "
L-~--I--'~-D'" 6. WITH NO INPUT SIGNAl TERM-
INAL 8 [OUTPUT I AT .]6110LT5
OUTPUT " OFFSET ADJ INCLUDED IN RTRIP
.V+I!I!PUT RANGE=19 TO 30 V '---~V\I'~---'
VOLTAGE 8ETWEEN
FOR 15 V OUTPUT TERMI".ALS 2 4 a
**V-INPUT RANGE=-16 TO-30V VOLTAGE 8ETWEEN
FOfH5 v OUTPUT TERMINALS J a4
REGULATION: (ADJUSTABLE WITH
RTRlpl
\ GROUND FAULT
[ Your (INITIAL~ t. 'lIN x 100=0.075% IV SIGNAL 60Hz
::c~~",VUOT"-"''cIlN~''~IA~L~) ~ 100=0,075 % VOUT
(ll FROM I TO 50 mAl
Fig.37 - Ground fault interrupter (GFJ) and
Fig.36 - Dual-voltage tracking regulator. waveform pertinent to ground fault
detector.
________________________________________________________________ 179
CA3095E
Super-Beta Transistor Array Features
• Two super·beta n-p-n transistors - hFE > 1000
Differential Cascode Amplifier Plus 3 Independent Transistors • Voltage-limiting circuitry (01, 02, Q5)
ACA·CA3095E is a monolithic array of transistors con- The exceptionally high·beta characteristics of 01 and 02, • Operation possible at II B down to < 1 nA
nected as a super-beta diHerential cascade amplifier with plus the large signal-voltage swing capability of 03 and 04, • Matched pair (01 and 02) -
three independent n-p-n transistors. (Refer to Fig. 1 for make the composite differential cascade amplifier an excel- V10=5 mV max. at le= 100j..lAdc
following description.) lent choice for a broad range of small-signal, high-input-
110 = 20 nA max. at Ie = 100 IlA dc
The differential cascade amplifier incorporates two cascade impedance amplifier applications including low-noise video
amplifiers. This amplifier is also recommended for use in
• Wide current range - < 1 IlA to 2 mA
amplifiers consisting of transistors 01, Q3 and Q2, Q4,
respectively, plus a voltage-limiting circuit. consisting of long-interval timers, oscillators, and long-duration one-shot Independent Transistors:
diodes D1, 02 and p-n-p transistor 05. Two of these applications.
• hFE = 300 typo for each transistor
transistors, 01 and 02, are super-beta types that have an The independent transistors, 06, 07 and 08, are high-voltage
• Wide current range - < 1 j..IA to 10 mA
hFE > 1000 and are capable of operating over a wide current silicon n-p-n conventional types for general use in signal
• Matched general-purpose transistors
range of 1 J.1A to 2 rnA. Each of these types comprises the processing systems in the frequency range from dc through
input section of its respective cascade amplifier. The output vhf. Separate terminals for each of these transistors permit • High voltage - VCBO = 45 V max_
section of each cascode amplifier employs a conventional maximum flexibility in circuit design_
Applications
n-p-n transistor, 03, Q4, respectively. The output signal is The CA3095E is supplied in a 16-lead dual-in-line plastic
obtained at the collectors of these transistors. See Operating Differential Cascade Amplifier:
package and operates over the ambient temperature range of
Considerations for bias considerations of the differential _55°C to +12SoC • Super-beta pre-amplifier for op-amp
cascade amplifier. • High-impedance dc meter amplifier
• Low-noise video amplifier
• Pie:zoelectric transducer amplifier
• Long-interval timer
MAXIMUM RATINGS, Absolute-Maximum Values at TA = 25 DC Conventional N-P-N Transistors (03, 04, 06, • Long-duration one-shot multivibrator
07,08)-
Power Dissipation: Collector-to-Base Voltage (VCBO) _ 45 V • Comparator with high-input impedance
Anv One Transistor 300 mW Collector-to-Emitter Voltage (VCEOI 35 V • Long·time-constant integrator
Total Package- Emitter-to-Base Voltage (VESOI ,. 6 V • Photocell amplifier
Upto 25°C _ 750 mW Collector-to-Substrate Voltage (VCIO) *. 45 V
• Low-noise amplifier-for operation from high-source
Above 25 °c . _ derate linearly 6.67 mW/oC Collector Current (lCI 50 mA
Base Current liB) . impedances
Ambient Temperature Range: 20 mA
Independent Transistors:
Operating -55to+125 °c Conventional P-N-P Transistor (051-
Storage -55 to +150 °c Collector-to-Base Voltage (VCBOI -45 V • General use in signal processing systems in dc through vhf range
Lead Temperature (During Soldering): Collector-to-Emitter Voltage (VCEO) -35 V
At distance not less than 1/32" 1O.79 mm) Limiting Circuit Current HPin 11) 20 mA
from case for 10 seconds max .. +265 °c
Voltage and Current Ratings Apply for Each * The collector of each transistor is isolated from the substrate by
Specified Transistor: an integral diode. The substrate must be connected to a voltage
Super-Beta Transistors (Q1, 021- which is more negative than any collector voltage in order to
Collector-to-Base Voltage (VCBO) . V maintain isolation between transistors and provide normal transistor
Emitter-to-Base Voltage (VEBO) V action. To avoid undesired coupling between transistors, the
Coliector-to-Substrate Voltage (VCIQ)*. 45 V substrate terminal should be maintained at either dc or signa! (ac)
Collector Current ItCI . 50 mA ground A suitable bypass capacitor can be used to establish a signal
Base Current ItB) 20 mA ground.
SHADED TRANSISTORS ARE
SUPER BETA TYPES
STATIC CHARACTERISTICS
Fig. I-Functional diagram_
Test Conditions limIts
Characteristics Symbol Units Test Circuits for Measurement of Super-Beta
Min. Typ_ Max_
Cascode Amplifier Characteristics
Characteristics Apply for Each Super-Beta Cascode Amplifier Transistor
Pair (01,031 and (02, Q41, Unless Indicated Otherwise
Collector-to-Base Breakdown Voltage
Emitter-to-Base Breakdown Voltage
(Applies only to 01 & 02)
Collector-to-Substrate Breakdown Voltage V{BRICIO ICI - 100 JJA, IS - IE - 0 45 V
VS_8orVlO __ 8-10V, 111" 10DJJA
CoHector Cutoff Current 100
ABE'" 100 MH
VlO_8"5V llC - 1 rnA 1500
DC Forward-Current Transfer Ratio VS-8 '" 5 V I Ie'" 100JJA 1000 2000 5000
Fig.2-V(BRJCBO teu circuit.
I Ie'" lOJJA 1500
Base-to-Emitter Voltage
(ApplIes only to 01 & Q2) IC'" 100 JJA. VS-8 or VlO-8 = 5 V 0.50 0.59 0.S8
ISor 110= 1 mA,lll - 100JJA.
Saturation Voltage V sat 0.22 0.7 V
170r Ig'" 100JJA
For Cascode Amplifiers as a Differential Matched Pair
Magnitude of Input-O~cf::-"_,,-:v:-o_It-,,g'--'_ _+--+IIII,0"-ol';-I_-I Ie ~ 100IJ. A mV
Magnitude of Input-Offset Current V6 -8 = V 10- 8 ~ 5V 20 cA
Magnitude of Input-Offset Voltage Drift I~Vlol
(Temp. Coeff.1 ~ 3.3 JJV/'C
Magnitude of Input-Offset Current Drift
(Temp. Coeff.) 0.05 nA/'e
Note 1; Terminal No.9 to terminals 10 and 11 connected or terminal No_ 7 to terminals 6 and 11 connected Fig.3-ICER test circuit
__-----------------------------------------------------------------181
CA3095E
000 zooo
~ 1&00
~=ij~'f4#+- f-
,::.'0 1'z.50~
:l'
;t 1200
f--!i/I
.1
a::-Q 1-%."" "0"
!it' 800 ~
."
;~
"'III J.o ~,
0.8 1.2
B
000
0
V
II
0.4 0.8 1.2
....
I.. 2
VOLTAGE ACROSS PINS 6 AND 8 (V6_el OR PINS 10 AND 8 VOLTAGE ACROSS PINS 6 AND' (Vi_aiDA PINS IOANO 8
(V,o-e)-\1 (1110-8 1-\1
2~ 50 ." 100
AMBIENT TEMPERATURE (TAI--C
Fig. 10-1· V characteristics frY thll ,uper-b.r. Fig. 1 , -I-V chllrac,.r;stics for tM SU".r-betll
cascodtlpilirs. ClIICodepilirs.
Fig. 12-Collector cutoff cumlnt w lImb;"'t
tBm".,.tu,. for tM CDnlftllltiOllllf
tr"".inors (VCE - 5 V. 10 VI.
COlLECTOR-TO-EMITTER
I C:~~~:R;~::~!~~:E~~~!.(~E
"
,t400
VOLTAGE (IICE.).~V Q9 -.OV
~"EN~ ri~!'TU~ IT": +~ ~
2
i
1'"0 .",,-
,-
/~
V
+2!5"C
- .........
......... ,
i ~r--t--t-+++-+--++t+--t--+-t+I
!
~ 0.7f--+--t-t+t--t--t-H;j;...4'''--t-t-H
,--- ....
I ~ f..---
~ --
~200
- -4O·C
.-
~~L-~~~t+t--t--t-t+t--t--t-t-H
~~
~
I' ~ 0.5
. . .. . . .. . . ..
f
g
0
001 0.1 1.0
COLLEClOR CURRENT (Icl- iliA
10
0.'
0.01 0.1 t
COLLECTOR CURRENT IIC1-mA
... 10
Fig. '3-CoIltJcmr cutoff eummt VI IImbumt
ttlmpttTlltu,. for rile conventiONIi Fi,.14-hFE lfS. Ie for Heh conwmtiona/ Fig. 15- V BE as e function of collector current
trllnsistor lOS, Ol, OBI. for the conlfflntion.1 transistors.
transistors (V cs - 6 V. '0 V, 15 VJ.
!i DC FORWARD CURRENT
TRANFER RATIO IhFE'-1O
/
~ I~-+--+-~+--+--+-~+-~~~
~ ~,~
~> O.• f--+--+-~+--+--+-~+~ftfl----·H-H v-
~tOA ~i1-
tzoo f-----_+------1:7~t__+-t------i
Fo.. !I/~
1/
~ l%.v 1 '00 / /
~ ~2 ~'I ~
8~.I
0.0
. .. I
I II
10
COLLECTOR CURRENT tIc J- mA nCS-2031'!1
2 ... ,
100
COLLECTOR CURRENT IICI - j4A
1000 .000
0.01
10
4 • •
100
4
FREQUENCY If) -
••
Hz
1000
. .. 10.000
92CS-20362
Fig.16-VCE fslltJ lIS a function of collector [Link]-Gain bandwidth product IfS collector Fig. 18-IN n. f for Hch super-beta CMCode
current (or the conventional currllnt for the [Link] clIscode amp/if;" trllnsiuor pIIir (01, 03) and
transiston. pairs. (Q2,04J.
AMIIENT TEMPERATUAE (TAI~25"C
10
... 100
FREQUENCY (n - HI
... 1000
. ..
IOPOO , 10 15
[Link]-TO-BASE VOLUGE (vcBol-v
Fig. 19-EN IIs- f for Nch super-bllta cascade Fig.20-CCB If'. VCBO for esch [Link] Fig.21-CCI lfS. VCIO for tlflCh Wptlr-bfltll
IImp/ifi," transistor pair (aI, Q3) and CBSCOde amplifier transistor pair (01, CIIICOdfJ IImplifier transistor PIli, (01.
(Q2,04). 03) lind (02, 04J. 03) lind 102. 04).
_________________________________________________________________ 183
CA3095E
TYPICAL APPLICATIONS (Cont'dl
,.
..
laMO
" ,%
......
,% ~~~-r.\-Y
Fig.30-High·input-imped/Jnce, low-nOise amplififlr circuit.
Y-'-lY
Fig.29-Super-Mtll Op·Amp with resistor drille network. Fig.31- Typical high-input-impedance dc voltmeter circuit.
Fig.32-Lon~delIlY monostllble multillibrlltor circuit. Fig.33-Low input-bills current compilrllror circuit.
FREQUENCY (f)~Hl
Fig.34-CA3095E wideband IImplifier. Fig.35-Equivalenr inpur noise lIoltage liS. frequency
for circuit of figure 34.
____~----------------------------__--__---------------------------185
CA3096, CA3096A, CA3096C
STATIC ELECTRICAL CHARACTERISTICS at TA =25"C 10
For Equipment Design
LIMITS
CHARAC- TEST
TERISTIC CONDITIONS CA3096AE CA3096E CA3096CE UNITS
Min_ Typ. Max. Min. Typ. Max Min. Typ. Max.
For Each n-p-n Transistor
ICSO VCs= lOV. - 0.001 40 - 0.001 100 - 0.001 100 nA
IE = 0
ICEO VCE = 10V, - 0.006 100 - 0.006 1000 - 0.006 1000 nA
IS = 0 '0 '0
25 0 25
TEMPERATUR'E. _·C " 100
V(SR)CEO IC= 1 rnA, 35 50 - 35 50 - 24 35 - V Fig. 3 - Collector cut-off current (I ceo) as a
IS = 0 function of temperature (n-p-n).
V(SR)CSO IC= lOIlA, 45 100 - 45 100 - 30 80 - V
IE = 0
VISR)CIO ICI = 101lA, 45 100 - 45 100 - 30 80 - V
IS=IE=O
.00
VISR)ESO IE= 101lA,
IC = 0
11 8 - 6 8 - 6 8 - V
::'
~ 400
[Link] J"U.J
~'£."'~~+25.C r-...
Vz IZ = 10llA 6 7.9 9.8 6 7.9 9.8 6 7.9 9.8 V : ~••' V I r-- ,t---
,ooi---""" V
VCEISAT) IC= lOrnA,
IS=l rnA
- 0.24 0.5 - 0.24 0.7 - 0.24 0.7 V
i V
-
- .. o·c
I
200
VSE IC=l rnA, 0.6 0.69 0.78 0.6 0.69 0.78 0.6 0.69 0.78 V
100
hFE VeE= 5V 150 390 500 150 390 500 100 390 670
Il1VSE/l1TI le=l rnA, - 1.9 - - 1.9 - - 1.9 - rnvte
g 0
0.01
, ... 0.1
, . .. I
COLLECTOR CURRENT (Xc l-mA
, .,. 10
VCE = 5V
Fig. 4 - Transistor (n-p-n) h FE 8S a function of
collector current.
09 COLLECTOR-lO-EMITTER VOLTAGE (VeE,-5V
I 0.8f--+-+-+++--f-++tt--t--t-t-tl
~w
~0.7 v~
~ o.6f--±_-I"'H+---1-++t+-+--+-+-tI
~V
e
~ 0.5
04
• 6 e 448 2. 4 ••
0·1 I 10 100
001 01 I 10 COLLECTOR CURRENT IIcl-mA
COLLECTOA CURRENT lIcl-mA
92CS-ZO'll TEMPERATURE --c: t2CS-2O!I4 Fig. 7- VCE(SATI (n·p-n)asafunctionofcol-
Fig. 5 - VBE (n-p-n) as a function of collector Fig. 6 - VBE (n-p-n) as a function of tempera- lectDr current.
current. ture.
______________~------------------------------------------------187
CA3096,CA3096A, CA3096C
DYNAMIC [Link]"·TO-£MITTE" VOLTAGE eveE} • 5'1
ELECTRICAL CHARACTERISTICS at T A = 25°C O'..•~-r--T-rT~-;---r'-~--T--+-+~
__
>
Typical Values Intended Only for Design Guidance
TYPICAL
1:~4--+~~~--~~~~~~~-H
CHARACTERISTICS TEST CONDITIONS
VALUES
UNITS
!; ::~r
For Each n-p-n Transistor ; 0.4
f=l kHz, VCE =5V, ~ O"f--+--+--H+-I-I-++++--+---I-++
Noise Figure (low frequency), NF 2_2 dB ~;I o.2f--+--+--H+-I-I-++++--+---I-+--H
IC = 1 mA. Rs = 1 k!l
.' [Link]--+---t--H+---j-·-+++-+--+---I-+--H
Low-Frequency, Input Resistance, Ri f=1.0kHz,VCE=5V, 10 k!l
4 •• 4 ••
Low-Frequency Output Resistance, Ro IC= 1 mA 80 k!l 0.01 0.1 I 10
COLLECTOR tUIU'ENT Ue I-filA
Admittance Characteristics: Fig. 12 - VBE (p-n-p) as a function of collector
current.
Forward Transfer Admittance, gfe 7.5 mmho
Yfe bfe -j13
TEMPERATU';".;'i~i:
gie f= 1 MHz, VCE = 5V, 2.2 I~ U.,
Input Admittance,
Yie bie
- IC=lmA j3.1 mmho ~o;
Output Admittance,
90e
--
0.76
mmho
Ii ",i
~! ,;
Yoe
b oe j2.4 ~~"
Gain-Bandwidth Product, fT VCE = 5 V,le = 1.0mA 280 MHz :i m: L J~, I','
VCE = 5 V,IC= 5mA 335 ::m::: , f:'i,W
o.
, , m
Emitter-to-Base Capacitance, CEB VEB = 3 V 0.75 pF --:j
TEMPERATURE--C 92CS-20322
Fig. 13 - V BE (p-n-p) as a function of tempera-
Collector-to-Base Capacitance, CCB VCS = 3 V 0.46 pI' ture.
Collector-to-Substrate Capacitance, CCI VCI = 3 V 3.2 pF
l 0.'
For Each p-n-p Transistor ~ 0.8
;<
f = 1 kHz, ;;; ,>1
~
Noise Figure (low frequency), NF 3 dB
IC = lOOIlA, RS = 1 H2 ~.
1/
-
o.
Low-Frequency Input Resistance, Ai
Low·Frequency Output Resistance, Ro
f = 1 kHz, VCE = 5 V, 27
680
kn
kn
~ 0.' .......
/
Gain·S"ndwidth Product, fT
IC = lOOIlA
VCE = 5 V, IC =.lOOIlA 6.8 MHz
iis 0.'
./
0.2
Emitter-to-Base Capacitance, CEB
Collector-to-Sase Capacitance, CCB
VEB = -3 V
Ves = -3 V
0.85
2.25
pF
pF
I• 0.1
" 6 a 0.1 I
" f, e 10
COLLECTOR CURRENT IICI-mA 92CS-f031!3
Base-to-Substrate Capacitance, CSI VSI = 3 V 3.05 pF Fig. 14 - Magnitude of input offset voltage
IV/olasa function of collector
current for n-p-n transistor 01-02-
:> 0.5
E
I
-~ 0.4 I
~
~ 1\ I I;
~ 0.'
.~ Iii
i
~
~
~
;•
02
01 '" ;
1'-- t-L.
VI
1
I
I i
0
0.01
2 . .. 2 .,. I
COLLECTOR CURRENT IIC1-mA
,i . ,I .
92'CS-20324 FR[OUENCYIfI-kHI FREQUENCY{fl-KH~
Fig. 15 - Magnitude of input offset voltage
Fig. 16 - Noise figure as a function of frequen- Fig. 17 - Noise figure as a function of frequen-
Iviol as a function of collector
cy for n-p-n transistors. cy for n-p-n transistors.
current for p-n-p transistor Q4- Q 9
___________________________________________________________________ 189
CA3096, CA3096A, CA3096C
• COLLECTOR-TO-EMITTER VOLTAGE ('ICE)' ~v ! I
~
I
I
I
- j
~l
7
r---. 1
• I ........
I i'-"
, I
--
t OUTPUT
,
0' . 6
I
I to
I
2 6 8 to
COLLECTOR CURRENTI1Cl-mA NOTe:
12 4~618
FI OR F2~ 10KHz
81AS VOLTAGE-v
Fig. 30 - Gain-bandwidth product as a function Fig. 31 - Capacitance as a function of bias Fig. 32 - Frequency comparator using
of collector current (p-n-p). voltage (p·n·p). CA3096E.
•
•
CENTER fREQUENCY: , kHz ,...
7 /
I
~
~
·• /
~ ·,
IOO".F g
02v
J
2
/ -_.
../ - -
'!--
-, o 0 ,
0 20
'2-'.'0 '1"2 'l-f2"0
FREQUENCY DEVIATION (AO-Uh
92CS -20341RI
Fig. 33 - Line·operated level switch using CA3096AE or CA3096E. Fig. 34 - Frequency comparator charac-
teristics.
v+
+vrnmT
OKn
"T K1: I~6RL '0
IF IO. II1'IA
AND Rl" KD
VT: t 36!11V "IN t
-'IT .
':-00 C,
TIME DELAY CHA~GES :I: 7"10
"'OR SUPPLY VOLTAGE CHAfliGE OF ± 10"10
Fig. 35 - One-minute timer using CA3096AE Fig. 36 - CA3096AE small-signal zero-voltage detector having noise immunity.
and a MOS/FET.
70
60 f-.. -
50 _.
+0
3Of--+~t-H+-
20f--+~+-H+--+- -H++--+~+
4 • '10 'r 4 . '100:2 4 . '1000
FREQUENC'((r)-kHr
9ZCS-20346 (SUBSTRATE) -
Fig. 37 - Ten-second timer operated form 1.5-volt Fig. 38 - Gain-frequency characteristics.
supply using CA3096E.
__________________________________________________________________ 191
CA3097E
Features:
Thyristor/Transistor Array • Complate isolation between alaments
• n· .." transistor - V CEO"" 30 V (min.)
For Military, Commercial, and Industrial Applications IC - 100 mA lmax.)
• p-n-p/n·p-n tf'llnsistor pair - beta
2: 8000 (typ.) OIC - 10 mA. individual p-n-p, n-p-n,
RCA·CA3097E" Thyristor/Transistor Array iS'a monolithic in- or transistor pair operation
Includes:
tegrated circuit that enables circuit designers to further inte-
• Programmable unijunction transistor
grate control systems. The CA3097E consists of five inde- • Uncomroitted n·po" Transistor
(PUT) - peak-point current - 15 nA
pendent and completely isolated elements on one chip; an • [Link]-Gate Silicon Controlled Rectifier (typ.) at RG = 1 Mil; V AK • ±JO V
n-p-n transistor. a p-n-p/n-p-n transistor pair, a zener diode, • Programmlble Unijunction Transistor (PUTI • (PUT) Extremely long RC time constants
a programmable unijunction transistor (PUT), and a sensitive- • p-n-p/n-p-n Transistor Pair with low .,.Iue of external capacitor
gate silicon controlled rectifier tSCR),
• Zener Diode • Sentitive-gate silicon controlled rectifier tSeR} -
The CA3097 is supplied in either the l6-lead dual-in-line
• Separate Substrate Connection 150 mA [Link] current (mo..)
plastic package ,"E" suffix) or the chip version ("H" suffix).
and operates over the full military-temperature raoW' of • Zenor·dodo impoclance IZZ) = 1511
-55 to +1 ?50 C. Ityp.) at 10 mA
Applications:
MAXIMUM RATINGS, Absolute·MlIJ(imum Values at TA = 25"C
• Tinws
Isolation Voltage, any terminal to substrate'" ........................ ,., ............................ . +50 V • Light dmmenlmotor controls
Dissipation, Total Package: • [Link]
UptoTA""550 C ........•.... , ............................ , 750mW • "One-shot" multivibraton
Above T A = 55°C .......................................... . derate linearly at 6.61 mWfOC • [Link].,laton
Ambient Temperature Range:
• Coma-raton. Schmitt tri.,,.
Operating ................................................ . -55 to +1250 C
Storage .......................................................... . -65 to +1500 C • Constant-CIU"ent sources
Lead Temperature (During Soldering): • Amplifien
At distance 1116 ± 1/32 inch n .59 ± 0.19 mm} from case for 10 seconds max ....................... . +265 0 C • Logic circuits
Each n-pon Transistor (03,061 • SCR uilllrmil
n
The following ratings apply with terminals 6 & 9 connected together. • Pul.. Circuits
ColiectoHo-Emitter Voltage (VCEO)'" .................................................... . JOV
Collector-to-Base Voltage (V CBO) ....................................................... . SOV
Emitter·to-Base Vmtage (VEBOI ...................•..... , ................................. .
Collector Current Uci .................................................................. .
Base Current (lSi ...................................................................... .
Dissipation (POl ...................................................................... .
SV
100mA
20mA
SOOmW
:-1'-Y-"--3-:' ·:-r--1
I
I
p~ ZI~!
6_-
SU8STRATE :
L__ _ _ _____ _ __ ..JI
p-n-p Tramistor C04)
5 4 I 7 15 1
The following ratings apply with terminals 1 & 8 connected together.
CoIlector-to-Emitter Voltage (VCEO) ....................................................... . ~40V
Coliector·to·Base Voltage (Vcse) ....................................•..................... -50 V
Fig. , - Schematic diB(JT8m of CA3091E.
Emitter·to·Base Voltage (VESe) .......................................................... . -10 V
Collector Current (lC)" ................................................................. . -10mA
Base Current US) .. .. .. .. .. .. .. . . . . . .. .. . .. .. . .. .. .. .. . .. .. . .. .. . . .. . . .. .. .. .. .. .. . .... . -3mA TYPICAL CHARACTERISTICS
Dissipation (Pol ...•..•................................................................ 200mW 1 AMIIENT TEMPERATURE (TA"25-C
1H1-p/n-p-n Transistor Pair (03.04) [Link]'ENT TRANSf'ER RATIOCIc/1e'-1O
Dissipation (POl .................................... '................................... . 500mW
Pro. .mmabla Unijunction Transistor, PUT (Q1) ~,~~--~~~-+--+-~+--t--+-~
Gate-to-Cathode Positive Voltage IV GK)' .................................................... . JOV !
Gate-to-Cathode Negative Voltage IV GKR)' .................................................. . SV
Gate-to-Anode Negative Voltage IVGA) .....•................................................ JOV
Anode-to·Cathode Voltage (V AK) ......................................................... . ±JOV
DC Anode Current ............ 'r' • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • IS0mA
Peak Anode Non-Recurrent Forward (On-State) Current 110 lAs pulse} ............................. . 2A
Total Average Dissipation ................................................................ . 300mW
Silicon Controll'" Rectifier, SCR IQ2)
Repetitive Peak Reverse Voltage (VRAXM), AGK" 1 K{l .......... , ........•.................... JOV
Repetitive Peak OII·State Voltage (VORXM), RGK' 1 kll ...................................... . JOV
oC On·State Current UTOC)" ............................... , ..•...•.........•............ " I) 8 1 " 6810
IS0mA
[Link] CURRENT {Ic)-mA
Peak Surge (Non-Repetitive) On-State Current (10 p.s pulse) ...................................... . 2A
Forward Peak Gate Current (lGFM) ......•........•.•....................................... 20mA
Peak Gate-ta-Cathode Reverse Voltage (VGRU).' _ ............................................ . Fig.2 - Base-ttHJmitr.T utul'lltion WJIr... n. colllJt:tOT cUmlnr for
SV n-p-n ".m/non 03 & 05.
Total Average DiSSipation .....•........................................................... 300mW
Zonor DioIto,IZU
OCCUrrent~ ..........................................•............................. 2SmA
Dissipation (POl .. '.' ................................................................... . 250mW
• One or more of the terminals of each element of the CA3097E is isolated from the substrate by a junction diode. I n order to
maintain electrical isolation between elements, the substrate terminal must be connected to • voltage which is no more posi-
tive than that of any other terminal. To avoid undesirable coupling between elements, the substrate terminal (terminal 10)
should be maintained at either de or signal .ac) ground.
.MBIENT TEMPERATURE ITAI-·c
Fig.3 - B...-tlHlmlttM IIOItilftl .. ambient ,."",.,."ru,. for"."."
trMUhton 03 & 05.
_______________________________________________________________ 193
CA3097E
TYPICAL CHARACTERISTICS (CONT'D)
ELECTRICAL CHARACTERISTICS (Con"d.1
CHARACTERISTIC SYMBOL TEST CONDITIONS FIG. LIMITS UNITS
Ambient Temperature NO.
(TAI- 250(:
Unlell Otherwise Specified Min. Typ. Max.
PROGRAMMABLE UNIJUNCTION TRANSISTOR (PUTI. O~ ~
~6000
OFFSET VOLTAGE VT'
Vs = IDV, RG = lDHl
11,22"
0..2 - 0..7
V
Vs = lDV, RG - 1M!:! 0..2 - 0..7 ~
~4000
ANODE·TO·CATHODE IF = 5DmA - 0..90. 1.5
i
VF 12 V
ON·STATE VOLTAGE 'F = lDDmA - 1 -
2000
C = D.22pF
PEAK OUTPUT VOLTAGE YOM 13,23 - 10. - V g
Anode Supply Voltage = 20V
6 8 100
Vs = lOV, RG = lDkil 14,22" - 0.55 1 [Link] CURRENT IIC"mA
PEAK·POINT CURRENT Ip /lA
Vs - 10V, RG = lMil - - 0..0.15 0..15
Vs = lDV, RG = lOkil 17,15 4 40. - Fig.. 10 - DC fDfWllrd-cun'Mt trans"'" ",t;o vs. collector cummt
VALLEY·POINT CURRENT ~A 10f' tramistor PIli, 03, Q4.
'V
Vs - lDV, RG - lMil 16 - - 25
GATE REVERSE CURRENT 'GAO Vs - JOV 22" - 0..0.2 - nA
GATE-tO-SOURCE VOLTAGE IVSI'IO~ t-I.
GATE REVERSE CURRENT 'GKS ~~~[Link] Short, VS, 22" - 0..2 - nA
0 .•
OUTPUT PULSE RISEl'lME tr
Anode-Supply Voltage
C=O.22~F
20V 23 - 60. - ns
SILICON CONTROLLED RECTIFIER (SCRI. 02
PEAK OFF·STATE CURRENT'
~ 0.3
FORWARD 'DXM VDRXM = 3DV, RGK = lkil 24 - - 2
~A
~
~
REVERSE 'RXM VRRXM = 3DV, RGK = lkil 24 - - 2 ,... 0.2
FORWARD DC VOLTAGE DROP VT IT= SOmA 18 - 0..90. 1.5 V ~ 0.'
o
GATE·TO·SOURCE TA"" 25°C 26 - 33 100
~A
'GS
TRIGGER CURRENT TA = -55°C 26 - 50 - ·50
DC GATE·TRIGGER VOLTAGE VGT V L = IDV, RL = lODil 19 - 0.55 0..75 V
HOLDING CURRENT 'HO RGK - lkil 20,24 - 1.2 - mA
CRITICAL RATE·OF·RISE EXPONENTIAL RISE,
OF OFF·STATE VOLTAGE
dv/dt
RGK = lkil, VDRXM = 3DV
25 - 150. - V/lls
GATE·CONTROLLED
TURN·ON TIME
'gt See Fig. 33 33 - 50. - ns
CI RCUIT·COMMUTATED
to See Fig. 33 33 - 10. - ~s
TURN·OFF TIME
ZENER DIODE, ZI
ZENER VOLTAGE Vz IZ = lDmA 21 7.2 8 8.8 V
ZENER IMPEDANCE Zz lZ - lOrnA, f = 1kHz - 15 25 il
ZENER VOLTAGE IAVzlVzJ/t'lT IZ= lOrnA "- -10.05 - %1°C
t'lVzjt'lT - -
TEMPERATURE COEFFICIENT
ZENER·TO·SUBSTRATE 'Z=I~A
"" -
mV/oC
~ 4 6 e, 2 " 6 8 10 2 4 6 8'00 2 4 6 81000
BREAKDOWN VOLTAGE
V(BRIZIO
TERM. 5 TO SUBSTRATE
50. 80. - V ANODE-tO-CATHODE ON-STATE CURRENT tIFI-mA
• VT = Vp - Vs (F'g. 221
Fig.'2 - Anode-to-cathodfl on-state voltage VI. anode-to-cathode
on-stlltfl current for 01 (PUTJ.
CURVE (.I): AMBIENT TEMPERATURE (T... }=25°C !~lii
..... BIENT TE .... ERATURE ITAJ·2~·C
FOR TEST CtAUIT. SEE fiG. 23
:
I CU~E (BI:
EQUIVALENT GATE RESISTANCE (RGJ'tO KA
EQUIVALENT GATE VOLTAGE ('o'5};<10 V
r;m
:i-!
'0 i. EQUIVALENT GATE ~~SISTA~.~~ ,(.~~l'IO ~.~.1m
,:::1"1+,11'1:: :" ,.. , "" ,E:;;::;
.tBj?~'·!ii!ii • . • ·• • • •
C·O.22 "F,R-2 MO
FROM SUPPL't TO
ANODE
.1
§ to c-_coo pF, R-2 MQ
~ : : . •r:tt. ?:. r~::~:l;± l.:;
FROM SUPPLY TO
ANODE.
:;:.,.A'.
to 20 ]0 o 5 W 15 W ~
ANODE SUPPLY VOLTAGE (VAAl-v [Link] GATE-SOURCE VOLTAGE (VsI-V [Link] GATE-SOURCE VOLTAGE (VSI-V
-~5 -25 b a's 50 75 IJo 125
-50
AMBIE"'T TEMPERATURE (TA)-"C
Fig. 13 - Peak output voltage 1f8. anode wppl'l lIo1fl11/f1 for Fig. 74 - Peak-point curTtlnt ..... fIII~sourcll "fIIMl/fland ambiflt1t
.at (PUT). Fig. 15 - Va/my-point current n. fIII • •ource voltage for
temPfl,([Link]'V for 07 (PUT). 01 (PUT).
----------------------------________________________~___________ 195
CA3097E
20V
(!}'-+-oVO
'.81111
Fig. 22 - Gentlfll' /IIJOdrJ chllnICtNin/cs toT 01 (PUT).
VAK
VRXM IRXM
I I
WITH SWI [Link]. INC'EASE VS'UNTIL SC;:=-FIRES IVTVM DROPS
-:::::i;1;;;;;;~I-:f=lF
•O=,.=I~- vAK APPLIED
FROM 10V TO "PPROXI .. ATELY IV I. tGS (TRIGGER 1IS MEASURED
JUST .!B.!Q! TO THIS TRIGGERING POINT. NOTE TH ..T IGS ....Y
V OXM
ElCPONENTlAI.; DECREASE AS Vs IS INCREASED DUE TO CURRENT DRAWN OUT
CONDITIONS: [Link] OF THE GATE TER..INAL. OF THt SCR AS IT TURNS ott. TO UNLATCH
RGK"I KQ THE SCR OPEN 5WI. •
TA"25·C
*"s 5t4OULO BE CAPABLE OF SUfJPLYIHG [Link].T INCREMENTS
NEAR THE TRIGGER POINT
Fig. 24 - hincipls WJIt11ge-cummt c/laractNistics Fig. 25 - OIIflnition of crifiu/,.,. of,istI of Fi,. 26 - Talt cin:uit fo, .,ermlnln,
fOl'02(SCR). off.,tlltII voJrap ftK 02 (SCR). 'GSin Q2 (SCRI.
APPLICATIONS CIRCUITS
1200
120V
'0",
'oon
L~ __ J
TVPICAL TEMPERATURE CM"RACTERISTIC
!:.UBSTRATE (i) RL. '330{to.~. IOO-![Link]""4'·C
TIIIII"G PERIOD ..... 200 SEC. WITH I MQ POT CENTERED TVP LOAD R£[Link]@I L .OT040m",16Yo/VoI_100.
TIMING CYCL.E BEGINS WHEN AC 'S APf"UEO -3'"4 (NO [Link] FULL LO.. OI
• SPRAGUE TVPE 4308, 51'F AT 50 V
SPRAGUE TYPE 6308, 'SI'F AT 50 V
OR EDUIVALENT
Fig. 27 - AC'lIne,opMIttKI olllt-shot timer.
[Link] RATE ADJUSTED BV VARYING RTOR CT'
OUTPUT PULSE WIDTH ADJUSTED av RIC.
OI~FERENTIATING TINE CONsTANT
TVPICAL. OPERATION FOR:
v+. 15 V. C,..O.I ~F, AT·4 3KO nCM-21929
CI :8ZpF, RI"60Kll
Fig. 29 - Pu_ gener"rot".
________________________________________________________________ 197
CA3098 Types
Programmable Schmitt Trigger Features: • Built-in hysteresis: 20 mV
max.
• Programmable operating
- With Memory current . • Programmable hysteresis:
20 mVto V+
-Dual-I nput Precision Level Detectors • Micropower standby dissi- • Dual reference input
pation
• Direct control of currents up • High sensor range: 100 0
Applications: to 150 mA to 100MO
• Control of relays, heaters, LED's lamps, • Low input on/off current of • Stable predictable Switching
photo-sensitive devices, thyristors, levels
less than 1 nA for pro· • Temperature-i:Ompensated
solenoids, etc. grammable bias current reference voltege
• Signal reconditioning of1 /lA
• Power can be strobed off
• Phase and frequency modulators via term. 2
• Onloff motor switching
• Schmitt tri ggers, level detectors
• Time delays
• Overvoltege, overcurrent, overtemperature
protection
• Battery-operated equipment 2 PROGRAMMABLE
BIAS CURRENT
• Square and triangular-wave generators INPUT (IalAsi
OUTPUT
The RCA·CA3098 Programmable Schmitt CURRENT
CONTROL
Trigger is a monolithic silicon integrated
circuit designed to control high·operating·
•
current loads such as thyristors, lamps,
relays, etc. The CA3098 can be operated
SIGNAL. INPUT
with either a single power supply with
maximum operating voltage of 16 volts, or a
dual power supply with maximum operating
voltage of ±8 volts. It can directly control
L __~A~
L ____ -----J
__ __.J
I
currents up to 150 mA and operates with
microwatt standby power dissipation when
y-
the current to be controlled is less than
30 mAo The CA3098 contains the following Fig. 1 - Block diagram of CA3098 programmable Schmitt trigger.
major circuit·function features (see Fig. 1):
1. Differential amplifiers and summer: the
circuit uses two differential amplifiers, Maximum Ratings, Absolute-Maximum Values at TA = 2!t'C:
one to compare the input voltage with Supply Voltage Between Terminals 6 and 4, ............................ 16 V
the "high" reference, and the other to Output Voltage Between Terminals 7 and 4, and 3 and 4 ................... 16 V
compare the input with the "low" refer· Differential Input Voltage Between Terminals 8 and 1, and
ence. The resultent output of the differ· Terminals 7 and 8 .............................................. 10 V
ential amplifiers actuates a summer cir· Operating Voltage Range:
cuit which delivers a trigger that initio Term.8 ....................................•................. V-to V+
ates a change in state of a flip·flop. Term. 7 .............................................. (V- plus 2.0 V) to V+
2. Flip-flop: the flip·flop functions as a Term. 1 ........................................... (V-) to (V+ minus 2.0 V)
bistable "memory" element that changes Load Current (Term. 3) ........................................... 150 mA
state in response to each trigger command Input Current to Voltage. Regulator (Term. 5) ......................... . 25 mA
Programmable Bias Current (Term. 2) ........................... ' ..... . mA
3. Driver and otuput stages: these steges Output Current Control (Term. 5) .................................. . 15 mA
permit the circuit to "sink" maximum Power Dissipation:
peak load currents up to 150 mA at Without Heat Sink:
terminal 3. Up to T A = 55D C
4. Programmable operating current: the cir· CA3098S, CA3098T ......................................... 630 mW
cuit incorporates access at terminal 2 to CA3098E . ... . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .. 630 mW
permit programming the desired quiescent Above TA = 55DC Derate linearly at ............................. 6.67 mWI"C
operating current and performance para· With Heat Sink:
meters. Up to T A = 55D C
CA3098S, CA3098T ......................................... 1.6 W
The CA3098 is supplied in the 8-lead dual·in·
Above TA = 55DC
line plastic packagej("Mini·Dip", E suffix),
CA3098S, CA3098T Derate linearly at ........................... 16.67 mWI"C
8-lead TO-5 style package (T suffix), 8·lead
Ambient Temperature Range (All Packages):
TO·S-style package with formed leads "OIL·
CAN" (Ssuffix), and in chip form (H suffix). Operating .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55 to + 125 DC
Storage ................................................... -65 to +150 DC
For information on another RCA Dual-Input Lead Temperature (During Soldering):
Precision Level Detector, see the data bulletin At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm)
for the RCA-CA3099E, File No. 620. from case for 10 seconds max. ................................ 265 DC
______________-----------------------------------------------------199
CA3098 Types
ELECTRICAL CHARACTERISTICS at T A = 25°C Unless Otherwise Specified 1.4 AMBIENT TEMPERATURE ITAI.2S·C
:> =~:M:J~~~~~;~:~~NT 118145)-IOOp'"
CHARACTERISTIC TEST CONDITIONS
Fig. LIMITS,
UNITS ~ L2 /
No. Min. Typ. Max.
~ 1r-+-~~+I/+-~4-rH
Input Offset Voltage:
VLR= Gnd, VHR = 3V
i ~·I---j---+-HHf--H-+-+-+-j
"Low" Ref., VIO(LR) 5 -15 -3 6 mV ~ ~~-+---+-~~--~-~~-+4
IBIAS = 100 IlA ~
~ 1/
VHR = Gnd, VLR = -3 V 5 o.4~-+---+v-'I'-1H--~-~~-+4
"High" Ref., VIO(HR) 6 -10 ±10 10
IBIAS = 100 Ilf/. ~ o21--f-::;.,....Q-HH--I--+-+-+-j
§ Vr-'
Temp. Coeff:
10 6 '.boo
"Low" Ref. -55°C to + 125 DC 7 - 4.5 - IlV;"C
'00
OUTPUT SINI( CURRENT IILOA01-I\fIA
"High" Ref. -55°Cto+ 125°C S - ±S.2 - Fig. 11 - Output saturation tloltage lIS. output
Min. Hysteresis VREG = 6 V, V+ = 12 V sink current:
Voltage VIO(HR-LR):
9 - 3 20 mV
IBIAS = 100 IlA
Temp. Coeff. -55°C to + 125°C 10 - 6.7 - IlV;"C
i
SUPPL'I' VOLTAGE IV+'-IOV
PROGRAMMING BIAS, CURRENT I1BIo\S '.100,.0\
Output Saturation Voltage, VI =4 V, VREG = 6V,
11,12 - 0.72 1.2 V Y
VCE(SAT) V+ = 12 V, IBIAS= lOOIlA ~I
W
Total Supply Current, ~""
g
ITOTAL: ~0.8
"ON"
VI = 4 V, VREG = 6 V;
V+ = 12 V, IBIAS = 100llA
13,14 500 710 SOO IlA s
~ Q7
VI-SV,VREG=6V
"OFF" 400 560 750 IlA
V+= 12V,ISIAS= 100llA
-100 -75 -50 -25 25 50 75 100 125
Input Bias Current, liS: AMBIENT TEMPERATURE ITAI-"C 92CS-20980
VI = 4 V, VREG = 6 V Fig. '2 - Output sa,turation voltage ambient
IB(p.n.p) V+= 12V,ISIAS= 100llA
15 - 42 100 nA
, temperature.
lIS.
VI = S V, VREG =. 6V
IB(n-p-n)
V+= 12V,IBIAS= lOOIlA
- 2S 100 nA
Output Leakage Current, Current from Term. 3 when
ICE(OFF) Q46is "OFF"
- - - 10 IlA
Switching Times:
Delay, td IC = lOOIlA - 600 - ns
Fall, tf IBIAS= 100llA - 50 - ns
18
Rise, tr V+= 5V - 500 - ns
Storage, ts VREG = 2.5 V - 4.5 - lIS 2 .. 6 810 2 .. 6 ,'I K) 2 .. 6 81000
Output Current, 10 V+= 12V,IBIAS=50IlA
- 100 - - mA
PROGRAMMING BIASCURRENT(IBIASl-".A
Fig. '3 - Total supply current tis. programming
bias current.
.. I'~ • AMBIENT TEMPERATURE CTA • S-
•~:~txT~~L~e~~Lyv:t;L'1A~tv..
e
PROGRAMMING BIASTc:.~~~T ~~,?S~:I~".:~ ~
Hf H::;+ '!~: ::::
·
I I ••
. , '6. IJ~,.'·'/I I I "?': V
.. ..== ==1-"".',.,
i
tr •
....
...
10
,/
I '7,c:: '""
. ·•,
u 1
!2
ii
4
~
:~
mf~
... +- tH' "t ,ttt
..
• Ht ;:1
tiL , . .. , . ..
!E
0.1
10 100
PROGRAMMING BIAS CURRENT (I8IAS)-~A
, 4 II
1000
Fig. 14 - Tota' supply current VB. ambient Fig. 15 - Input bia, current VI. programming bias Fig. 16 - Input·offset voltage
temptN'ature. CUf1'8nt. rest Circuit.
____________________________________.__________________________________ 201
CA3099E
Programmable Comparator - - With Memory POSITIV£SUPPLY
[Link]£FOft
CONSTANT-
CURR£NT8IA$ v'
RCA·CA3099E Programmable Comparator is a monolithic
silicon integrated circuit designed to control high·operating-
current loads such as thyristors, lamps, relavs. etc. The SOURC£OFRfF£A£I\ICE
CA3099E can be operated with either a single power supply "o~u.G£ I"Vb,,!I II
with maximum operating voltage of 16 volts. or a dual
power supply with a maximum operating voltage of ± 8 Volts.
Jt can directlv control currents up to 150 rnA. It operates with
microwatt standby· power dissipation when the current 10 be
controlled is less than 30 rnA. The CA3099E contains the
following six (61 major circuit-function features (Figure 11:
1. Differential amplifiers and summer; the circuit uses two
differential ampl ifiers. one to compare the input yoltage
with the "high" reference, and the other to compare the
input with the "low" reference. The resultant output of
the differential amplifiers actuates a summer circuit
which delivers a trigger that initiates a change in state of
a flip-flop.
2. Flip-flop; the flip-flop functions as a bistable "memory"
element that changes state in response to each trigger
UNIIElo,n.~~ED
.
"\'u1./h.\JfD
command.
Fig. , -Block diagram of CA3099E progrllfJll1Hlbl. [Link].
3. Driver and output ltages: these stages permit'the circuit to is..". 3 for (leIltll'M dercriptlon Df circuit [Link].)
"sink" maximum peak load currents up to 150 mA at
terminal 3.
4, Programmabla operating current; the circuit incorporates
a separate terminal to permit programming the desired
quiescent operating current and performance parameters.
5. Internal sources of reference voltage and programmable Features: Applications:
bias current; an integral circuit supplies a temperature-
• Programmable operating current • Control of relays, heaters, LEO's, lan,ps,
compensated reference \loltage IVb/21 which is about 1/2 • Micro-power stlndby dissipation photo-sensitive devices, thyristol'l,
of the externally applied bias \loltage (Vb), Additionally, • Directly controls current up to 160 mA solenoids, etc.
integral circuitry can optionally be used to supply an • Low input onloff current of leIS than 1 nA • Signal reconditioning
uncompensated constant-current source of bi8$ (lbias). for programmable bias current of 1 tJA. • Phase and frequlncy modulators
• Built·in Ilysteresis: 10 mV ma:K. • Onloff motor switching
6. Voltage regulator; provides optional on-chip \loltage regu· • Programmable hysteresis: 10 mV to v+ • Schmitt trlggel'l, level detecton
lation when power for the CA3099E is provided by an • Dual reference input • Time deleys
unregulated supplv. • High sensor range: 100 n to 100 Mn • avlrvoltage. cwercurrent,
• Suble predictable switching levels overtemperature protaction
• Temperature-compens8ted reference • Battllry-opara'btd equipment
voltage • Square end triangular-wave generators
ELECTRICAL CHARACTERISTICS AT TA = 25"C (Unless otherwire indicated)
Mtximum Retin... AbsoJute-Msxl,,!um ValutJl.t TA .. 2SOC:
SupplV Voltage Between Terminals 10 and 4,
9 and 4, 8 and 4
Output Voltage Setween Terminals 7 and 4,
,.,. V
CHARACTERISTICS
Referent;eVoltage
Referent;e Voltage
SYMBOL
VREF
TEST CONDITIONS
TA • 250C Un...
OtMrwi_ IndicMed
Term. 9 = 12 V, Term.4 = Gfd, Term.1' = Test
FIG. No.
LIMITS
MIN. TYP. MAX.
5.7
• ..3
UNIT
V
and 3and 4. V 100 JNloC
Differential Input Voltage Setween Temperature Coefficient
Tllt'minals 14 and " and Terminals 13and 14. 10 V Regulated Supplv Voltage VREG Term.5 1 K to 12V. Term.4 = Grd, Term.610KtoGrd 7.2 V
Operating Voltage Range:
Tllt'm.14 Regulated Supplv Voltage
OVtoV+ 2.• my/aC
Temperature CoeffiCient
Term. 13 2.0 V to V+
Term. 1 aV to V+ mmus2.0 V Input Qffset Voltage:
Load Current (Term. 3). 150 mA
"Low" Reference VIO ILA) VLR = Grd, VHR = 3 V. ISlAS = l00JJP, 20,6 -8 -3
mV
Input Current to Voltage Regulator (Term. 5) 25 mA "High" Referent;e VIO (HAl VHR = Grd, VLR = 3V,~BIAS= 1DOpA 20.7 ±1
Programming Bias Current (Term. 2) . 1 mA
Output CUrrent Control (Term. 71. "Low" Reference Temp.
15 mA CoeffiCient -55OC 10 .1250 C 20•• 4.' 20
Power Dissipation: /NI"C
UptoTA=550C. "High" Aeference Temp
Above T A '" 55°C. Derate Lmearlyat
750
6.67
mW
mW/oC
CoeffiCient -550C to +125aC 20 •• - "'.2 >20
Ambient Temperature Aange: Min. Hvstere51s Voltage VIOIHR-LR,
Operatmg VREG" 6 V. V· = 12 V, 'BIAS = tDO~A 21,10 10 mV
-55 to +125 °c
Storage. -65 to +150 o C Min. Hvstere5's Voltage _S5oC to t1250C 11 6.7 20 IN/0C '
Lead Termperature lOuring Soldermg): Temperature Coefficient
At distance not less than 1/32 Inch (0.79 mml Output Saturation Voltage VCEISATI V,-4V. "REG'" 8 V, y+ '" 12 Y,ISIAS" 100~ 21,12,13 - 0.72 1.2 V
from seating plane for 10 s maximum
>2" DC
Total Supplv Current"
V, - 4 V, VREG = 8 Y, y+ '" 12 V, 'SIAS. = 100SiA
'TOTAL "ON" 21,14,15 600 710 BOO
ITOTAL jJA
'TOTAL "OFF" VI-S.Y, VREG" 6Y, V+ "12V,IBIAS = tOO~ 21,14.15 420 560 760
InputSlas Current:
IBIp..n·pl VI = 4 V; VREG '" 6 V. V+ "12 V, ISlAS '" l00~ 21,16,17 33 200
lui nA
ISlnop-n1 VI"8 V. VREG = 6 Y, y+ .. 12 V, 'SIAS -tDOpA 21,16,17 20 60
OutPUt Leakage Current ICEtOFFI Current from Term.3 when 046 is "OFF" 10
Internal Bias Current IIBC IB,19 120 200 280 jJA
Switching Times:
Delav
Fall
Rise
'. Ie" l00)JA
ISlAS" 1001JA
v+ "'5V
22
22
22
600
60
600
VREG = 2.5 V
Starage 22 4.6 pS
"
203
CA3099E
=t 4 ~N:~~~: ;~~::::~~~~ ~TI~ ~ 25"C
t1 ·.~I:::~~FF~~~:~ :~t~::~ (f~~~II::~
; '.~-+4+r-~~~~~~~~
~ 2~~~~~~~--~r+t-r+--t-rt1
g ~V
~
~ I
~
..
i
25 50 lS 100 I~ 10 4 II 1 100 4 II '1000
PROGRAMMING liAS CURRENT tlltASI-,.A
AMIIENT TEMPERATURE (TA!--C UCS-20!H9
92CS-20914
FIg. 9 - Input-offHt IIOIt.,. ("high" reference} v.t. ambient Fig. to - Min. hV$[Link] volt",. n. progrllmming bill' curr"",.
ttnn",,"ture.
:r
r'
AMBIENT TEMPERATUR£ (TA'-U·C
:=~:~~~~~=~~T ClBlAS!·IOO~A
I
i, I ='::;';;;:",~ ,'- 4 REGULATED SUPPLY VOLTAGE tVR£GI-' v
~ '~+-~~~I+-/+-~~
i M'r---+_--_t~~_H~_i----+__t_r1
!
~!
Mir_--~--+_~4Il_--+_--~_i_t1
O.4r_--~--+/-,t'+~----t----t-++-l JI~
l
§
~r_--~~~_i__t_t--__t----~~+_l
V
,
10 100 & • lboo A....NT TEMPERATURE 1f,.1-"C 9ZC$-ZOHO
10 100
... 1000
PROGRAMMING liAS CURRENT (1 8IASI-p.A IlCS- 20913
OUTPUT SINK CURRENT ClLOACI-ftlA
Fig. 12 - Output SIIturlItion IIOItll(Jll If$. output .tlnk cur"",t• Fi,. 13 - Output Slltu,.t/on IIOIt"". .... I!IIrIbitInt ,."".,lItul'&
. .. '0
PIIIOGRAMMING
. .. '00
liAS CURRENT CIIIASI-,..A
. .. '000 SUPPLY VOLTAII: (V+I-V
FI,. 16 _ In",""" billS CUffllftt VI. IUpply voItIIfI&.
Fig. '6· 'nputbiMcurrtl"t .... fJI'Of1'I!Immintlbiucu',.",. FIll- t'-ln,.",.blMcu".",n.""""""""",tcnw.
V+
.IV
~~
I I
V
I I
0I:L
:I J
I
:
~TD+i I.~
I I "I
HYSTERESIS VOLTAGE -VI "oFF"-VI 'bN" ....Tf I- rTsij I
9ZC$-20994 41 T , .-
FIg. 18 -Input-off.t voItIJIII tart circuit. F~ '9 - Min. hyltere,ti.r voItll(Jll. tot. supply current,
IIIId input bills cur""'t ttl6t circuit. FIJ. 20 - Switching tlnw test cin:uit.
For application information, see Data Bulletin File No. 620.
-----------------------------------------------------------------205
CA31 00 Types
ELECTRICAL CHARACTERISTICS, At TA = 25"C: TYPICAL CHARACTERISTIC CURVES (Cont'd)
LIMITS
TEST CONDITIONS
CHARACTERISTICS SUPPLY VOLTAGE (V+,V-)-15 V UNITS
UNLESS OTHERWISE SPECIFIED MIN. TYP. MAX.
STATIC
Input Offset Voltage, VIO VO=O±O.l V - ±1 ±S mV
Input Bias Current, 'IB - 0.7 2 /JA
Vo = 0 ± 1 V
Input Offset Current, 110 - ±0.C5 ±OA /JA
Low·Frequency Open-Loop Vo = ± 1 V Peak, F = 1 kHz - dB
Voltage Gain,AOL. 56 61
Common-Mode I "put, + 14
CMRR :;:'76 dB ±12 - V
Voltage Range, VieR -13
Common-Mode
Rejection Ratio. CMRR VI Common Mode'" ± 12 V 76 90 - dB
fREQUENCY (O-MHz
Maximum Output Voltage:
Positive, VOM + Differential Input Voltage:;:: 0 ± 0.1 V +9 +11 - Fig. 4 - Open-loop gain vs. frequency and supply
V voltage.
Negative, VOM - RL = 2 KH -9 -11 -
Maximum OutPllt Current: AMBIENT TaPERATURE ITA'-ZS"C
LOAD RESISTANCE IAL,"ZIUl
Positive.'OM+ Differential I nput Voltage = 0 ± 0.1 V +15 +30 - mA
LOAD CAPACITANCE tCL"20pf
Negative. 10M RL" 250 H -15 -30 -
Supply Current,t+ Vo ~ a to.l V, RL210KH - 8.5 10.5 mA
Power-Supply
Rejection RatiO, PSRR
l1V+:::; t lv.6v-~t 1 V 60 70 - dB
DYNAMIC
Unity-Gain
Crossover Frequency, fT
Cc = 0, Vo = 0.3 V (p.P) - 38 - MHz
1-MHz Open-Loop
Voltage Gain, AOL
1 = 1 MHz, Cc =O. Vo = 10 V (P·P) 36 42 - dB
10 20
NONINVERTING GAIN-de
Slew Rate, SR: o 6 19.1
INVERTING GAIN - dB
20-dB Amplifier AV = 10, CC= 0, VI =1 V (Pulse) 50 70 - CLOSED-LOOP GAIN {ACLI-dB
V/jJs
Follower Mode AV = I, Cc = 10 pF, VI = 10 V (Pulse - 25 Fig. 5 - Required compensation capacitance tis.
~
closed-loop gain.
Power Bandwidth, PBw&:
20-d8 Amplifier AV= la, Cc' 0, Vo = 18 V (P·P) 0.8 1.2 -
MHz
Follower Mode AV= l,Cc s 10pF, Vo -lBV (P·P) - 0.4 -
Open-Loop Differential
Input Impedance, Z,
F = 1 MHz - 30 - Kn
Open-Loop
F = 1 MHz - 110 - n
Output Impedance, Zo
Wideband Noise Voltage Re-
terred to Input, eN(Total) BW = 1 MHz, RS = 1 Kil - 8 - jJVRMS
Settling Time. ts
[TO Within ± 50 mV 01 9 V RL =2 KH, CL = 20 pF - 0.6 - jJs
Output Swing
COMPENSATION CAPACITANCE (CC' PINS I TO e - p f
.. Power Bandwidth = Slew Rate • Low-frequency dynamic characteristic
nVO (p·P)
Fig. 6 - Slew rate vs. compensation capacitance.
,,. AMBIENT TEMPERATURE ITA"2S"C
SUPPlY VOLTAGE (V~V-':15 V
30 AMBIENT TEMPERATURE (TA'.2S"C
BANDWOTH (BW) AT 6de-IMHr ~><1 SLPPLY
AMBIENT TEMPERATIJRE ITAI-ZS"C
VOLTAGE 1'1+, v-l-ISV'
~ 4 r- ,---
~---
.i ,-
~
- .'~,
i"-.,
f". .-
~
~
7+I!5V' HEWLETT
I-oy '-...
-
2
CA3~~~!~CE
,
"0
S
-115'1
I
..s:..
METER 4BI5A
- I
is
10:
,
t-....
:-... ---
'-...
10
AOJUST fOR
Vo~OtO.l
20
VDC
FREQUENCY (fI-MHI
'30 40
102 ~ e 10"
SOURCE RESISTANCE IRsl-n
, e 104
I~
* -'""',
1 1
,"
fREQUENCY (f1-MHI
~
_.
t-....
"'"
Fig. 7 - Typical open-loop output impedance tis. Fig. 8 - Wideband input noise voltage vs. source Fig. 9 - Typical open-loop difffJrential input
frequency. resistance. impedance tis. frequency.
___________________________________________________________________ 207
CA31 00 Types
TYPICAL APPLICATIONS
3dB BANOWIDTH '15 MHz
CLG'20dB
INPUT
~¥ OUTPUT TO
TERMINATED
,on
TRANSMISSION
LINE
-3dB 8ANDWIOTH~20~HI
TOTAL INPUT NOISE
IMHz BIf
VOLTAGE REFERRED TO INPUT
2MHI !5V
::<35 .. vRMS 4MHI 2 II
", "
Fig. 21 - 20 dB video amplifier. Fig. 22 - 20 dB video line driver.
INPUT IMPEDANCE
:::<!50Kn
TEST
Vr(AC) LEADS
ImA FULL
SCALE OC
METER
=-FULL SCALE
CALIBRATION
ADJUST
Fig. 23 - Fast positive peak detector. Fig. 24 - 1 MHz meter-driver amplifier.
Chip Dimensions and Pad Layout
The photographs and dimensions represent a chip
when it is part of the wafer. When the wafer is cut
into chips, the cleavage. angles are 57° instead of
90° with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0.17 mm) larger
in both dimensions.
Dimensions in parentheses are in millimeters and
are derived from the basic inch dimensions as in·
dicated. Grid graduations are in mils (1()""-3 inch).
CA3100H Chip
______________________________________________________________________ 209
CA3118, CA3146, CA3183 Types
COMPARISON OF RELATEO PREOECESSOR TYPE WITH TYPES IN THfs DATA BULLETIN TYPICAL STATIC CHARACTERISTICS CURVES-
DATA
VCEO VCBO Cca CCI CEa CA3118 and CA3146 SERIES (cont'd Fig.2 to 12)
FILE
min. min. typo pF typo pF typo pF eASE CURRENT (:lel-O
NO.
CA30l8 338 15 20 0.23 0.715 60 0.58 2.8 O.G
CA3D18A 338 15 20 0.23 0.715 50 0.58 2.8 O.G
CA3118AT 40 60 0.33 0.730 50 0.37 2.2 0.7
CA3118T 30 40 0.33 0.730 50 0.37 2.2 0.7
le·l0mA IC-lmA
CA3046 341 15 20 0.23 0.715 50 0.58 2.8 O.G
CA3146AE 40 50 0.33 0.730 50 0.37 2.2 0.7
CA3146E 30 40 0.33 0.130 50 0.37 2.2 0.7
Ic"5QmA le-lOmA
CA3083 481 15 20 0.4 0.74 100
CA3183AE 40 60 1.7 0.75 75
CA3183E 30 40 1.7 0.75 75
STATIC ELECTRICAL CHARACTERISTICS - CA3118 and CA3146Serie.
TEST CONDITIONS LIMITS
I
CA3118AT, CA3146AE CA3118T. CA3148E
,.,
CHARACTERISTICS SYMBOL UNITS '" ,.
AMBIENT TEMPERATURE ITAI-·C
Min. Typ. Max. Min. Typ. Max. Fig.2- I CEO", TAforanytransistor. I
For Elldl Transistor: EMITTER CURR£NT II 1·0
Collector-ta-Base
VIBRICBO Ie'" 10JLA. Ie = 0 50 72 40 72
Breakdown Voltage
Collector-la-Emitter
Breakdown Voltage V(BRICEO Ie = 1mA, IS • 0 40 56 30 56 v
Collecto(-to-$ub$lrate lei = IOIotA, IS .. 0
V(BRICIO 50 72 40 72 v
Breakdown Voltage Ie = 0
Emitter-to-Base
VIBRIEBO Ie '" 10~A. Ie = a v
Breakdown Voltage
Collector-Cutoff Current ICEO VCE '" 10V, IS '" 0
Collector-Cutoff Current ICBO VCS = 10V, IE "'0 0.002 100 0.002 100 oA
85 85
DC Forward-Current
Transfer Ratio -FE Vce=5V IC"" mA 30 100 30 100
Ic"'OIlA 90 90
aase-to-Emitter Voltage
Collector-to-Emitter
Saturation Voltage
V8E
VCEsat
VCE = 3V, IC = 1 mA
IC: lOrnA, la = 1 mA
0.63 0.73
0.33
0.83 0.63 0.73
0.33
0.83 v
v , . AMBIENT TEMPERATURE (TA 1--<:
'00
".
For transistors 03 and Q4 [Link] COnf....donl:
Collector-Cutoff
Current
1 CA31l8AT
and
Iceo VCE = 10V, la" a
Fig. 3 - I CSO vs. TA for any transistor.
COLLECTOR-TO-[MITTER VOLTAGE (VcEI-5 V
DC Forward-Current CA311BT f--t-------j--+--+---j--+--+---t---j j 180
AllaIENT T£MPERATURE IT Al -12!5"C
Transfer Ratio only -FE VCE '" SV, IC = 1 rnA 1500 9000 1500 BOOO
i 140
Base-fa-Emitter
VBE
VCE =5V Ie = lamA
Ie "'lmA
1.46
1.32
1.46
1.32
v ffi 120 II "-
~.lc
(031004)
100
Magnitude of Base-to-
Emitter Temperature
I I
"V8E
"T
VCE =5V, Ie '" 1mA 4.4 4.4
; eo - II r--
-
Coefficient
For trantistors Q1 Mel 02 lAS. Differential Amplifier):
i &0 Jl
1.0 II
... . . .. . . ...
Magnitude of Input
Offset Voltage
IVaEl • VBE21
Vce = SV, tE = 1 mA 0.48 0.48 mV ~--"
, II
0.'
Magnitude of
hFE Ratio
I CA3118A T WId
CA311BTonly
VCE '" SV,
ICI = IC2" 1mA
0.9 1.0 0.9 1.0 1.1
COLLECTOR CURRENT (Iel-IIIA
10
Fig. [Link]",ytrsnsistor.1
Magnitude of Base-to-
VCE = SV. COLLECTOR-TO-EMITTER VOLTAGE IVCEIK!lV
Emitter Temperature 1.9
Ie: 1 rnA
Coefficient
Magnitude of VIO
VeE = SV, 0.9
(Vue 1 - VBE2) Temp- 1.1
ICI "IC2" I rnA
erature COefficient
1 CA3148AE
ne
"'.
Magnitude of
InpulOffset VeE :SV,
110 0.3 0.3 0.1
Current . CA3146E IC,·tC2'" 1 rnA
1',0'.',021 only
0.4
-75 -50 -20 0 25 50 15 100 In
AMBIENT TEMPERATURE (TAJ--C
82CS-IIS44
Fig. 5 - VSE vs. TA forany transistor.
___________________________________________________________________ 211
CA3118, CA3146, CA3183 Types
TYPICAL STATIC CHARACTERISTICS CURVES- TYPICAL DYNAMIC CHARACTERISTICS CURVES
CA3118 and CA3146 SERIES (Fig.2 to 12) (FOR ANY TRANSISTOR)-CA3118,CA3146 SERIES (Fig. 13 to 22)
t=:
.
I B COLLEClOR-TO-EMITTER VOLTAqE IVCE'o5V
<If : AMBIENT TEMPERATURE (TA'- 25"C
== COLLECTOR-TO-EMITTER VOLTS (\t£loSV COLLECTOR-TO-EMITTER VOLTS (VeE>- 5 v
,
[Link] RESISTANCE OHMS (Rs)'500 SOURCE RESISTANCE OHMS IAslolOOO
AMBIENT TEMPERATURE (TAl"25"C AMBIENT TEMPERATURE (TAI"25"C
~ '0 '0
a~2r--r--t-rrt--r--t-rrt--+--t-~
~ a'±=j=::$m$$$U=t2$/~ I.~i/ijr" ,. &~~
~
~.::!.:I- i
~ ]=r--r--t-rrt--+--t-rrb"t---t-1-t1 " v
~ .,.~,
~ ~ 2r--+--+-rr+--+/--bii"'l-+--+--+-1-t1 '0
r
~# fO 1
loJ i:Y '/
~O':~~m!
= :~
;:::-.. ./ V , v /
f-l9-~
-. ..
5
; :~~--+--+-+~--+--+-+~--+--+-+~ ----. . . ~ f-l!l-
00
0.01 2 " 6 '0.1 .. 6 8 I
COLLECTOR MILLIAMPERES tIel
4 6 8 10 , . .. ,
COLLECTOR MILLIAMPERES tIel
, . .. ,
COLLECTOR MILLIAMPERES IIel
Fig. 12 - 110 V$. IC (01 and 02) for types CA3146AE Fig. [Link]@Rs=500f!. Fig. [Link]@Rs=lkf!.
and CA3146E.
30 COLLE~TOR TO-EMITTER VOLTS (VeE'- 5 V
SOURCE RESISTANCE OHMS (R5'-I0000
AMBIENT TEMPERATURE {TA'-25-c
i 100 COLLECTOR-TO-EMITTER VOLTSIVCE )o5V COMMON-EMITTER CIRCUIT, BASE INPUT
, 20" v
~i4~+=~**~~~~~=t=+=t~=+~
~~ 3Or-+--++++-+-++l-l---....:o"'-+-I+r-+--I
1 . ./.
1,~J1
1
~ " (#;B"
/ ~ f20f--f--Htl-++++f--I-......-"1<.++f--H
~
~
'0
@.~"'~ l/ 8! ..~~~~++-I+~~~~+~
~;
~t or-+--=~~~~l!>.-.+-I-I-I--+-+-I+I-~'--I
,/'I-- V" V"""
i;_~-+--I-II-H--II--I-+f~~~-+~~~-I
0
5
"'"
, -. . . VI-"
0'
COlLECTOR MILLIAMPERES ([Link]
, . .. .,.00 " 180.1 46',
[Link] MILLIAMPERES IIel
"
I
68
10
.,
Fig.15-NFvs. 1e@Rs=IOkn.
1:t:'aeJ+-~~~R'A~lf;S~A~~I"P'1
COLLECTOR-TO-EMTTER VQ..TS (VcEI"3
COLLECTOR NILLIAMPERESII I-I
~ ~ ol--+---+-++J,tre ~E:~;A:T~~:=:NCIES ~
-3
J~ • bo. ~i
p'
til ~~-O'.5f--f--f-f-H-+·-+--H+"-"'If---1
5~ 3 ,~~1--+-++++-+-++t+--+---1
!~
~~ 2 11-'1--+---1-+++-+--++++-+--1
ail , ...
L ~~ -I .. of---f--f-++t--+--+++t---+---I
., 468
,
2 "68
FREQUENCY (fI-MH!
'0
... '00
~
0.1
, ." , , .FREOUENCYlfl-NHz
.
./
, . ~i
10 2
FREQUENCY(f}-MHz
8100
Fig. 18 - Yi. vs. f. Fig. 19- Yo. V£ f. Fig. 20- Yre "" f.
"':'::::1.·:. I T : ! '
800 '" :,:. ,:" :::: : : , , ' "" .
·······1''''''
:: ~~:: >:"
40~:~1 ::
:::11I,:':,
':' "::.1::
'00 ::::
........ .
'::: :":1,,' ':" ,. .
;::::::::::::::::::::""
BIAS VOLTAGE-V
COLLECTOR MLLIAMPERES IIcl
Fig. 21- 'T"" 10 Fig. 22- CEB. CCg. eelvs. bias voltage
__________________________________________________________________ 213
CA3127E
Features.'
High-Frequency N-P-N
- Gain-Bandwidth Product (fT) > 1 GHz
Transistor Array - Power Gain = 30 dB (typ.) at 100 MHz
For Low-Power Applications at Frequencies up to - Noise Figure = 3.5 dB (typ.) at 100 MHz
- Five independent transistors on a common substrate
500 MHz
RCA-CA3127E* consists of five general-
purpose silicon n-p-n transistors on a common Applications:
monolithic substrate. Each of the completely - VHF amplifiers - VHF mixers
isolated transistors exhibits low 1 If noise and
a value of fT in excess of 1- GHz, making the - Multifunction combinations- - I F Converter
CA3127E useful from de to 500 MHz. RF/mixer/oscillator - IF amplifiers
Access is provided to each of the terminals - Sense amplifiers - Synthesizers
for the individual transistors and a separate - Synchronous detectors - Cascade
substrate connection has been provided for amplifiers
maximum application flexibility. The mono-
lithic construction of the CA3127E provides 92CS-22214
close electrical and thermal matching of the Fig. 7 - Schematic diagram of CA3127E.
five transistors.
The CI\3127E is supplied ,n a 16-lead dual-in-
line plastic package and operates over the full STATIC ELECTRICAL CHARACTERISTICS at TA = 25°C
military temperature range of -55 to +125"C. LIMITS
CHARACTERISTICS TEST CONDITIONS UNITS
* Formerly RCA Dev. No. TA6206. Min_ Typ. Max_
MAXIMUM RATINGS, For Each Transistor:
Absolute-Maximum Values:
Collector-to-Base
POWER DISSIPATION. Po:
Breakdown Voltage
IC= [Link],IE =0 20 32 - V
Anyone transistor. 85 mW
Total Package: 0 Collector-to-Emitter
For T A up to 75 C 425 mW Breakdown Voltage
IC=lmA,IB=O 15 24 - V
For T A >
75°C Derate
Collector-to-Substrate
Linearly at.
AMBIENT TEMPERATURE RANGE:
6.67 mW/oC
° Breakdown Voltage
ICl = [Link],IB=O, IE =0 20 60 - V
Operating . -[Link] +125 C Emitter-to-Base
Storage . . -65 to +12SoC
Breakdown Voltage*
IE = 10 [Link], IC = 0 4 5.7 - V
LEAD TEMPERATURE
lOURING SOLDERING): Collector-Cutoff-Current VCE = 10 V, IB = 0 - - 0.5 [Link]
At distance 1/16 ± 1/32 inch
11.59 ± 0.79 mm) from case
Collector-Cutoff-Current VCB = 10V,IE =0 - - 40 nA
for 10 seconds max. . +265 0 C IC=5 mA 35 88 -
DC Forward-Current -,
The [Link] apply for each transistor in Transfer Ratio VCE =,6V Ic=l,mA 40 90 -
the device:
. Collector-ta-Emitter Voltage, V CEO . · 15V
IC =0.1 rnA 35 85 -
Collector-ta-Base Voltage, VCBO . · 20 V Ic=5mA .0.71 0.81 0.91
Collector-ta-Substrate Voltage, VeIO· · 20V
Collector Current, Ie 20 mA Base-to-Emitter Voltage VCE = 6 V IC=l mA 0.66 0.76 0.86 V
*The collector of each transistor of the CA3127E
IC=O.l mA 0.60 0.70 0.80
is isolated from the substrate by an integral diode. Collector-to-Emitter
The substrate (terminal 5) must be connected to
Saturation Voltage
Ic=10mA,IB=lmA - 0.26 0.50 V
the most negative point in the external circuit to
maintain isolation between transistors and to Magnitude of Difference
provide for normal transistor action. in VBE
01 & 02 Matched - 0.5 5 mV
Magnitude of Difference
AMBIENT TEMP[MTWRE ITA)·2i5"C
COLLECTOR-TO-EMITTER 'IOLTAGE IVcE,·6V
in IB
VCE = 6 V, IC = 1 mA - 0.2 3 [Link]
30 RSCllRZ • .eo04 """-
T 2.
~
~
Vi--'
../
../
.....y
~
~l~
, ·When used as a zener for reference voltage. the device must not be subjected to more than 0.1 millijoule of
energy from any possible capacitance or electrostatic discharge in order to prevent degradation of the
junction. Maximum operating zener current should be less than 10 rnA.
,. V
5
/ ~~
...... 1---" ~
"" 1"'=
• • 'Go
100 11HZ...........
0.0'
"
COU,ECTOR CURRENT (lcl-illA
Fig_ 2 - 1If noise figure as a function of collector
current at RSOURCE = 500 11.
_____________________________________________________________________ 215
CA3127E
. . . .NT TEIIIPIItATUM: 1'Tf)-ZS"'C t. [Link] TEMPERATUM: IT.. I-2"(
,AIt: ''tEl·• ..,
.
[Link]-TO-Dntu . . 1.2 COLLECTOIt-TO-PlfTTtR VOLT....
\
IIg . • CClLLlCTOII CUMlNT lIeI.I .... (VeEI"V
,/ J 1.1 [Link] ClJRHNTtlcl-I." I
T
V ....
!
I
~u
'.0
•~
Ii Y ,/
•I
i=i ' iI .T T
/ ~ O. I
iH-
r: ./"
/'
/til
./ A 0.'..
~ .,.'I-~
./
.//
•I
-• I
~ ,L..--"'" •,
100 .. .
FIitEQUENCY In-IIIH.
, 1000
COLLECTOR CURRENT UC1-mA
[Link]--hz
'00 . . ...
saCS-1HZ'
Fig. 10 - Input admittance (Y ,,) as B function of fig. It - Input admittance (Y tt) as a function of Fig. 12 - Output admittance IY22) au function of
frequency. collector current. frequency.
100 S • 1"'1lOO
FREQUENCY tn-MHI
COLLECTOR CURRENTIICI-mA COLLECTOR CURRENTlIcI-IIIA
Fig. 13 - Output admittance I Y22}a$ a function of Fig. 14 - Forward transadmittance (Y21) au Fig. 15 - Forward transadmittance IY21} au
collector current. function of collector current. fUlJCtion of frequency.
,00 1 "1000 •
COLLECTOR CURRENT IIC1-ImA FREQUENCY ttl-MHJ
Fig. 16 - ReverBe transadmittance IY 12} as a Fig. 17 - Reverse transadmittance (Y 12) as a Fig. 18 - Voltage--gain test circuit using current-
function of collector current. function of frequency. mirror biasing for 02-
This circuit was chosen because it conveniently
represents a close approximation in performance to
a properly unilateralized single transistor of this
type. The use of Q3 in a current-mirror configu-
ration facilitates simplified biasing. The use of the
cascade circuit in no way implies that the tran-
,<-.--'......=-' 02 1
sistors cannot be used individually.
,
1
1
~60n
,
""n .
=1
O~:!TEr-_~-'-1.......<1Ir_ _ _.......'OO"'!!;o'
I ".n J:
~
I*
-1. E. F. JOHNSON NO) 160-104-1
OR EQUIVALENT
Fig. 20 - Block diagram, of power*fJBin and noise-
Fig. 19 - tOO-MHz power-gain and noise-figure test circuit. figure test sBt-upS.
________________________________________________________________ 217
CA3130, CA3130A, CA3130B Types
MAXIMUM RATINGS, Absolute-Maximum Values
rcMi5O'-------------------, '1+
II 2OOJ£A
'
DC SUPPLY VOLTAGE I
(Between v+ and V- Terminals) . . • . . • .. 16 V TEMPERATURE RANGE: I
DIFFERENTIAL-MODE OPERATING (all types) •.••• -55 to + 1250C I
INPUT VOLTAGE ••.....•.••...••.. ±S V STORAGE (all type" ..••..•• -66 to + 160~ I
COMMON-MODE DC I
OUTPUT SHORT-CIRCUIT
INPUT VOLTAGE •.. (V+ +8 V) to (V- -0.5 V) DURATION ~ . • . . • • • • . • . . INDEFINITE
INPUT-TERMINAL CURRENT ........• 1 mA LEAD TEMPERATURE
DEVICE DISSIPATION: (DURING SOLDERING):
WITHOUT HEAT SINK - AT DISTANCE 1/16 ± 1/32 INCH
UP TO 55°C ... . . • • • • . • • • . • • . .. 630 mW (1.59 ± 0.79 mm) FROM CASE
ABOVE 55°C •... Derate linearly 6.67 mWfDC FOR 10 SECONDS MAX. • • . • +265 oC
WITH HEAT SINK -
AT 125°C. •• . . . . •• . • • . •• . • • • .. 418 mW ·Short circuit may be applhkl to ground or to either
BELOW 125°C ... Derate linearly 16.7 mWfDC supply. OfFSfT
....L
TOTAL SUPPLY \IOlTAGE (!fOR INDICATED VOlTAGE GAINS)_" V
-WITH ',.UT TERMINALS BIASED SO THAT TERM. fj POTENTIAL
ELECTRICAL CHARACTERISTICS at TA-25oc, V+-15 V, V- - 0 V (Unle•• otherwi.. specified) ·=,;:~~::::~;:~:.~D"'VEN TO "'HER SU"" RAIL.
UCS·14715.
LIMITS
Fig. 3 - Block diagram of the CA3130 Serie•.
CHARACTERISTIC CA3130B (T,S)
Min_ Typ. Max.
CA3130A (T,S,E) CA3130 (T,S,E) Units
Min. Typ. Max. Min. Typ. Max . r;;..""m'j"T wiii"li..
I Ill..!
E
,~ SUPPLY .....,...'V·· .. v,V" ••
Input Offset Voltage,
- - r IT"' ..... ~ 13
- 0.8 2 2 5 8 15 mV
IVloI, V±=±7,5 V
Input Offset Current,
~
;;: eo
100
• ,...·~1I11
IIII +.L '00 I,
11101, V±=±7.5 V
- 0.5 10 - 0.5 20 - 0.5 30 pA
~ "'..... '{t 'l! ,"/,1 I --i
w 'c;;. '"!' '.l"!' 3
..t
~ eo
Input Current, II
V±=±7.5 V
- 5 20 - 5 30 - 5 50 pA j 1~:?' ·-1
'1,.. "
- - • ~~
large,Signal Voltage lOOk 320 k - 50 k 320k 50 k 320 k VIV
I I~ t4 ~
Gain, AOL
VO=10 V p _p ' RL =2 kn 100 110 - 94 110 - 94 110 - dB
~
20
~
II
I 111.1 Iq
NI,\11 ,
i
'0 ,0' ,0' ,.- ,m-
Common-Mode
Rejection [Link]
86 100 - 80 90 - 70 90 - dB FREQUENCY HI "" "CS-1471.
Common-Mode Input- -0.5 -0.5 -0.5
Voltage Range, VICR 0 to 10 0 to 10 0 to 10 V Fig. 4 - Open-loop 1I0/[Link] gain and phs.. ,hift
VI. frequency for _iOU8 ""'II1II of
12 12 12 CL , Co and RL •
Power·Supply Rejection
Ratio, /:"VIOI/:,.V± - 32 100 - 32 150 - 32 320 p.V/V ! 110 LOAD _'STANCE 'RL'. 2ItA Ij-
V±=±7.5 V
',140
J~
Maximum Output
Voltage:
VOM+ 12 13.3 - 12 13.3 - 12 13.3 - 1,20
At RL=2 kn
VOM-
VOM+ 14.99
0.002
15
0.Q1
-
-
14.99
0.002 0.Q1
15 -
-
14.99
0.002 0.01
15 -
V •i"·
At RL =00
0 0.Q1 0 0.Q1 0 0.Q1 ~, '00
VOM
Maximum Output I ..
Current: ~
·'00 ·so 0 so '00
IOM+ (Source) @ AMIIENT TEMPOATURE IT.I- oc" SlZeS-f..'!'I'!'
VO=OV 12 22 45 12 22 45 12 22 45 Fig. 6 - Open·/oop gain VI. temperature.
mA
IOM- (Sink) @
VO= 15V
Supply Current, I :
VO=7.5 V,RL = 00
12
-
20
10
45
15
12
-
20
10
45
15
12
-
20
10
45
15
.. I'
j'
I7.S
: II.S
:'::T~~=R~:.;;t:I~;.:I~••:~ ~
~~ ~~3
~
!1
I
II:·
Ii!
VO=OV, RL =00 - 2 3 - 2 3 - 2 3
mA
1,0 I~ \! 1:1 ' I,I
Input Current, II' - 15 - - - - nA !<ib 4 :'t
Fig.12 Fig.12 Fig.12 ~75 \;
Input Offset Voltage i
- - - i* • ,,,
Temp. Drift,
/:"VIO//:"T*
large-Signal Voltage 50 k
5
320 k
15
-
-
-
10
320 k
-
- -
10
320 k
p.V(OC
VIV
~ .. ,.
Gain, AOL * 94 110 - - 110 - - 110 - dB
0
0 ... • 7.' ".5 '0 17.'
QATE [Link]£IVGI (TEltMS 4. I)-V
20
t2CS~24'!'1
22.'
..
Fig. 6 - Volta!J8 transfer characteTlBtlcB of
COS/MaS output .tage.
____________________ ~ _____________________________________________ 219
CA3130, CA3130A, CA3130B Types
CIRCUIT DESCRIPTION PMOS transistors Q4 and 05 with respect to gate-protection diodes in the input circuit
Fig. 3 is a block diagram of the CA3130 Term. 7. A patential of about 2.2 volts is and, therefore, a function of the applied
Series COS/MOS Operational Amplifiers. The developed across diode-connected PMOS tran-
input terminals may be operated down to sistor 01 with respect to Term. 7 to provide
0.5 V below the negative supply rail, and the gate bias for PMOS transistors 02 and 03. It
output can be swung very close to either should be noted that Ql is "mirror-con-
supply rail in many applications. Conse· nected"t to both 02 and 03. Since tran-
quently, the CA3130 Series circuits are ideal sistors Ql, 02, 03 are designed to be iden-
for single·supply operation. Three Class A tical, the approximately 2QO-microampere
amplifier stages, having the individual gain current in 01 establishes a similar current in
capability and current consumption shown 02 and 03 as constant-current sources for
in Fig. 3, provide the total gain of the both the first and second amplifier stages,
CA3130. A biasing circuit provides two respectively.
potentials for common use in the first and
At total supply voltages somewhat less than
second stages. Term. 8 can be used both for 8.3 volts, zener diode ZI becomes non-
phase compensation and to strobe the output conductive and the potential, developed INPUT CURRENT eXT , - ,A
stage into quiescence. When Term. 8 is tied across series-connected Rl, 01-04, and 01. 92CS-290••
to the negative supply rail (Term. 4) by varies directly with variations in supply Fig. 1 1 - Input current VI. common-mode voltage.
mechanical or electrical means, the output voltage, Consequently, the gate bias for 04,
potential at Term. 6 essentially rises to the 05 and 02, 03 varies in accordance with voltage. Although the finite resistance of the
positive supply·rail potential at Term. 7. supply-voltage variations. This variation re- glass terminal-to-case insulator of the TO-5
This condition of essentially zero current sults in deterioration of the power-supply- package also contributes an increment of
drain in the output stage under the strobed rejection ratio (PSR R) at total supply volt- leakage current, there are useful compensa-
"OFF" condition can only be achieved when ages below 8.3 volts. Operation at total sup- ting factors. Because the gate-protection net-
the ohmic load resistance presented to the ply voltages below about 4.5 volts results in work functions as if it is connected to
amplifier is very high (e.g., when the amplifier seriously degraded performance. Terminal 4 potential, and the TO-5 case of
output is used to drive COS/MOS digital the CA3130 is also internally tied to Term-
circuits in comparator applications). Output Stage-The output stage consists of a inal4, input terminal 3 is essentially "guarded"
drain-loaded inverting amplifier using COS/ from spurious leakage currents.
Input Stages-The circuit of the CA3130 is MOS transistors operating in the Class A
shown in Fig. 1. It consists of a differential- mode. When operating into very high resist- Offset Nulling
input stage using PMOS field-effect tran- ance loads, the output can be swung within Offset-voltage nulling is usually accomplished
sistors (06, 07) working into a mirror-pair millivolts of either supply rail. Because the with a 100,DOO-ohm potentiometer con-
of bipolar transistors (09, Ql0) functioning output stage is a drain-loaded amplifier, its nected across Terms. 1 and 5 and with the
as load resistors together with resistors R3 gain is dependent upon the load impedance. potentiometer slider arm connected to Term.
through R6. The mirror-pair transistors also The transfer characteristics of the output 4. A fine offset-null adjustment usually can
function as a differential-to-single-ended con- stage for a load returned to the negative be effected with the slider arm positioned in
verter to provide base drive to the second- supply rail are shown in Fig. 6. Typical op- the mid-point of the potentiometer's total
stage bipolar transistor (all). Offset nulling, amp loads are readily driven by the output range.
when desired, can be effected by connecting stage. Because large-signal excursions are non- Input-Current Variation with Temperature
a 100,OOO-ohm potentiometer across Terms. linear, requiring feedback for good waveform
1 and 5 and the potentiometer slider arm to The input current of the CA3130 Series cir-
reproduction, transient delays may be en- cuits is typically 5 pA at 25 0 C. The major
Term. 4. Cascode-connected PMOS transistors countered. As a voltage follower, the ampli-
02, 04 are the constant-current source for portion of this input current is due to leakage
fier can ach ieve 0.01 per cent accuracy levels, current through the gate-protective diodes in
the input stage. The biasing circuit for the including the negative supply rail.
constant-~urrent source is subsequently de-
the input circuit. As with any semiconductor-
scribed. The small diodes 05 through 08 junction device, including op amps with a
provide gate-oxide protection against high- Input Current Variation with Common- junction-FET input stage, the leakage cur-
voltage transients, e.g., including static elec- Mode Input Voltage rent approximately doubles for every lOoC
tricity during handling for 06 and Q7. increase in temperature. Fig.12 provides data
As shown in the Table of Electrical Charac- on the typical variation of input bias current
Second-Stage-Most of the voltage gain in the teristics, the input current for the CA3130 as a function of temperature in the CA3130.
CA3130 is provided by the second amplifier Series Op-Amps is typically 5 pA at T A=250 C
stage, consisting of bipolar transis,,>r all when terminals 2 and 3 are at a common- 4000 V+~7.5V
2 V·z-7'V
and its cascode-connected load resistance mode potential of +7.5 volts with respect to
provided by PMOS transistors Q3 and 05. negative supply Terminal 4. Fig.11 contains
The source of bias potentials for these PMOS data showing the variation of input current
transistors is subsequently described. Miller- as a function of common-mode input voltage
Effect compensation (roll-off) is accom- at TA = 25 0 C. These data show that circuit
plished by simply connecting a small capa- designers can advantageolJsly exploit these
citor between Terms. 1 and 8. A 47-picofarad characteristics to design circuits which typi-
capacitor provides sufficient compensation cally require an input current of less than 1
for stable unity-gain operation in most pA, provided the common-mode input volt-
applications. age does not exceed 2 volts. As previously
noted, the input current is essentially the
Bias-Source Circuit-At total supply voltages, result of the leakage current through the
somewhat above 8.3 volts, resistor R2 and /
-80 -60 -40 -20 0 20 40 60 eo 100 120 140
zener diode ZI serve to establish a voltage of AMBIENT TEMPERATURE ITAI-·C
8.3 volts across the series-connected circuit,
consisting of resistor R I, diodes 01 through Fig. 12 - Input current VB. ambient temperature.
tFor general information on the characteristics
04, and PMOS transistor 01. A tap at the of COS/MOS transistor-pairs in linaar-eircuit
junction of resistor R1 and diode 04 provides applications, see File No. 619, data bulletin on In applications requiring the lowest practical
a gate-bias potential of about 4.5 volts for CA3600E "COS/MOS Transistor Array". input current and incremental increases in
___________________________________________________________________ 221
CA3130, CA3130A, CA3130B Types
su ited to service as voltage followers. Fig. 16 waveform in Fig. 17a with input-signal 9-Bit COS/MOS DAC
shows the circuit of a classical voltage ramping. The waveforms in Fig. 17b show A typical circuit of a 9-bit Digital-to-Analog
follower, together with pertinent waveforms that the follower does not lose its input-to- Converter (DAC)* is shown in Fig.18 This
using the CA3130 in a split-supply config- output phase-sense, even though the input is system combines the concepts of multiple-
uration. being swung 7.5 volts below ground potential. . switch COS/MOS IC's,' a low-cost ladder
A voltage follower. operated from a single This unique characteristic is an important network of discrete metal-ox ide-film resistors,
supply. is shown in Fig. 17, together with attribute in both operational ampl ifier and a CA3130 op amp connected as a follower,
related waveforms. This follower circuit is comparator applications. Fig .. 17b also shows and an inexpensive monolithic regulator in a
linear over a wide dynamic range, as illus- the manner in which the COS/MOS output simple single power-supply arrangement. An
trated by the reproduction of the output· stage permits the output signal to swing down additional feature of the DAC is that it is
to the negative supply-rail potential (i.e., readily interfaced with COS/MOS input logic,
ground in the case shown I. The digital-to- e.g., 10-volt logic levels are used in the circuit
analog converter (DAC) circuit, described in of Fig_18.
the following section, illustrates the practical
The circuit uses an R/2 R voltage-ladder
use of the CA3130 in a single-supply voltage-
network, with the output potential obtained
10 Ul follower application. directly by terminating the ladder arms at
either the positive or the negative power-
+1'5 V
supply terminal. Each CD4007 A contains
three "inverters", each "inverter" function-
10 ~n
ing as a single-pole double-throw switch to
terminate an arm of the R/2R network at
either the positive or negative power-supply
BWI-3dB)=4MHr
terminal. The resistor ladder is an assembly
SR~ 10 VII" of one per cent tolerance metal.-oxide film
resistors_ The five arms requiring the highest
accuracy are assembled with series and
parallel combinations of 806,OOO-ohm re-
2 loA
sistors from the same manufacturing Iot_
A single 15-volt supply provides a positive
o II'F bus for the CA3130 follower amplifier and
feeds the CA3085 voltage regulator. A
"scale-adjust" function Is provided by the
regulator output control, set to a nominal
10-volt level in this [Link]. The line-voltage
regulation (approximately 0.2%) permits a
9-bit accuracy to be maintained with varia- .
tions of several volts in the supply. The
flexibil ity afforded by the COS/MOS building
blocks simplifies the design of DAC systems
tailored to particular n~eds.
Top Trace: Output
Bottom Trace: Input Single-Supply, Absolute-Value, Ideal Full-
lal Small-signal response 150·mV/div.
OV Wave Rectifier
and 200 ns/div.) The absolute-value circuit using the CA3130
is shown in Fig_ 19. During positive excur-
(a) Output..waveform with input-signal ramping sions, the input signal is fed through tne
12 V Idiv. and 500 !,s/div.l feedback network directly to the output.
Simultaneously. the positive excursion of the
input signal also drives the output termi-
nal (No_ 6) of the inverting amplifier in a
negative-going excursion such that the 1 N914
diode effectively disconnects the ampl ifier
from the signal path. During a negative-going
excursion of the input signal, the CA3130
functions as a normal inverting amplifier with
a gain equal to -R2/R1. When the equality
of the two equations shown in Fig. 19 is
satisfied, the full-wave output is symmetrical.
92CS·24739
Top Trace: Output signal 12 Vldiv. Peak Detectors
and 5 !'s/div.)
Peak-detector circuits are easily implemented
Center Trace: Difference signal (5 mV Jdiv.
92CS-24728RI with the CA3130, as ill ustrated in Fig. 20
and 5 )lsldiv.) for both the peak-positive and the peak-
Bottom Trace: Input signal (2 V/div.
Top Trace: Output 15 V/div. and 200 !'sldiv.)
Bottom Trace: Input 15 V/div. and 200 !'sldiv.) negative circuit. It should be noted that with
and 5!,s/div.1 large-signal inputs, the bandwidth of the
(b) Output-waveform with ground-reference
(b) Input-output difference signal showing
sine-wave input
settling time (Measurement made with
Tektronix 7 A 13 differential amplifier) Fig_17 - Single-supply voltage-follower with
associated waveforms_ (e.g_, for use *"Digital-to-Analog Conversion Using the
Fig. 16 - Split~supply voltage follower with in single-supply DIA converter; see RCA-CD4007A COSIMOS IC", Application
associated waveforms. Fig.9 in ICAN-6OOO!_ Note ICAN-6080.
___________________________________________________________________ 223
CA3130, CA3130A, CA3130B Types
justment over the range from 0.1 to 50 volts
and currents up to 1 ampere. The error
amplifier (lCl) and circuitry associated with
IC2 function as previously described, al-
though the output of ICl is boosted by a
discrete transistor (04) to provide adequate
base drive for the Darl ington ·connected series·
pass transistors 01, 02. Transistor Q3 func-
tions in the previously described current-
limiting circuit.
Multivibrators
The exceptionally high input resistance pre-
sented by the CA3130 is an attractive feature
for multivibrator circuit design because it
permits the use of timing circuits with high
RIC ratios. The ·circuit diagram of a pulse
generator (astable multivibratorl. with pro-
visions for independent control of the "on"
and "off" periods, is shown in Fig. 23.
Resistors R1 and R2 are used to bias the
CA3130 to the mid-point of the supply-volt-
age and R3 is the feedback resistor. The
pulse repetition rate is selected by position-
ing Sl to the desired position and the rate
remains essentially constant when the re-
sistors which determine "on·period" and
"off-period" are adjusted.
Function Generator
6UA Fig. 24 contains a schematic diagram of a
function generator using the CA3130 in the
RSULATtON (NO LOAD TO FULL LOAD); c 0.01" integrator and threshold detector functions:
INPUT REGULATION: OD21&./V This circuit generates a triangular or square-
HUM AND NOISE OUTPUT: '" 20 I£V loP TO 100 kHz
'2CM~24752 wave output that can be swept over a
Fig.21 - Voltageregulstorcircuit (0 to 13 Vat 40 ms). 1·,000,000:1 range (0.1 Hz to 100 kHz) by
means of a single control, Rl. A voltage-
control input is also available for remote
sweep-control.
+cr--~-------------------.--------~ The heart of the frequency-determining sys-
tem is an operational-transconductance-ampli-
fier (OTA)', IC1, operated as a voltage-con-
trolled current-source. The output, la, is a
current applied directly. to the integrating
capacitor, Cl, in the feedback loop of the
integrator IC2, using a CA3130, to provide
ths triangular-wave output. Potentiometer
R2 is used to adjust the circuit for slope
1000 pF 43 k.D. + symmetry of positive-going and negative-
- 100 going signal excursions.
,.F
Another CA3130, IC3, is used as a controlled
+55V OUTPUT, switch to set the excursion limits of the
INPUT
lC2 0.1 T050V triangular output from the integrator circuit.
AT I A
!CAm6 Capacitor C2 is a "peaking adjustment" to
I optimize the high-frequency square-wave
I performance of the circuit.
I Potentiometer R3 is adjustable to perfect the
I "amplitude symmetry" of the square-wave
L __ _ output signals. Output from the threshol d
detector is fed back via resistor R4 to the
input of ICl so as to toggle the current
IkQ
'OkQ·~VO~LT~A~G~E----------4-----~ source from plus to minus in generating the
S2kA [Link]
linear triangular wave.
REGULATION INO LOAO TO FULL LOAO): <0.005%
INPUT REGULATION, <[Link]%/Y
HUM AND NOISE OUTPUT, <250,.V RMS UP TO 100 kHz
92CM-24734
Fig.22 - Vo/tags regulator circuit (0. I to 50 V st I A). "See File No. 475 and ICAN-6668.
________________________________________________________________ 225
CA3130, CA3130A, CA3130B Types
+15 v
7~kn
INH1f---,\z"',,n..--<H
I I'F
5001 RL-,oon
("0·150 ...,
AT THO·
- 10 ..)
AV(CLl =48 dB
LARGE SIGNAL
BW\-3 dB)" 50 kHz
510 Ul
NOTE: *SEE FILE NO. 619
TRANSISTORS pi, p2, p3 AND nl, n2, n3 ARE
PARALLEL - CONNECTED WIiH Q8 AND QI2,
RESPECTIVELY, OF THE CA313Q
92CM-24131
Fig. 25 - COS/MOS transistor array (CA3600E J
connected as power-booster in the
outpllt stage of the CA3130.
92CS·25243
The photographs and dimensions represent a chip
Dimensions in parentheses are in millimeters and when it is part of the wafer. When the wafer is
are derived from the basic inch dimensions as in- cut into chips, the cleavage angles are 570 in-
dicated. Grid graduations are in mils (10- 3 inch). stead of gOO with respect to the face of the chip.
Therefore, the isolated chip is actually 7 mils
(0. 17 mth) larger in both dimensions.
Dimensions and Pad Layout for CA3130H.
___________________________________________________________________ 227
CA3138G, CA3138AG Types
ELECTRICAL CHARACTERISTICS at TA = 25°C
LIMITS
Characteristic Test Conditions CA3138G CA3138AG Units
Min. Typ. Max. Min. Typ. Max.
Collector-t~-Emitter Sustaining
Voltage, V CEO(sus)'
IC=lmA,IB=O 15 20 - 15 20 - V
Collector-ta-Emitter Breakdown _.
IC = 10llA 20 55 25 60 - V
Voltage, V(BRICES
Collector-ta-Base Breakdown
IC = 10 IIA, IE = a 20 55 - 25 60 - V
Voltage, V (BRICBO
Emitter-ta-Base Breakdown
IE = 10 IIA, IC = a 5 7.2 - 5 7.2 - V
Voltage, V(BRIEBO
Base-ta-Emitter Saturation
IC = [Link]= 12.5mA 0.7 0.81 1.1 0.7 0.81 1.1 V
Voltage, VBE(satl'
Collector-ta-Emitter Saturation
IC=500mA, IB = 12.5 mA - 0.26 0.4 - 0.26 0.4 V
Voltage, V CE(sat)'
ICBO VCB=15V - 0.03 1 - 0.02 0.1
Collector·Cutoff VCE = 10 V - 0.5 - - 0.3 1.0
ICED IIA
Current
lEBO VEB = 4 V - 0.01 - - 0,01 0.1
IC=10mA, VCE= 5V - - - 35 140 -
Static Forward-Current Transfer I C =100mA,VCE=5V 80 160 450 80 160 450
Ratio (Beta), hFE*
IC = 500mA, VCE = 5V 95 170 500 95 170 500
IC = 1 A, VCE = 5 V 40 170 - 40 170 -
Small,Signal Forward Current IC - 50mA, VCE = 10V,
Transfer Ratio, hfe f=100MHz
2 - - 2 - -
Collector-ta-Base
Capacitance, CCB
VCB = 10 V, IE = 0 - 18 - - 18 - pF
Emitter-ta-Base
Capacitance, CEB
VEB = 0.5 V, IC = 0 - 77 - - 77 - pF
Rise Time (See Test Ckt.
Fig.61,t r IC=570mA
- 6 - - 6 - ns
Fall Time (See Test Ckt.
Fig. 6), tf IBl = 30mA - 100 - - 100 - ns
Delay Time (See Test Ckt.
Fig. 61, td IB2 = a - 7.5 - - 7.5 - ns
Storage Time (See Test Ckt.
Fig. 61, ts - 850 - - 850 - ns
*Pulse Conditions: width == 300 ,u.s; duty cycle == 1 %.
HV
V TO [Link]
o SCOPE
+gv.1""'l... OVl.....Of-'W_ _-f
60i" ON
40,..8 OFF
92CS-26926RI
Fig. 6 - Switching time test circuit and waveforms.
________________________________________________________________ 229
CA3140, CA3140A, CA3140B Types
TYPICAL ELECTRICAL CHARACTERISTICS CIRCUIT DESCRIPTION
Fig.2 is a block diagram of the CA3140
TEST Series PMOS Operational Amplifiers. The
CONDITIONS input terminals may be operated down to
CHARACTERISTIC CA3140B CA3140A CA3140 UNITS 0.5 V below the negative supply rail. Two
V+=+15V
(T,S,E) (T,S,E) class A amplifier stages provide the voltage
V-= -15V (T,S)
gain, and a unique class A8 amplifier stage
TA = 25°C provides the current gain necessary to drive
low-i mpedance loads.
[Link] of Re-
A biasing circuit provides control of cascoded
sistor Between
Input Offset Voltage constant-current flow circuits in the first and
Term. 4 and 5 or 43 18 4.7 kn second stages. The CA3140 includes an on-
Adjustment Resistor
4 and 1 to Adjust chip phase-compensating capacitor that is
Max. Via sufficient for the unity gain voltage-follow-
I nput Resistance Rl 1.5 1.5 1.5 Tn er configuration.
Input Stages - The schematic circuit diagram
Input Capacitance CI 4 4 4 pF of the CA3140 is shown in Fig.3_ It con-
Output Re~istance RO 60 60 60 n sists of a differential-input stage using PMOS
field-effect transistors (09, 010) working
Equivalent Wideband BW = 140 kHz intoa mirror pair: of bipolar transistors (all,
Input Noise Voltage en 48 48 48 !J. V 012) functioning as load resistors together
RS = 1 Mn with resistors R2 through R5_ The mirror-
(See Fig. 39)
pair transistors also function as a differen-
Equivalent Input
Noise Voltage en
I
f= 1 kHz RS = 40 40 40
nV/...!Hz
tial-to-single-ended converter to provide base-
current drive to the second-stage bipolar
f=10kHz \lOOn 12 12 12
(See Fig.l 0) transistor (013). Offset nulling, when de-
Short-Circuit Current to sired, can be effected with a 10-kn poten-
tiometer connected across terminals 1 and
Opposite Supply Source IOM+ 40 40 40 mA 5 and with its slider arm connected to termi-
Sink IOM- 18 18 18 mA nal 4. Cascode-connected bipolar transistors
Gain-Bandwidth 02, 05 are the constant-current source for
the input stage. The base-biasing circuit for
Product, (See Figs. 5 &18) IT 4.5 4.5 4.5 MHz
the constant-current source is described sub-
Slew Rate, (See Fig.6) SR 9 9 9 V/!J.s sequently. The small diodes 03, 04, 05 pro-
vide gate-oxide protection against high-volt-
Sink Current From Terminal 8
age transients, e.g., static electricity.
To Terminal 4 to Swing 220 220 220 IJ.A Second Stage - Most of the voltage gain in
Output Low the CA3140 is provided by the second amp-
Transient Response: lifier stage, consisting of bipolar transistor
RL = 2 kn 0.08 0.08 0.08 !J.s 013 and its cascode-connected load resis-
Rise Time
tr CL = 100pF tance provided by pipolar transistors 03, 04_
Overshoot (See Fig, 37) 10 10 10 %
On-chip phase compensation, sufficient for
Settling Time RL = 2kn a majority of the applications is provided by
1 mV ts 4.5 4.5 4.5 Cl. Additional Miller-Effect compensation
atl0V p_p , CL=100pF !J.s
10mV 1.4 1.4 1.4 (roll-off) can be accomplished, when de-
(See Fig_ 17) Voltage Follower
sired, by simply connecting a small capa-
citor between terminals 1 and 8, Terminal
8 is also used to strobe the output stage into
quiescence. When terminal 8 is tied to the
negative supply rail (terminal 4) by mechani-
calor electrical means, the outout terminal 6
swings low, i.e., approximately to terminal
4 potential.
Output Stage - The CA3140 Series circuits
employ a broadband output stage that can
sink loads to the negative supply to comple-
ment the capability of the PMOS input stage
when operating near the negative rail. Ouies-
cent current in the emitter-follower cascade
circuit (017, 018) is established by tran-
sistors (0 14, 015) whose base-currents are
"mirrored" to current flowing through diode
02 in the bias circuit section. When the
CA3140 is operating such that output ter-
minal 6 is sourcing current, transistor 018
functions as an emitter-follower to source
OFFSET
NULL current from the V+ bus (terminal 7), via
07, R9, and R 11. Under these conditions,
the collector potential of 013 is suffi-
Fig.2 - Block diagram of CA3140 series. ciently high to permit the necessary flow of
base current to emitter follower 017 which,
in turn, drives 018.
231
CA3140, CA3140A, CA3140B Types
1----, r - - - - -
BIAS CIRCUIT INPUT STAGE
I II
I r-++----l-------,
~--++--I
I
I
I
I
SUPPLY [Link] (v-t; Y-}-YOLTS
. Fig.4 - Open-loop voltage gain v. supplV voltage
and temperature.
20 LOAD RESISTANCE (RLI. 2 Ul
LOAD CAPACITANCE (eL.I" 100 pF
OFFSET NULL STROBE
ALL RESISTANCE VALUES ARE IN OHMS.
Fig.3 - Schematic diagram of CA3140 series.
!5 10 15
SUPPLY VOLTAGE IV+, V-I - VOLTS
20 ..
Fig,5 - Gain-bandwidth product vs supply voltage
and temperature.
TYPICAL ELECTRICAL CHARACTERISTICS FOR DESIGN GUIDANCE
At V+'!'5 V, V-= 0 V, TA = 25°C
CHARACTERISTIC CA3140B CA3140A CA3140 UNITS
(T,S) (T,S,E) (T,S,E)
I nput Offset Voltage IVlol 0.8 2 5 mV
Input Offset Current 11101 0.1 0.1 0.1 pA
I nput Current II 2 2 2 pA
Input Resistance 1 1 1 Tn
Large·Signal Voltage Gain AOL 100 k 100 k 100 k V/v
(See F ig,.4, 18) 100 100 100 dB
Common·Mode Rejection Ratio, CMRR 20 32 32 IJV/V I
SUPPLY VOLTAGE IV+, V-'-VOLTS
94 90 90 dB
Fig.6 - Slew rate vs supplV voltage andtemperature.
Common·Mode Input·Voltage Range VICR -0.5 -0.5 -0.5
V
(See Fig.20) 2.6 2.6 2.6
Power·Supply Rejection Ratio [Link].V+ 32 100 100 IJV/V
90 80 80 dB
Maximum Output Voltage VOM+ 3 3 3
V
(See Figs.13,20) VOM- 0.13 0.13 0.13
Maximum Output Current:
Source 10M+ 10 10 10
mA
Sink 10M 1 1 1
Slew Rate (See Fig.6) 7 7 7 V/IJs
Gain-Bandwidth Product (See Fig.5) fT 3.7 3.7 3.7 MHz
Supply Current (See Fig.7) 1+ 1.6 1.6 1.6 mA
De,,;ce Dissipation PD B B B mW I
SUPPLY VOLTAGE IV+, V-}-[Link]
Sink Current from Term. 8 to
200 200 200 IJA Fig.7 - Quiescent supply current VB supplv voltage
Term. 4 to Swing Output Low
and temperature.
________________________________________________________________ 233
CA3140, CA3140A, CA3140B Types
load current, device dissipation will increase,
raising the chip temperature and resulting in
increased input current. Fig.19 shows typi-
cal input-terminal current versus ambient
temperature for the CA3140.
It is well known that MOS/FET devices can
exhibit slight changes in characteristics (for
example, small changes in input offset volt-
age) due to the application of large differ-
ential input voltages that are sustained over
v- long periods at elevated temperatures.
Q BASIC b IMPROVED c. SIMPLER
IMPROVED
Both applied voltage and temperature ac-
RESOLUTION
RESOLUTION celerate these changes. The process is rever-
Fig. 15 - Three offset-voltage nulling methods_ sible and offset voltage shifts of the opposite
polarity reverse the offset. Fig.14 shows the
SUPPLY VOLTAGE: V -115'1;'1-.-115'1 FOLLOWER typical offset voltage change as a function of
AMBIENT TEMPERATURE (TA)-2!1·C - - - INVERTWG
various stress voltages at the maximum rating
of 125°C (for TO-5); at lower temperatures
(TO-5 and plastic!. for eX;lmple, at 85°C,
this change in voltage is considerably less.
In typical linear applications, where the
differential voltage is small and symmetircal,
these incremental changes are of about the
same magnitude as those encountered in an
operational amplifier employing a bipolar a
transistor input stage.
SUPER SWEEP FUNCTION GENERATOR
01 1.0 10 A function generator having a wide tuning
lal SETTLING TlME - ", ran~ is shown in Fig.21. The 1,000,000/1
adjustment range is accomplished by a single
variable potentiometer or by an auxiliary
FOLLOWER
sweeping signal. The CA3140 functions as a
non-inverting read-out amplifier of the tri-
SUPfiLYVOLTAGE,V -+I!lVjY---I!5Y - 7'1II~
,~°.
Fig. 16 - Methods of utilizing the VCE($at) sinking- AMBIENT TEMPERATURE ITA1- ZS·C
- 9Ol~
current capability of the CA3140 series. 1100
I '%11111 t;. f.
-105~ I
'il - 120~-:'
Sao S~j ~- - 13!I:i~
BANDWIDTH AND SLEW RATE
For those cases where bandwidth reduction
is desired, for example, broadband noise re-
~
~IO
~
Sr.
1,.
.~
~
.
p~ -"'0 ~~
duction, an external capacitor connected be-
tween terminals 1 and8 can reduce the open-
~40 ~>
loop -3 dB_ bandwidth_ The slew rate will,
however, also be proportionally reduced by
using this additional capacitor. Thus, a 20%
reduction in bandwidth by this technique
.'"
INVERTING
~'"
10
"
, .
10 10"
FREQUENCY
1111r..~r.
1111 1 1111:'0
[Link]~
10
m- HI
to' 10
,
will also reduce the slew rate by about 20%_
SIMULATED
Fig.17 shows the typical settling time re-
'~i
Fig. IS - Open-loop va/raga gain and phase lag
quired to reach 1 mV or 10 mV of the final
oo:~ ~2.n
vs frequency.
value for various levels of large signal in-
puts for the voltage-follower and inverting I ,
unity-gain amplifiers. The exceptionally "." K: SUPPLY VOLTAGE: Y+.+I!I V, ""---15 Y
fast settling time characteristics shown in [Link].Q -e.- 10
Fig.18 are largely due to the high combina- /
tion of high gain and wide bandwidth of
the CA3140.
INPUT CIRCUIT CONSIDERATIONS
(b) TEST CIRCUITS
As mentioned previously, the amplifier in- Fig. 17 - Input IIoltage vs settling time.
puts can be driven below the terminal 4
potential, but a series current-limiting re-
sistor is recommended to limit the maximum tremely large input-signal transients from
input terminal current to less than 1 mA to forcing a signal through the input-protection
prevent damage to the input protection network and directly driving the internal
circuitry. constant-current source which could result -60 -40 -20 0 20 40 10 10 100 120 140
Moreover, some current-limiting resistance in positive feedback via the output terminal. AMBIENT TEMPERATURE ITA I - '"C
should be provided between the inverting A 3.9-kn resistor is sufficient.
input and the output when the CA3140 is The typical input current is in the order of
used as a unity-gain voltage follower. This Fig. ~9 - Input current vs ambient
10 pA when the inputs are centered at nomi-
resistance prevents the possibility of ex- nal device dissipation. As the output supplies tempera ture.
______________________________________________________ ~--~-------235
CA3140, CA3140A, CA3140B Types
[Link]
SWEEP IN
6204
FREQUENCY
CAliBRATION -15 V
MINIMUM I
I
I
I
510 Q
I
I I
: g~~19A::AY
L ________ ..J
:
Fig. 23 - Sine-wave shapero
-15 V
potentiometer connected between terminals
Fig. 22 - Meter driver and buffer amplifier. 2 and 6 of the CA3140 and the 9.1-kil re-
sistor and 10-kil potentiometer from termi-
750llll nal 2 to ground, Two break points are es-
tablished by diodes D1 through D4. Positive
100 kO feedback via D5 and D6 establishes the zero
slope at the maximum and minimum levels
FINE
100 kll RATE of the sine wave. This technique is neces-
sary because the voltage-follower configu-
8.2 kll
+15V SAW~OJ~ AND
ration approaches unity gain rather than the
LOW~LEVEL SET
zero gain required to shape the sine wave at
(-14.5'11) the two extremes.
This circuit can be adjusted most easily with
75 lin a distortion analyzer. but a good first approxi-
mation can be made by comparing the output
signal with that of a sine-wave generator. The
initial slope is adjusted with the poten-
tiometer R 1. followed by an adjustment of
10 kn GATE
'>--<6l_O_-"AI'v-+ PULSE R2. The final slope is established by ad-
OUTPUT
justing R3. thereby adding additional seg-
ments that are contributed by these diodes.
Because there is some interaction among
these controls, repetition of the adjustment
procedure may be necessary
(7)--+----~r_----r-<.J +15V
SWEEPING GENERATOR
91Ul IOkn Fig. 24 shows a sweeping generator. Three
LOGVro
-----, N: TRIANGLE CA3140's are used in this circuit. One
I CA3140 is used as an integrator. a second
TRANSISTORS I ~ SAWTOOTH
device is used as a hysteresis switch that
C~~g:6
IOOll IL____ 3 _ _________ JI
ARRAY
I,
.AM "LOG'
determines the starting and stopping points
of the sweep. A third CA3140 is used as a
logarithmic shaping network for the log
function. Rates and slopes. as well as saw-
Fig. 24 - Sweeping generator. tooth. triangle. and logarithmic sweeps are
generated by this circuit.
establish the upper frequency limit, set the justment control calibrates the meter so
Frequency Adjustment Potentiometer to its that it deflects 1. 6 of full scale for each de- WIDEBAND OUTPUT AMPLIFIER
upper end and then adjust the Maximum cade change in frequency.
Frequency Calibration Control for the maxi- Fig. 25 shows a high-slew-rate. wide band am-
mum frequency. Because there is inter- plifier suitable for use as a 50-ohm trans-
action among these controls, repetition of SINE-WAVE SHAPER mission-line driver. This circuit. when used
the adjustment procedure may be necesary. in conjunction with the function generator
The circuit shown in Fig. 23 uses a CA3140 and sine-wave shaper circuits shown in Figs.
Two adjustments are used for the meter. as a voltage follower in combination with 21 and 23 provides 18 volts peak-to-peak
The meter sensitivity control sets the meter- diodes from the CA3019 Array to convert output open-circuited. or 9 volts peak-to-peak
scale width of each decade, while the meter the triangular signal from the function gen- output when terminated in SO ohms. The
position control adjusts the pointer on the erator to a sine-wave output signal having ty- slew rate required of this amplifier is 28
scale with negligible effect on the sensitivity pically less than 2% TH D. The basic zero- volts/l/s (18 volts peak-to-peak x 11' x O.S
adjustment. Thus, the meter sensitivity ad- crossing slope is established by the 10-kil MHzl.
______________________________________________________________ 237
CA3140, CA3140A, CA3140B Types
system is a serious consideration, the more FOR SINGL.E SUPPLY
usual current-sampling resistor-type of cir- +30V 20 dB FLAT POSITION GAIN
± 15 dB BASS AND TREBLE BOOST AND
cuitry should be employed_ CUT AT 100 Hz AND 10 11HZ', RESPECTIVELY
25 VOLTS p-p OUTPUT AT 20 kHz
01105 ,.F -3 dB AT 24 kHz FROM I kHz REFERENCE
A power Darlington transistor (in a heat
sink TO-3 case), is used as the series-pass
element for the conventional current-limiting
system, Fig_ 27, because high-power Dar- FOR DUAL SUPPLIES
lington dissipation will be encountered at +15 V
low output voltage and high currents_
A small heat-sink VERSAWATT transistor is 2.2 MA
used as the series-pass element in the fold-
back current system, Fig_28, since dissi-
pation levels will only approach 10 watts_
In this system, the D2201 diode is used for ,,
current sampling_ Foldback is provided by 10110 I
the 3 kn and 100 kn divider network con- I
BOOST
BASS:
'
nected to the base of the current-sensing L___TQ'!.E_ ~.!~~L._ ~E_T!i!>,!K___ J
transistor _
'Both regulators, Figs_ 27 and 28, provide Fig. 30 - Tone control circuit using CA3130 series
better than 0_02% load regulation_ Because 120-dB midband gain!.
there is constant loop gain at all voltage set-
tings, the regulation also remains constant_ lator output. A FET channel resistance, a
Line regulation is 0_1% per volt_ Hum and FOR SINGLE SUPPLY thermistor, a lamp bulb, or other device
noise voltage is less than 200 JlV as read whose resistance is made to increase as the
with a meter having a 10-MHz bandwidth_ output amplitude is increased are a few of
Fig_31 (a) shows the turn ON and turn OFF the elements often utilized.
characteristics of both regulators_ The slow
turn-on rise is due to the slow rate of rise 2.2MA
of the reference voltage_ Fig_ 29 (b) shows
the transient response of the regu lator with 20pf :
I :1:.15 dB BASS ANO TREBL.E BOOST
the switching of a 20-n load at 20 volts out- L''V''''knc".'''.'''n:-~yv,kn~ : :~pi~~I~lL~~ Hz AND 10 kHz, OUTPUT
put_ ILINEAR) I 2e VOLTS p-p OUTPUT AT 20 kHz.
I BOOST TREBLE CUT J -3 dB AT 70 11Hz FROM 1kHz
L~~E_~_~~F!<J ~E::~iN,.;E POSITION GAIN.
CI
TONE CONTROL CIRCUITS
FOR DUAL. SUPPLIES
".
f. 1
High-slew-rate, wide-bandwidth, high-output 21r~
voltage capability and high input impedance AOS·I+~"'~
are all char,acteristics required of tone-con-
trol amplifiers_ Two tone control circuits ACL"I+~
that exploif these characteristics of the
CA3140 are shown in Figs. 30 and 31. Fig. 32 - Basic Wien bridge oscillator circuit
Fig. 31 - Baxandall tone control circuit using using an operational amplifier.
The first circuit, shown in Fig. 31, is the
Baxandall tone-control circuit-which provides CA3140 series.
unity gain at midband and uses standard Fig. 33 shows another means of stabilizing
linear potentiometers_ The high input im- the oscillator with a zener diode shunting
pedance of the CA3140 makes possible the WIEN BRIDGE OSCILLATOR the feedback resistor (Rf of Fig. 32). As
use of low-cost, low-value, small-size capaci- the output signal amplitude increases, the
tors, as well as reduced load of the driving Another application of the CA3140 that zener diode impedance decreases resulting
stage. makes excellent use of its high input-imped- in more feedback with consequent reduction
ance, high-slew-rate, and high-voltage quali- in gain; thus stabilizing the amplitude of the
Bass treble boost and cut are ± 15 dB at ties is the Wien Bridge sine-wave oscillator. output signal. Furthermore, this combina-
100 Hz and 10 kHz, respectively. Full A basic Wien Bridge oscillator is shown in tion of a monolithic zener diode and bridge
peak-to-peak output is available up to at Fig. 32. When R 1 = R2 = Rand Cl = C2 = C, rectifier circuit tends to provide a zero tem-
least 20 kHz due to the high slew rate of the the frequency equation reduces to the fa- perature coefficient for this regulating sys-
CA3140_ The amplifier gain is -3 dB down miliar f;, 112 11' RC and the gain requireri for tem. Because this bridge rectifier system
from its "flat" position at 70 kHz. oscillation, AOSC is equal to 3. Note that has no time constant, i.e., thermal time con-
Fig. 30 shows another tone-control circuit if C2 is increased by a factor of four and R2 stant for the lamp bulb, and RC time con-
with similar boost and cut specifications. is reduced by a factor of four, the gain re- stant for filters often used in detector net-
The wideband gain of this circuit is equal to quired for oscillation becomes 1_5, thus per- works, there is no lower frequency limit.
the ultimate boost or cut plus one, which in mitting a potentially higher operating fre- For example, with l-JlF polycarbonate capa-
this case is a gain of eleven. For 20-dB quency closer to the gain-bandwidth pro- citors and 22 Mn for the frequency deter-
boost and cut, the input loading of this cir- duct of the CA3140. mining network, the operating frequency is
cuit is essentially equal to the value of the Oscillator stabilization takes on many forms. 0.007 Hz.
resistance from terminal No.3 to ground. It must be precisely set, otherwise the am- As the frequency is increased, the output
A detailed [Link] of this circuit is given in plitude will either diminish or reach some amplitude must be reduced to prevent the
"An IC Operational Transconductance Amp- form of limiting with high levels of distor- output signal from becoming slew-rate limi-
lifier (OTA) With Power Capability" by tion. The element, Rs , is commonly re- ted. An output frequency of 180 kHz will
L, Kaplan and H. Wittlinger, IEEE Trans- placed with some variable resistance element. reach a slew rite of approximately 9 volts!
actions on Broadcast and Television Re- Thus, through some control means, the value Jls when its amplitude is 16 volts peak-to-
ceivers, Vol. BTR-18, No.3, August, 1972. of Rs is adjusted to maintain constant oscil- peak.
__________________________________________________________________ 239
CA3140, CA3140A, CA3140B Types
[Link]--:;;
R3 '10 on (Oo?;) 92CS-278S7RI
20 v p - p Ir>.PUT 811<1- 3d81 -290 .HI, DC OUTPUT (AVG I
Fig. 37 - Single-supply, absolute-value, ideal fuJI-wave rectifier with associated waveforms.
+- 15 V
SIMULATED
LOAD
>-"1"""-'
, ),
100 PF~r 1t*
, ,
L~j
~::-
8w(-3dB\·4.5 MHz TOP TRACE :OUTPUT
TOP TRACE :OUTPUT SIGNAL
SR'9 Y/jJ.~ (50 mY/OIY AND 200 ns/OIVI
{5V/DIV AND 5/-Ls/DIV.}
BOTTOM TRACE: INPUT
005,..F CENTER TRACE: DIFFERENCE SIGNAL
(50 mVlOIVANO 200 fls/DIVl
(5m VlOIV· AND 5~sl DIV·}
(a) SMALL· SIGNAL RESPONSE
BOTTOM TRACE '-INPUT SIGNAL
150 mV/DIV ANO 200nslOlVl
{5V/DIV. AND 5j-ts/DIV}
\b) INPUT- OUTPUT DIFFERENCE SIGNAL
SHOWIN(; SETTLING TIME {MEASUREMENT
MADE WITH TEKTRONIX 7AI3 DIFFERENTIAL
AMPLIFIER) 92C5-21880
Fig. 38 - Split-supply voltage-foJlower test circuit and associated waveforms.
BW(-3dBl= 140 kHz
l 54-62
(1312-1574\
TOTAL NOISE VOLTAGE (REFERRED IkSl
TO INPUT}:48/J-V TYP
92C$-27888
Fig. 39 - Test circuit amplifier (30~d8 gain) used
for wideband noise measurement. r-
• 4~10
(0 102~ 02541
1 - - - - - - - (I 80~=~g006) - - - - - - - 1
CA3140H Chip
The photographs and dimensions represent Dimensions in parentheses are in millimeters and
a chip when it is part of the wafer. When the are derived from the basic inch dimensions as in-
wafer ~ cut into ch;p~, the cleavage angles dicated. Grid graduations are in mils (10--- 3 inch).
are 57 instead of 90 with respect to the
face of the chip. Therefore, the isolated
chip ;s actually 7 mils (0.17 mm) larger
in both dimensions.
___________________________________________________________________ 241
CA3141E
~ AMBIENT TEMPERATURE (TAI-25-C
::e 2.5 \VF,-VF2\'\"'-"'\'~"-V..\
I IVF7VF.I'IV...-',o\
~~ •
r~ ,1'1"; ';'i; '0" .... ·.,i ,
,
I 0.' 1/ .1::1";;;; ;1';;
,,;];""1'
~ !!! . ,I;;;;;;;' , .
0
l 468 l 4 68 , • '8 , • '8 2 4 68 !!i ~~iIHr'j,
10 10 2 103 104 105 4
MAGNITUDE OF ANODE CURRENT(I:FAJ-pA CATHODE-lO-ANODE DC REVERSE VOLTAGE IVRI-Y ANOOE-TO-SUBSTRATE DC REYERSE YO..TAGE evw-v
92CS-27176 92C5-27177 '2CS-2Tt78
Fig. 4 - Diode offset voltage vs. magnitude of Fig. 5 - Diode capacitance v&. cathode-ta- Fig. 6 - Diode anode-ta-substrate capacitance
anode current. anode reverse voltage. vs. reverse voltage.
'0 t=
,-
"!I0 4 t
~
Zl03
,- DIODE -TO- SUBSTRATE
LEAKAGE CURRENT V
~ := /
~
Y,o'
, Iv l/
~
~
~IO
2-
:~
1/ -\
g !~
, 'r
v:: V- DIODE REVERSE
(LEAKAGE)CURRENT
0., 'f- .... ~ ,.0
0.01 2 4 686.1 2 4 6 8 I 2 4 681'0
FORWARD (ANODE),CURRENT U:F)-mA
2 4 68 -'00 -50 o 50 100
AMBIENT TEMPERATURE (TA)--C
,zeS-27181
92C$' 271 79
Fig. 8 - Forward (cathode) current liS. forward Fig. 9 - DC leakage current vs. ambient
Fig. 7 - Diode cathode-to-substrate capacitance vs.
. (anode) current temperature.
cathode-to-substrate DC reverse IID/tage.
__________________________________________________ ~------------------243
CA3l60, CA3l60A, CA3l60B Types
MAXIMUM RATINGS, Absolute-Maximum Values CIRCUIT DESCRIPTION
TEMPERATURE RANGE:
DC SUPPLY VOLTAGE Fig.3 is a block diagram of the CA3160
(Between V+ and V- Terminals) . . . . . . .. 16 V OPERATING IAII Types). -55 to +1250 C
series COS/MaS Operational Amplifiers. The
DIFFERENTIAL-MODE STORAGE (All Types) ..... -65 to +150oC
INPUT VOLTAGE .................. ±8 V input terminals may be operated down to
COMMON-MODE DC OUTPUT SHORT·CIRCUIT 0.5 V below the negative supply rail, and
INPUT VOLTAGE ... IV+ +8 V) to (V- -0.5 V) DURATION* ................ INDEFINITE the output can be swung very close to
INPUT-TERMINAL CURRE~JT ......... 1 mA LEAD TEMPERATURE either supply rail in many applications. Con-
DEVICE DISSIPATION: IDURING SOLDERING):
WITHOUT HEAT SINK- sequently, the CA3160 series circuits are ideal
UP TO 55°C ................... 630 mW AT DISTANCE 1/16 ± 1/32 INCH for single-supply operation. Three class A
ABOVE 55°C .... Derate linearly 6.67 mW/oC 11.59±0.79MM) FROM CASE amplifier stages, having the individual gain
WITH HEAT SINK - FOR 10 SECONDS MAX ........... +265°C capabil ity and current consumption shown
AT 125°C... ....... ..... ...... 418 mW
BELOW 125°C ... Derate linearly 16.7 mW/oC *Short circuit may be applied to ground or to either in Fig.3, provide the total gain of the CA3160.
supply, A biasing circuit provides two potentials for
common use in the first and second stages.
Terminals 8 and 1 can be used to supplement
the internal phase compensation network if
additional phase compensation or frequency
ELECTRICAL CHARACTERISTICS at TA=25 0 C, V+=15 V, V- = 0 V (Unless otherwise specified)
roll-off is desired. Terminals 8 and 4 can also
LIMITS be used to strobe the output stage into a low
CA3160B (T, S) CA3160A (T, S, E) CA3160 (T, S, E) Units quiescent current state. When Terminal 8 is
CHARACTERISTIC tied to the negative supply rail (Terminal 4)
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max by mechanical or electrical means, the out-
Input Offset Voltage, put potential at Terminal 6 essentially rises
IVlol, V±=±7.5 V
- 0.8 2 - 2 5 - 6 15 mV to the positive supply-rail potential at Ter-
minal 7. This condition of essentially zero
Input Offset Current, current drain in the output stage under the
11101, V±=±7.5 V
- 0.5 10 - 0.5 20 - 0.5 30 pA
strobed "OFF" condition can only be a-
chieved when the ohmic load resistance pre-
Input Current, II
- 5 20 - 5 30 - 5 50 pA sented to the amplifier is very high (e.g.,
V±=±7.5 V when the amplifier output is used to drive
Large·Signal Voltage 100 k 320 k - 50 k 320 k - 50 k 320 k - VN COS/MaS digital circuits in comparator
Gain, AOL applications) .
VO=10V p _p , RL=2kH 100 110 - 94 110 - 94 110 - dB Input Stages - The circuit of the CA316U is
Common-Mode shown in Fig.l. It consists of a differential-
86 100 - 80 95 - 70 90 - dB input stage using PMOS field·effect tran-
Rejection Ratio,CM R R
sistors (06, 07) working into a mirror-pair
Common·Mode Input· -0.5 -0.5 -0.5 of bipolar transistors (09, 010) functioning
Voltage Range, V'ICR 0 to 10 0 to 10 0 to 10 V as load resistors together with resistors R3
12 12 12 through R6. The mirror-pair transistors also
Power-Supply Rejection function as a differential-to-single-ended con-
verter to provide base drive to the second-
Ratio,/WIOIb.V± - 32 100 - 32 150 - 32 320 /lVN stage bipolartransistor (all). Offset nulling,
V±=±7.5 V when deSired, can be effected by connecting
Maximum Output a 100,000-ohm potentiometer across Terms.
Voltage: 1 and 5 and the potentiometer slider arm to
Term. 4. Cascade-connected PMOS tran-
At RL=2 kS! YOM
+ 12 13.3 - 12 13.3 - 12 13.3 - sistors 02, 04, are the constant-current source
YOM 0.002 0.01 - 0.002 0.01 0.002 0.01 for the input stage. The biasing circuit for the
V
+ 14.99 15 - 14.99 15 - 14.99 15 - constant-current source is subsequently de-
At RL= ~ YOM
scribed. The small diodes D5 through D7
YOM 0 - 0.01 - 0 0.01 0 0.01
provide gate-oxide protection against high-
Maximum Output voltage transients, e.g., including static elec-
Current: tricity during handling for 06 and 07.
10M + (Source) @ Second-Stage - Most of the voltage gain in
Vo = 0 V 12 22 45 12 22 45 12 22 45 the CA3160 is provided by the second am-
mA plifier stage, consisting of bipolar transistor
10M (Sink) @ all and its cascade-connected load resistance
Va = 15 V 12 20 45 12 20 45 12 20 45 provided by PMOS transistors 03 and 05.
Supply Current, I The source of bias potentials for these PMOS
VO=7.5V,RL=~ - 10 15 - 10 15 - 10 15
mA
transistors is described later. Miller Effect
compensation (roll off) is accomplished by
VO=OV,RL=~ - 2 3 - 2 3 - 2 3 means of the 30-pF capacitor and 2-kH
Input Current, II' - Fig.l1 15 - [Link] - - [Link] nA resistor connected between the base and
collector of transistor all. These internal
Input Offset Voltage components provide sufficient compensation
Temp. Drift, - 5 15 - 6 - - 8 - /lV/oC for unity gain operation in most applications.
LWIO/b.T' However, additional compensation, if desired,
Large-Signal Voltage 50 k 320 k - - 320 k - 320 k V/V may be used between Terminals 1 and 8.
Bias-Source Circuit - At total supply volt-
Gain, AOL 94 110 - - 110 - - 110 - dB ages, somewhat above 8.3 volts, resistor R2
and zener diode Zl serve to establish a volt-
age of 8.3 volts across the series-connected
___________________________________________________________________ 245
CA3160, CA3160A, CA3160B Types
r---------------------.., v+
I
I 200 ~A
I
I
I
I
I
10 102 103 104 I' 6
FREQUENCY (f}-Hz
OFFSET
NULL
TOTAL SUPPLY VOLTAGE (FOR INDICATED VOLTAGE GAINS) v .,!5
* WITH INPUT TERMINALS BIASED SO THAT TERM.6 POTENTIAL 92CS- 28573 FigA - [Link] voltage gain and phase shift
IS +7.~ V ABOVE TERM. 4.
VB. frequency for various values of CL
"WITH OUTPUT [Link] DRIVEN TO EITHER SUPPLY RAIL.
Fig. 3 - Block diagram of the CA3160 Series.
and RL.
-100 -50 0
AMBIENT TEMPERATURE CTA'-
, so
oc
I '00
"
~
GATE VOLTAGE (VG I [TERMS 4
I~
a
17.5
8J-V
20 22.
, ,
TOTAL SUPPLY VOLTAGE (V+)-V
Fig.5 - Open-loop gain VS. temperature. Fig.6 - Voltage transfer characteristics of Fig.7 - Quiescent supply current vs. supply voltage.
COS/MOS output stage.
Z 4'1 24" 2 48' 2 "II' • 48. 2 .. , . 24'1 2 .. , . 2 .. ' . 2 .. "
~ 6 8 ~ 12 14 16
0.001 0.01 0.1 I 10 '00 0001 0.01 0.1 I 10 100
TOTAL SUPPLY VOLTAGE 1'1+1-'1
MAGNITUDE OF LQADCURR£NT tILI-mA MAGNITUDE OF LOAD CURRENT fILI- mA
Fig.S - Quiescent supply current VB. wpp/y voltage Fig.9 - Voltage across PMOS output transistor Fig. 10 - Voltage across NMOS output transistor
at several temperatures. (081 vs. load current. (0121 vs. load current.
1000& AMBIENT TEMPERATURE (TA)·~·C
2 .. 68'0 Z 468,022 468,032 "68'0" 2 .. 68'05
I 1/
-80 -60 -40 -20 0 20 40 60 80 100 120 140
FREQUENCY (f)-Hz 92(5-24157, INPUT CURRENT I.:IT)- pol [Link] TEMPERATURE (TAI-·C
Fig. I I - Equivalent noise voltage 1fS. frequency. Fig. 12 - Input current vs. common-mode voltage. Fig. 13 - Input current vs. ambient temperature.
_______________________________________________________________ 247
CA3160, CA3160A, CA3160B Types
This characteristic is due to the fact that TYPICAL APPLICATIONS 9-Bit COS/MOS DAC
reactance of the input capacitance becomes a Voltage Followers A typical circuit of a 9-bit Digital-to-Analog
significant factor in shunting the source Converter (DAC)* is shown in Fig.19. This
Operational amplifiers with very high input
resistance. It should be noted, however, that system combines the concepts of multiple-
resistances. like the CA3160, are particularly
for values of source resistance very much switch COS/MaS IC's. a low-cost ladder
suited to service as voltage followers. Fig.17
greater than 1 megohm, the total noise network of discrete metal·oxide-film resis-
voltage generated can be dominated by the shows the circuit of a classical voltage
follower, together with pertinent waveforms tors, a CA3160 op amp connected as a
thermal noise contributions of both the follower, and an inexpensive monolithic regu-
feedback and source resistors. using the CA3160 in a split·supply config-
uration. lator in a simple single power-supply arrange-
ment. An additional feature of the DAC is
A voltage follower. operated from a single·
that it is readily interfaced with COS/MaS
supply, is shown in Fig.18 together with
+7,' V input logic, e.g., 10-volt logic levels are used
related waveforms. This follower circuit is
in the circuit of Fig.19.
linear over a wide dynamic range, as illus-
trated by the reproduction of the output
waveform in Fig.18b with input-signal ramp- The circuit uses an RI2R voltage-ladder net-
ing. The waveforms in Fig.18c show that work, with the output-potential obtained
directly by terminating the ladder arms at
the follower does not lose its input-to-
output phase-sense, even though the input is either the positive or the negative power-
being swung 7.5 volts below ground poten- supply terminal. Each CD4007A contains
tial. This unique characteristic is an important
three "inverters", each Uinverter" function~
ing as a single-pole double-throw switch to
attribute in both operational amplifier and
terminate an arm of the R/2R network at
comparator applications. Fig.18c also shows
either the positive or negative power-supply
the manner in which the COS/MaS output
terminal. The resistor ladder is an assembly
stage permits the output signal to swing down
BW(-3dBl=200 11Hz Ikn of one per cent tolerance metal-oxide film
TOTAL NOISE VOLTAGE (REFERRED
TO INPUTl-40I'V TYP,
to the negative supply·rail potential (i.e., resistors. The five arms requiring the highest
ground in the case shown). The digital-to- accuracy are assembled with series and para-
92:CS-Z8!177
analog converter (DAC) circuit. described in llel combinations of 806,OOO-ohm resistors
the following section, illustrates the practical from the same manufacturing lot.
Fig. 16 - Test-circuit amplifier (3o-dB gain) used use 01' the CA3160 in a single·supply voltage-
for wideband noise measurements. follower application.
A single 15-volt supply provides a positive
bus for the CA3160 follower amplifier and
feeds the CA3085 voltage regulator. A
+7e v
"scale-adjust" function is provided by the
regulator output control, set to a nominal
10-volt level in this system. The line-voltage
regulation (approximately 0.2%) permits a
9-bit accuracy to be maintained with varia-
JOkn
tions of several volts in the supply. The
I flexibility afforded by the COS/MaS building
I blocks simplifies the design of DAC systems
,I tailored to particular needs.
-[Link]
1.
-=-
i?M~ATED LOAD
CAPACITANCE Error-Amplifier in Regulated Power Supplies
The CA3160 is an ideal choice for error-
amplifier service in regulated power supplies
BW (-3 dBI: 4 MHz since it can function as an error-amplifier
SR; 10 VII's
[Link].F when the regulated output voltage is re-
92CS-28578 quired to approach zero.
(a)
The circuit shown in Fig.20 uses a CA3160
as an error amplifier in a continuously ad-
justable I-ampere power supply. One of the
key features of this circuit is its ability to
regulate down to the vicinity of zero volts
with only one de power supply input.
An RC network, connected between the base
of the output drive transistor and the input
voltage, prevents "turn-on overshoot", a
condition typical of many operativ.,al-ampli-
fier regulator circuits. As the amplifier be-
comes operational, this RC network ceases
to have any influence on the regulator per-
formance.
(b) Small Signal Response
Ie) Input-Output Difference Signal Showing
Top Trace: Output
Bottom Trace: Input Settling Time
Top Trace: Output Signal
Center Trace: Odference Signal 5 m VIdiv
Bottom Trace: Input Signal * "Digital·to~Analog Conversion Using the RCA·
CD4007 A COS/MaS I Cu. Appl ieation Note
Fig. t 7 - Split-supplV voltage follower with associated waveforms. ICAN-6080.
______________________________________________________________ 249
CA3160, CA3160A, CA3160B Types
INPUT
...V
OUTPUT
ov .. :ssv
AT I AMPERE
0.2,,'
2.41Ul
T'I1/'
.W DELAY
.3OA
.56pF
.OA
HUM AND NOtSEOUTPUTc2!50"V .... S:
500A REGULATION (NO LOAD TO FULL LOAD'
< [Link]!i .. :
SZk4 INPUT REGULATION c 0·01 "IV
100K4
Fig.20 - Voltage regulator circuit (0.1 to 35 Vat 1 A).
Precision Voltage-Controlled Oscillator condition is accomplished by feeding an out· signal, the circuit consumes somewhat less
The circuit diagram of a precision voltage- put signal from terminal 6 of A2 through R4, than 500 microamperes plus the meter cur-
controlled oscillator is shown 'in Fig.21. The D4 to the inverting terminal (terminal 2) rent required to indicate a given voltage.
oscillator operates with a tracking error in the of A1, thereby adjusting the multi vibrator Thus, at full·scale input, the total supply
order of 0.02 percent and a temperature co- interval, T3. current rises to slightly more than 1500
efficient of [Link]%/oC. A multivibrator microamperes.
(A1) generates pulses of constant amplitude
(V) and width (T2l. Since the output Voltmeter With High Input Resistance Function Generator
(terminal 6) of Al (a CA3130) can swing The voltmeter circuit shown in Fig.22 il-
within about 10 millivolts of either supply- A function ,generator having a wide tuning
lustrates an application in which a number range is shown in Fig.23. The adjustment
rail, the output pulse amplitude (V) is of the CA3160 characteristics are exploited.
essentially equal to V+. The average output range, in excess of 1,000,000/1, is accom-
Range-switch SW1 is ganged between input
volt~ge (E,avg ,= V T2/T1) is applied to the
plished by a single potentiometer. Three
and output circuitry to permit selection of
non-onvertong onput [Link] of comparator operational amplifiers are utilized: a CA3160
the proper output voltage for feedback to
as a voltage follower, a CA3080 as a high·
A2 via an integrating network R3, C2. Terminal 2 via 10 Kn current·limiting re-
Comparator A2 operates to establish circuit speed comparator, and a second CA3080A
sistor. The circuit is powered by a single
conditions such that Eavg = V1. This circuit 8.4-volt mercury battery. With zero input as a programmable current source. Three
variable capacitors C1, C2, and C3 shape
the triangu lar signal between 500 kH z and
1 MHz. Capacitors C4, C5, and the trimmer
vea CONTROL VOLTAGE (Vi) po~entiometer in series with C5 maintain
(O-IOV) essentially constant (±10%) amplitude up
(SENSITIVITY= IkHz/VOLTi
to 1 MHz.
'OK .M
Staircase Generator
R' Fig.24 shows a staircase generator circuit
'OOK
utilizing three COS/MOS operational ampli-
fiers. Two CA3130's are used; one as a
•6
multivibrator, the other as a hysteresis switch .
1001( The third amplifier, a CA3160, is used as a
linear staircase generator.
03 Picoammeter Circuit
182K Fig. 25 is a current·to-voltage converter can·
o. figuration utilizing a CA3160 and CA3140
01 - 05 = IN914 31< to provide a picoampere meter for ±3 pA full-
scale meter deflection. By placing Terminals
F;g.21 - Voltage~contro/Jed oscillator. 2 and 4 of the CA3160 at ground potential,
__ ~ ____________________________________________________________ 251
CA3160, CA3160A, CA3160B Types
$.IKO 1"914
output (Terminal 6) near ground, thus mar-
kedly reducing the dissipation by reducing
+ I!!tV the supply current to the device.
100 The CA3140 stage serves as a Xl00 gain
." stage to provide the required plus and minus
output swing for the meter and feedback
100
network. A 100-to-l voltage divider network
." consisting of a 9.9-Kn resistor in series with
a 100-ohm resistor sets the voltage at the
10-KMn resistor (in series with Terminal 3) to
±30 mV full-scale deflection. This 30-mV
signal results from ±3 volts appearing at the
top of the voltage divider network which
IIIIULTIVIIRATOR RETRACE INHIIIT
also drives the meter circuitry_
DlKA
By utilizing a switching technique in the
+lDmVTO+IOV
IOOKA
meter circuit and in the 9.9 Kn and 100-ohm
network similar to that used in voltmeter
circuit shown in Fig. 22, a current range of
(a)
3 pA to 1 nA full scale can be handled with
the single 10- KMn resistor.
Single-Supply Sample-and-Hold System
Fig. 26 shows a single-supply sample-and-hold
system using a CA3160 to provide a high
input impedance and an input-voltage range
of 0 to 10 volts. The output from the input
buffer integrator network is coupled to a
CA30BOA. The CA30BOA functions as a
strobeable current source for the CA3140
output integrator and storage capacitor. The
CA3140 was chosen because of its low out-
put impedance and constant gain-bandwidth
product. Pulse "droop" during the hold
9ZCSM28596 interval can be reduced to zero by adj usting
(b) - Staircase Generator Waveform the l00-Kn bias-voltage potentiometer on
Top Trace: Staircase Output the positive input of the CA30BOA. This
2 Volt Steps zero adjustment sets the CA30BOA output
Center Trace: Comparator voltage at its zero current position. In this
Bottom Trace: Osciflator sample-and-hold circuit it is essential that the
amplifier bias current be reduced to zero to
Fig. 24 - Staircase generator. minimize output signal current during the
hold mode. Even with 320 mV at the ampli-
fier bias circuit terminal (5) at least ± 100 pA
of output current will be available.
Wien Bridge Oscillator
A simple, single-supply Wien Bridge oscil-
lator using a CA3160 is shown in Fig_ 27_
A pair of parallel-connected 1 N914 diodes
comprise the gain-setting network which
standardizes the output voltage at approxi-
mately 1.1 volts_ The 500-ohm potentiometer
is adjusted so that the oscillator will always
start and the oscillation will be maintained.
Increasing the amplitude of the voltage 'may
lower the threshold level for starting and for
5.61U1 sustaining the oscillation, but will introduce
more distortion.
lOOn
Operation with Output-Stage Power-Booster
The current sourcing and sinking capability
of the CA3I60 output stage is easily supple-
92CN·Z8589RI
mented to provide power-boost capabi lity.
In the circuit of Fig.2B, three COS/MaS
Fig.25 - Curren t-to-voltage converter to pro vide a picoammeter transistor-pairs in a single CA3600 IC array
with ± 3 pA full·scale deflection. are shown parallel-connected with the output
stage in the CA3160. In the Class A mode of
CA3600E shown, a typical device consumes
________________________________________________________________ 253
CA3160, CA3160A, CA3160B Types
IN~II---J\Mr1-<
1
I ~F
500
.on
100 mW
-=' AT [Link]·
A-20 dB
LARGE SIGNAL
8W(-3dS-I90 KHz
20 KG
NOTE: ·SEE FILE NO. 619
TRANSISTORS pi, p2, p3 AND nl,n2, n3 ARE
PARALLEL. - CONNECTED WITH 08 AND 012,
RESPECTIVELY, OF THE CA3160
92CN-28592
Fig.28 - COS/MOS transistor arrBY (CA3600E) connected as power
booster in the output stage of the CA3160.
55-63
(1.397-1$001
66-74
11157-1.8791 .~-J
I
J
Dimensions in parentheses are in millimeters and The photograph and dimensions represent a chip
are derived from the basic inch dimens~ns as when it is part of the wafer. When the wafer is cut
indicated. Grid graduations are in mils (10- inch). into chips the cleavage angles are 57'1 instead of
9t1' with respect to the face of the chip. Therefore,
the isolated chip is actually 7 mils (0.17 mm)
larger in both dimensions.
___________________________________________________________________ 255
CA3181E
TRUTH TABLE
BINARY INPUTS OUTPUTS DISPLAY
STATE ~ 22 21 2!l a b c d e f g
0 L L L L L L L L L L H
0
1 L L L H H L
.
L H H H H
I
2 L L H L L L H L L H L
2
3 L L H H L L L L H H L
3
4 L H L L H L L H H L L
Y
5 L H L H L H L L H L L
5
6 L H H L L H L L L L L
6
7 L H H H L L L H H H H
1
8 H L L L L L L L L L L
B
9 H L L H L L L L H L L
'3
10 H L H L H H H H H H L
-
11 H L H H L H H L L L L
E
12 H H L L H L L H L L L
H
13 H H L H H H H L L L H
L
14 H H H L L L H H L L L
P
15 H H H H H H H H H H H BLANK
__________________________________________________________________ ~7
CA3162E
MAXIMUM RATINGS, Absolute-Maximum Values: that the multiplex rate is unchanged_ Fig. 3
DC SUPPLY VOLTAGE (between terminals 7 and 141_ . +7 V shows the timing of conversion and digit
INPUT VOLTAGE (terminall00r 11 to ground I ±15V select pulses for the high-speed mode. Note
DEVICE DISSIPATJDN: that the basic AID conversion process requires
Up to T A - +55:: _ . . . .. 750mW approximately 5 ms in both modes_
AboveT A =+55 C . derate linearly at 7.9 mW/oC The "EEE" or " ___ " displays indicate that
AMBIENT TEMPERATURE RANGE:
the range of the system has been exceeded in
Operating. . 0 to +75°C
the positive or negative direction, respec-
Storage -65 to +150o C
LEAD TEMPERATURE (DURING SOLD,ERINGl:
tively. Negative voltages to -99 mV are dis-
At distance 1/16 ± 1/32 inch (1.59 ± 0/79 mml from case for 10 seconds max. +265°C played with the minus sign in the MSD. The
BCD code is 1010 for a negative overrange
(___ ) and 1011 for a positive overrange
v+ BCD OUTPUTS (EEE).
I
System Application
: }OIGIT SELECT
@-MSD
OUTP~ Fig. 2 is the block diagram of a basic system
L -___ -'"--t..... (V-LSD
using the CA3162E and the CA3161E_ An
actual-size PC board layout for this circuit
G)-NSD
is shown in Fig. 4. The BCD outputs of the
HIGH INPUT II
CA3162E drive the BCD inputs of the
CA3161E BCD-to-7-segment decoder directly.
The seven-segment outputs are multiplexed
CONVERSION to the three LED displays. The digits are
6 CONTROL
selected by terminals 3, 4, and 5 (CA3162EJ.
which provide base current to the external
7 GND
p-n-p transistors_ The p-n-p's, in turn, provide
if-
MSO-MOST SIGNIFICANT DIGIT current to the anodes of the display. Adjust-
NSO" NEXT SIGNIFICANT DIGIT 92CM-30414RI
LSD" LEAST SIGNIFICANT DIGIT ment procedures for the gain and zero
potentiometers are given in Note 1 of the
GAIN
ADJ Electrical Characteristics chart_
Fig. 1 - Functional block diagram of the CA3162E.
<.v
...
TE ...
12
r ---. -
zoo"'"
.........
O!LSD
- _J IlOO mY
41110DJ
NORMAL
LOW-SPEED ..-ODE:
L_ ---I 11-'OOOmY
"'6
HOLD:
''lfROtJ=~N
V6" 12 II
..... J !:Il,Il00"'''
2 ml/DIVISlON
,2CS-I0411ft1
Fig. 3 - High speed mode timing diagram •
.,
I>on
. •2
150n ••"'>1'
CA3162E CA3162E
TERMINALS TERMINALS 92CL.- 30418RI
~ ~
"4'~Kn 1'2"5,[Link]
*-FAIRCHILD FNO'070R EQUIVALENT
DIGIT
SEGMENT
=ORIVF:R DRIVERS
Fig. 2 - Basic digital readout system using the CA3162E and
the CA3161E_
_____________________________________________________________________ 259
CA3182E
+5.
CA3162E Liquid Crystal Display (LCDI
,.
1
Application
Fig. 6 shows the CA3l62E in a typical LCD
application. LCD's may be used in favor of
LED displays in applications requiring lower
power dissipation, such as battery·operated
.ov ·CD409.
2 m-
OF LCD
equipment, or when visibility in high·ambient·
light conditions is desired.
Multiplexing of LCD digits is not practical,
since LCD's must be driven by an ac signal
and the average voltage across each segment is
zero. Three CD4056B liquid·crystal decoder/
drivers are therefore used. Each CD4056B
:CD~6B }m_ OF LCD
contains an input latch so that the BCD data
for each digit may be latched into the decoder
t
using the inverted digit·select outputs of the + ••
CA3l62E as strobes. ,.
Inverters Gl and G2 are used as an astable
multivibrator to provide the ac drive to the
LCD backplane. Inverters G3, G4, and G5 are
the digit·select inverters and require pull·up
GI-G6·C004049ua
4
•
CD40~B
mo"
OF LCD
resistors to interface the open·collector out· HEX INVERTER
• 1
puts of the CA3l62E to COS/MOS logic. G7- G8: C040llUB
TO LCD
QUAD 2-INPUT NAND
The BCD outputs of the CA3l62E may be BACKPLANE
connected directly to the corresponding
CD4056B inputs (using pull·up resistorsl. In
this arrangement, the CD4056B decodes the
negative sign (-I as an "L" and the positive
overload indicator (EI as an "H".
92CL- 31016
CA3162E Common·Cathode, LED Display
Application Fig. 6 - Typical LCD application.
Fig. 7 shows the CA3162E connected to a
CD45ll B decoder/driver to operate a com·
mon·cathode LED display. Unlike the
CA3l6l E, the CD45ll B remains blank for
all BCD codes greater than nine. After
999 mV the display blanks rather than dis·
playing EEE, as with the CA3l61E. When
,-----
I
- - - - - - -------,
I/8CD404tUI
110- I
displaying negative voltage, the first digit reo CD+OIU I
mains blank instead of (-I. and during a
negative overrange the display blanks. I I
I
The additional logic shown within the dotted
area of Fig. 7 restores the negative sign (-I,
I I
allowing the display of negative numbers as
L_ ~
low as -99 mV. Negative overrange is indio
v·
cated by a negative sign (-I in the MSD [Link] HP5082-M3I
OR EQUIVALENT
position. The rest of the display is blanked. 1.21CA
During a positive overrange, only segment b of , '"
the MSD is displayed. !.IKA
111111
. ..
I II IU
Fig. 7 - Typical common-cathode LED application.
___________________________________________________________________ 261
CA3164E
ELECTRICAL CHARACTERISTICS at T A = 25°C, V+ = 9 V Connections for Optional Functions
LIMITS 1. Low Battery Adjustment - Terminal 5
CHARACTERISTIC TEST CONDITIONS UNITS
Min. Typ. Max. Add diodes as shown below to increase the
the low·battery trigger point.
Operating Voltage 7 9 11 V
Common·Mode Input
Voltage Range, VICR
(V+ -2 V) = 7 V 0 - 7 V v+~
~
Low·Battery Trigger External adjust
Voltage (increase onlv) 7.3 7.7 7.9 V
Horn Driver Term. 8 = 100 mA - 0.5 - V
VCE(SAT) Term. 8 - 300 mA - 1 -
Reference Voltage 5.8 6.2 6.6 V 2. Sounder Operating Mode
Input Leakage Term. 2 - - 1 Continuous sound on alarm - connect
Current, IL Term. 2 at 50 C - - 2.5 pA terminal 11 to V+.
Term. 3 - 50 Pulsed sound on alarm - connect resistor
No LED connected - 8* 12 between terminal and ground.
Standby Current (13 MO LED connected-20 mA 3. Remote (Interconnect)
for 30 ms every 60s - 18 -
from Term. 4 to gnd) IlA Connect terminal 12 to same terminal on
Photoelectric operation - - 13
all other units (fan out = 20 units). When
LE 0 photocurrent = 0.6 A
15 sec. ratel interconnecting units for the remote·alarm
function, ,the extremely low currents in·
Reference Source Current 5 - - JJ.A valved make it extremely important that
LED Driver Sink Current 40 50 - mA a provision be made for limiting externally
Interconnect Current induced transients into the remote termi·
Source ISink = 10 IlA typo - 2.8 - mA al. For example, inadvertent contact with
external power sources or electrical storm
Sink ISource = 1.3 mA typo - 50 - IlA activity may cause triggering of the remote
Low·Battery Adjust, Term.5 alarm function. The circuit below will re-
Input Current 50 70 100 nA
duce the possibility of such occurences.
Timing Current Term. 13 10 - 50 nA
LED Blink Period Adjustable - - 1 PPM IkG
LED Pulse Width Fixed - 30 - ms TO OTHER
Remote Fan·Out 20 - - DETECTORS
Alarm Pulse Duty Cycle On·time - 95 - %
(4.7 MO from Term. II On·time = 95% - 0.5 - sec. 92CS-31023
to gnd Off·time - 5% - 0.026 -
• Adj ustable to 5 /loA
4. LED On·Time Adjustment
Option 1: The CA3164E is designed to
provide a fixed LED on-time of approxi-
mately 30 ms. For applications requiring
OPERATING MODES TRUTH TABLE a reduction in on·time the following cir·
Alarm cuit is recommended:
Smoke Low Led Alarm Systam Remote
Condition Ionization Battery 6 Enable Unit
Horn Interconnect
Chamber Pulser Status
~
8 12 :LTAGE AT TERMS
11
Normal No No Blink Off X Low Off 470kil
No Ves ov
Low Battery Blink Beep X Low Off
Smoke In Chamber Ves X On Pulsed* Resistor High On 20mA
ILED
to ground
External Input A1 j I--'m.
From Remote Unit No No Blink On" High High On
•• Alarm Horn follows mode programmed for internal system input. For ekample, if terminal 11 has
resistor connected to ground, horn will beep. If terminal 11 is connected to V+. horn will be "on." :x>----+ TO MECH. HORN
X = Don't Care 92CS-31024
Blink & Beep = 30 msec (fixed) every 50 sec (AOJ)
Pulsed = 95% "on" time - Period is determined by resistor from terminal 11 to ground-5% Off Time This circuit reduces the LED on-time but
* Horn "Continuous" if terminal 11 is connected to V+ does not affect the horn on·time of 30 ms.
When using this configuration during the
continuous·alarm mode (smoke in cham·
ber! the LED will be off instead of on, as
shown in the truth table. If the horn is
pulsed during the alarm mode, the LED
will blink at the pulse rate.
___________________________________________________________________ 263
CA3240, CA3240A Type.
Dual SiMOS Operational Amplifiers TOP VIEW
With MOS/FET Input. Bipolar Output
The RCA-CA3240A and CA3240 are dual Features:
versions of the popular CA3140-series inte- Ii Dual version of CA3140 N,[tSfe"1 !I
grated circuit operational amplifiers. They - Internally compensated I=T~':.\/) e. >-"T"--"""
combine the advantages of MOS and bipolar IN~~~(81 7
transistors on the same monolithic chip. The - MOS/FET input stage
gate-protected MOS/FET {PMOSI input tran-
sistors provide high input impedance and a
wide common-mode input voltage range
{al Very high input impedance (ZIN'- 1.5 Tn typ_
{bl Very low input current {l1'- 10 pA typo at ± 15 V
(c) Wide common-mode input-voltage range {VICR'-
..
*'PINS 9 AND 15 INTERNALLY
CONNECTED THROUGH APPAOX
El Suffix
(typically to 0.5 V below the negative supply can be swung 0.5 volt below negative supply-
rail)_ The bipolar output transistors allow a Pin compatible with the
wide 0.!Jtput voltage swing and provide a high voltage rail industry-standard 747
output current capability. {dl Rugged input stage - bipolar diode protected
The CA3240A and CA3240 are supplied in - Directly replaces industry types 747 and 1458 in
the 8-lead dual-in-line plastic package (Mini- most applications
DIP, E suffix). and in the 14·lead dual-in-line - Operation from 4-to-36 volts
plastic package {El suffixl. They are pin- single or dual supplies
compatible with the industry standard 747
and 1458 operational amplifiers in similar - Characterized for ± 15-volt operation and for
packages. The CA3240A and CA3240 have TTL supply systems with operation down to 4
an operating-temperature range of -40 to volts
+850 C_ The offset null feature is available - Wide bandwidth - 4.5 MHz unity gain at
only when these types are supplied in the
14-lead dual-in-line plastic package (El suf- ± 15 Vor30V
9tCS-30011
fixl. - High voltage-follower slew rate - 9 V IlJs
- Output swings to within 0.5 volt of E Suffix
negative supply at V+ a 5 V, V- .. 0 Pin compatible with the
industry-standard 1458
Fig. 7 - Functional diagram•.
Applications:
- Ground-referenced single-supply amplifiers
in automobile and portable instrumentation
- Sample and hold amplifiers
- Long-duration timers/multivibrators
{microseconds-min utes-hours)
- Photocurrent instrumentation
- Active filters - Intrusion alarm systems
- Comperators - Instrumentation amplifiers
- Function generators - Power supplies
Circuit Description
The schematic diagram of one amplifier
section of the CA3240 is shown in Fig. 2. It
consists of a differential amplifier stage using
PMOS transistors Q9 and 010 w"ith gate-to-
~ource protection against static discharge
damage provided by zener diodes 03, 04,
and 05. Constant current bias is applied to
the differential amplifier from transistors 02
and 05 connected as a constant-current
source. This assures a high common-mode
rejection ratio. The output of the differential
amplifier is coupled to the base of gain stage
transistor 013 by means of an n-p-n current
mirror that supplies the required differential-
y-
OFFSET NULL to-single-ended conversion. Provision for off-
ALL RESISTANCE \aLUES ARE IN OHMS. 92CL-:SOO'4 set null for types in the 14-lead plastic
• ONLY AVAILABLE WITH 14-LEAD DIP (£1 SUFFI)( I package {E! suffixl is provided through the
Fig. 2 - SchllfTNlticodiagrBm of one"'a/f CA3240 _ie•• use of this current mirror_
______________________________________________________________ 2~
CA3240, CA3240A Type.
TYPICAL ELECTRICAL CHARACTERISTICS 20 LOAD RESISTANCE {RL'- 2 110
LOAD CAPACIT~~CE (ell = 100 pF
TEST
TYPICAL VALUES
CONDITIONS
CHARA'CTERISTIC V+ = +15 V CA3240A CA3240 UNITS
V-= -15 V
TA = 25°C
Typ. Value of
Input Offset Voltage Resistor Between
Adjustment Resistor Terms. 4 and 18 4.7 kn
(El Package Only) 3(5) or Between
4 and 14(8) to II 10 15 20
Adjust Max. SUPPLY VOLTAGE IY·, V")- VOLTS
92CS-30018
VIO
Fig. 5 - Gain-bandwidth product lIS a function
Input Resistance Rl 1.5 1.5 Tn of supply voltage Bnd temperature.
Input Capacitance CI 4 4 pF
Output Resistance RO 60 60 n
Equivalent Wideband
BW=140 kHz
Input Noise Voltage en 48 48 Il V
RS = 1 Mn
(See Fig. 21 )
Equivalent Input
f= 1 kHz RS= 40 40
Noise Voltage en nV/v'"Hz
(See Fig. 10) f=10kHz lOOn 12 12
Short·Circuit Current to
Opposite Supply Source 10M + 40 40
mA , ,
Sink IOM- 11 11 SUPPLY V<lLTAGE IY+, V-l-YOLTS
92CS-50017
Gain·Bandwidth
Product 4.5 4.5 MHz Fig. 6 - Slew rate as B function of supply
fT
voltage and temperature.
(See Figs. 5 and 19)
Slew Rate SR
9 9 V/lls
(See Fig. 6)
Transient Response:
Rise Time RL=2 kn [Link] [Link] Ils
tr
Overshoot (See Fig. 20) CL =100 pF 10 10 %
Settling Time RL=2 kn
1 mV 4.5 4.5
at 10 Vp . p • t-;o";;;v ts CL =100 pF
1.4 1.4
Ils
(See Fig. 17) Voltage Follower
Crosstalk f = 1 kHz 120 120 dB
2
o '0 20
"
SUPPLY VOLTAGE{V+,V-I-V
Fig. 7 - Ouiescent supply current lIS a
function of supply voltBge and
temperature.
AMBIENT TEMPEltATUIIE IT..,)· m·c
> SUPPLY VOlTAGE, Y+-16 Y, Y-·-15 V ,120 ::l~T~J~,YU+Re!!!W.)~-;I5';'8V
I I
l~
~
~20
f\ IM>O
~'~~-+~r--~++B-'~H-~-+t+~++B-~~
i \ z
,
I.
!60
I" 1\
\
~ 4O~-+Ht~++B-H-f'Icl-+t++++B-~~
~~ • !\.
~ 0
, .. , . . , I............, 1 20
L-~O~,o~~~~~~~,~~-L~,,~.~~~~~~~,,~.~~,~
10 K 'OOK
FREQUENCY (f)-H~
•• FREQUENCY {f I - Hz:
10 lot
FREQUENCY (f) -
10'
Hz
,0' ,0'
92CS-30020
Fig. 8 - MaX1"mum output voltage swing Fig. 9 - Common~mode rejection ratio Fig. 10 - Equivalent input noise voltage
as a function of frequency. as a function of frequency. as a function of frequency.
__________________________________________________________________ 267
CA3240, CA3240A Type.
TYPICAL ELECTRICAL CHARACTERISTICS FOR DESIGN GUIDANCE
~
'i~
AtV+=5V, V-=OV, TA=250 C
TYPICAL VALUES
CHARACTERISTIC
CA3240A CA3240
UNITS "---
j-
~~T.. ui VOLTAGE i-i-;
:INPUl
Input Offset Voltage, 2 5 mV
IVlol iz_ ,',';"""
,::wc
r~
Input Offset Current, 11101 0.1 0.1 pA ,·.~~~~~"U"E
Input Current, II 2 2 pA
Input Resistance 1 1 Tn
Large-Signal Voltage Gain,
(See Figs. 4,19)
AOL lOOk
100
100 k
100
V/V
dB ~ -.~~ .. ')""
Common-Mode Rejection Ratio, CMRR 32 32 pV/V
90 90 dB I~
Common-Mode Input-Voltage -0.5 -0.5
Range, VICR V
(See Fig. 22) 2.6 2.6
~~
Power-Supply Rejection Ratio, PSRR 31.6
90
31.6
90
pVN
dB
II r.~
Maximum Output Voltage, VOM
+ 3 3 II
I~·
V
(See Figs. 16,22) VOM- 0.3 0.3
Maximum Output Current: I~
Source, IOM+ 20 20 . rnA 5 SUPPLY VOLTAGE (V.... ' 1_ V
Sink 1 Fig. 16 - Output-voltage-swing capability and
10M 1
common-mode input-voltage range
Slew Rate (See Fig. 6) 7 7 V/p.s as a function of supply voltage and
temperature.
Gain-Bandwidth Product, fT 4.5 4.5 MHz
(See Fig. 5)
Supply Current, 1+ 4 4 mA
(See Fig. 7) 10 K: SUPPLY VOLTAGE: Y+"15 Y, V-.-I& V
Device Dissipation, PD 20 20 mW /
YOLT~I
alPPLY ·.VI
~ENT TDI"'n. (T.J-U-C
y---. Y
---~
" I
~Y- ~:
.
~.
> I
! •
!•
i>5-1/
./ /
,- 1----
' ,"
~_""(""'.'"
........... _(~l
• .,.
I
~ 0
.....
-~ . ~'~
Joo-:
r's:f~
~ -80 -40 -20 0 ZO 40 10 eo 100 120 140
-. t-'
AaelENT TEMPERATURE (T.)--C 'UeS-2f",
-I
... , "\
. . .. . . .
Fig. 18 - Input current as a function of
m
-I
1\"\ ambient temperature.
-" '-
0.1 ID 10
Cal SETTLING TIME - ~
·.,.v,V-·-15 .lll\-:1. - 7S ::
FOLLOWER
INVERTING
• kn .roo SUPPLY VOLTAGE, V
AMBIENT TEMP£[Link] ITAI- 2a-c
<%
~
wu
V
.~~~
t. ~~
-IOn
-
f ~~~ I ..? \.
-""IIi
120
rJ
S ~.
- I.. -
; - lOCI 3
~IO ~-.~~ \.
~
~ <<Ie;
~40 ~~
Lo 11Ir-~-'0..
III I I
.,. ... .,. III 1111 "'-
&2CS-300Z.
10
" FREQUENCY (fl - Hz "" ", ""
C~l TES:r CIRCUITS Fig. 19 - Opan-loop IIOltsl/fll/flin and ph_lag
Fig_ 17 - Input voltage H a function of .ettling timB_ 81 8 function of frequency.
____________________________________________________________________ 269
CA3240, CA3240A Types
TYPICAL APPLICATIONS
OnlOff Touch Switch 1(7)
The on/off touch switch shown in Fig. 26
uses the CA3240E to sense small currents
flowing between two contact poi nts on a
touch plate consisting of a PC board metal-
lization "grid"_ When the "on" plate is
touched, current flows between the two
halves of the grid causing a positive shift in v-
the output voltage (Term_ 7) ofthe CA3240E_ v-
These positive transitions are fed into the a BASIC b IMPROVED c SIMPLER
RESOLUTION IMPROVED
CA3059, which is used as a latching circuit RESOLUTION
and zero-crossing triac driver_ When a positive * SEE CHARACTERISTICS CHART 92CS-30032
pulse occurs at Terminal 7 of the CA3240E, FOR VALUE R
the triac is turned on and held on by the
CA3059 and its associated positive feedback Fig. 25 - Three offset~voltage nulling meth'ids.
circuitry (5l-kn resistor and 36-kn/42-kn (CA3240AE1, CA3240E1 onlv.!
voltage divider). When the positive pulse
occurs at Terminal 1 (CA3240E), the triac is
turned off and held off in a similar manner.
Note that power for the CA3240E is supplied
by the CA3059 internal power supply.
44M
The advantage of using the CA3240E in this +6V --~vv----~--o ~
120V/2201/
circuit is that it can sense the small currents 60Ha/5OHz
associated with skin conduction while al-
lowing sufficiently high circuit impedance to
provide protection against electrical shock.
Dual Level Detector (window comparator!
Fig_ 27 illustrates a simple dual liquid level
detector using the CA3240E as the sensing
amplifier_ This circuit operates on the princi- + 6V
ple that most liquids contain enough ions in SOURCE
solution to sustain a small amount of current
44 M 92CM- 30005
flow between two electrodes submersed in
the liquid. The current, induced by an 0_5-V
potential applied between two halves of a
PC board grid, is converted to a voltag,e level
by the CA3240E in a circuit similar to that
of the on/off touch switch shown in Fig_ 26_
Fig_ 26 - On/off touch switch_
The changes in voltage for both the upper
and lower level sensors are processed by the
CA3l40 to activate an LED whenever the
liquid level is above the upper sensor or
below the lower sensor.
12M
Constant-Voltage/Constant-Current Power Supply
The constant-voltage/constant-current power
supply shown in Fig_ 28 uses the CA3240E
as a voltage-error and current-sensing ampli-
fier _The CA3240E is ideal for this application
because its input common-mode voltage-range
includes ground, allowing the supply to
adjust from 20 mV to 25 V without requiring
an additional negative input voltage_ Also,
the ground reference capabi Iity of the CA-
3240E allows it to sense the voltage across
the l-n current-sensing resistor in the nega-
tive output lead of the power supply. The
CA3086 transistor array functions as a refer-
ence for both constant-voltage and constant-
current limiting_ The 2N6385 power Darling-
ton is used as the pass element and may be
required to dissipate as much as 40 W. Fig. LOW
29 shows the transient response of the LEVEl 92CM- 30006
supply during a 1OO-mA to l-A load transi-
tion. Fig_ 27 - Dual level detector_
~
______________________________________________________________________ 271
CA3240, CA3240A Types
Differential Light Detector
In the circuit shown in Fig. 32, the CA3240E
converts the current from two photo diodes
to voltage, and applies 1 V of reverse bias to
the diodes. The voltages from the CA3240E
outputs are subtracted in the second stage
+ 15V
(CA3140) so that only the difference is
amplified. In this manner, the circuit can be
used over a wide range of ambient light
conditions without circuit component ad·
justment. Also, when used with a light source,
the circuit will not be sensitive to changes in
light level as the source ages. OUTPUT
'>...r.'~-A
1
RCA
C30B09
PHOTO
DIODE
TYPICAL ELECTROCARDIOGRAM WAVEFORM
92CM-30009
VERTICAL: [Link].
(AMPLIFIER GAIN .'OOX)
(SCOPE SENSITIVITY. [Link]/DIy.
HORIZONTAL: > 0.2 SECIDIY (UNCAL) Fig. 32 - Differential light detector.
9tCS-lOOll
Fig. 31 - Typical electrocardiogram waveform.
CA3240H Dimensions and Pad Lavout
The photographs and dimensions represent a chip
when it is part of the wafer. When the wafer is cut
into chips; the cleavage angles are 5.,0 instead of
goo with respect to the face of the chip. Therefore,
the isolated chip is lICtually 7 mils (0.17 mm)
larger in both dimensions.
Dimensions in parentheses Bre in millimeters and
are derived from the basic inch dimensions as in-
dicated. Grid graduations are in mils (70- 3 inchJ.
NOTE: NOS. IN PADS ARE FOA 14-lEAO DIP
NOS. OUTSIDE OF CHIP ARE FOR 8- LEAD DIP
________________________________________________________________ 273
CA3290, CA3290A, CA3290B
ELECTRICAL CHARACTERISTICS at TA = -55 to +1250 C 01 and 04 are operated with a constant cur-
rent load, their gate-to-source voltage drops
TEST VALUES will be effectively constant as long as the
CHARACTERISTIC CONDITIONS CA3290B CA3290A CA3290 UNITS input voltages are within the common-mode
V+ Typ. MaK. Typ. MaK. Typ. MaK. range. As a result, the input offset voltage
(VGS(Ol) + VBE(02)-VBE(03)-VGS(04)l
VIC=1.4 V 5V - will not be degraded when a large differential
In put Offset 3.5 4.5 - 8.5 - de voltage is applied to the device for ex-
VO=l.4 V
Voltage, V 10 mV tended periods of time at high temperatures.
VIC-O V,
±15 V 3.5 - 8.5 - 8.5 Additional voltage gain following the first
VO=O V
stage is provided by transistors 07 and oa.
Temp. Coefficient The collector of oa is open, offering the user
of Input Offset 8 - 8 - 8 - /J.V;oC a wide variety of options in applications. An
Voltage,L'. V lOlL'. T additional discrete transistor can be added if
it becomes necessary to boost the output
In put Offset VIC=l.4V 5V 2 22 2 28 2 32 sink-current capability.
nA
Current, 110 VIC=O V ±15 V 7 22 7 28 7 32 The detailed schematic diagram for one com-
parator and the common current-source
VIC=l.4V 5V 2.8 32 2.8 45 2.8 55 biasi ng is shown in Fig. 2. PMOS transistors
Input Current, II" nA Q9 through 012 are the current-source
VIC-O V ±15V 13 32 13 45 13 55
elements identified in Fig. 1 as 11 through 14,
5V 0.85 1'.6 0.85 1 0.85 1.6 respectively. Their gate-source potentials
Supply Current, 1+ " RL = 00 mA (VGS) are supplied by a common bus from
30V 1.62 3.5 1.62 3 1.62 3.5
the biasing circuit shown in the right-hand
150 - 150 - 150 - V/mV portion of the Fig. 2. The currents supplied
Voltage Gain, AOL RL=15kn ±15 V by 010 and 012 are twice those supplied by
103 - 103 - 103 - dB
Q9 and all. The transistor geometries are
V+=5 V, appropriately scaled to provide the requisite
Saturation +125 0 C 0.22 0.7 0.22 0.7 0.22 0.7 currents with common VGS applied to Q9
4 mA, V
Voltage +VI=O V, -55 0 C 0.1 - 0.1 - 0.1 - through 012.
-VI=l V
Output Leakage 15 V 65 - 65 - 65 -
nA
Current, 10L 36V 130 lk 130 lk 130 lk
"At T A = +12So C
"At TA = -55°C
I
I i&.PARATOR
NO.2
TOTAl.. SUPPLY [Link] I - v
Fig. 3 - SUpply current as a function
of supply voltage (both amplifiers).
-VIo--'-I--+--+---k~
Fig. 2 - Schemetic diagrem of CA3290
(only one is shown).
In essence, 01 and 04 function as source· transients (e.g., static electricity). The cur· INPUT COMMON-MOOE VOLTAGE (VIC)-V
followers to drive 02 and 03, respectively, rent flow in 01 and 02 is established at
with zener diodes 01 through D4 providing approKimately 50 microamperes' by constant- Fig. 4 - Input cu"ent /18 B function
gateO()Kide protection against input voltage current sources 11 and 13, respectively. Since of Input common-mode voltage_
___________________________________________________________________ 275
CA3290, CA3290A, CA3290B
ELECTRICAL CHARACTERISTICS AT TA = 2SoC
TEST LIMITS
t
,ov
··· j'
:l
I ~l ~i
~
~ 'v
If
CHARACTERISTIC CONDo
V+ Min.
CA3290
Typ. Max.
UNITS
~
~
· l
/.
;'OOrrN
..·
Input OffSet Voltage,
~
VIO VIC=l.4 V
SV - 7.S 20 ~
VO=l.4 V S IOmY +125-C ~
'-
VIC=O V
±lS V - 7.S 20
mV 5
~ ·q:~-~!
Input Curr~nt,
VO=O V
II
i!
,mY·
10fl-A
2 •• 1 I .. I ' I ....
IOOfl>~TPUT SI~m~URRENT_~~m.
VIC=l.4 V SV - 3.S 50 92CS-~
pA Fig. 9 - Output saturation vo/rage as B
VIC=O V ±lS V - 12 50
function of output sink cu"ent.
Input Offset Current, 110
VIC=1.4 V SV - 2 30
pA
VIC-O V ±lS V - 7 30
Common-Mode Input-
Voltage Range, VICR V'N C>-'-;'.i\'2tv-'-I
10 XIO SCOPE
V+-3.5 V+-3.1
VO=l.4 V 5V
V- V--1.5
- PROBE
V Ok
V+-3.8 V+-3.4
Vo=OV ±15 V
V- V--1.6
-
Supply Current, 1+ 30 V - 1.35 3
mA
RL = 00 SV - 0.8 1.4
Voltage Gain, AOL 25 BOO - V/mV
±15 V
RL=lSk!1 88 118 - dB
Output Sink Current
VO=1.4 V
5V 6 30 - mA
Saturation Voltage
WITH Cc
+VI=O V,
-VI=l V, SV - 0.12 0.4 V TOP TRACE IIJ4.5mVlDIY-YlN
BOTTOM TRACE -IOVlDIV· \louT
4mA H ·5,..,/DIV
Output Leakage Current, 15 V - 100 -
pA
IOL 36 V - 500 -
Response Time
RL=5.1 k!1 Rising Edge - 1.2 - IlS
15 V
Falling Edge - 200 - ns
Common-Mode Rejection ±15 V - 44 562
IlV /V
Ratio, CMRR SV - 100 562
Power·Supply Rejection
Ratio, PSRR
±lS V - lS 316 IlV /V WITHOUT Cc
TOP TRACE .. 4.5mVlOIV
Large-Signal Response BOTTOM TRACE· JOVlDIY
Time
15 V - SOO - H -S,../DIV
ns
RL=S.l k!1 5V - 400 - 92CM-30059
Fig. 10 - Paras;t;c~scillations test circuit
and B8Sociated waveforms.
_____________________________________________________________________ 277
CA3290, CA3290A, CA3290B
Fig. 13 - Light-<:ontrol/ed on",.hot timsr. Fig. 14 - Low-frequency multivlbrator.
+l&V
lOOK
+I!SV 471<
01
INPUT
47<
02
1001(
Fig. 15 - Window comparator.
I MEG
Fig. 16 _I LEO barllraph drivsr.
The photographs and dimensions of each COS/MOS
chip represent a chip when it is part of the wafer.
When the wafer is cut into chips, the cleavage
angles are 57° instead of 90° with respect to the
face 01 the chip. Therefore, the isolated chip is
actually 7 mils (0. " mm) larger in both dimensions.
Dimensions in parentheses are in millimBttlrI and
NOTE:
70-1.
~os. IN PADS ARE FOR I-LEAD DIP AND TD-5
dicated. Grid graduation. are in mil. ,,0-
are derived from the basic inch dimensions .. in-
3 inch}.
NOS. ourslDEOFCHIP ARE FOR 14- LEAD DIP
92CM-30091
Dimensions and pad layout for the CA3290H.
_____________________________________________________________________ 279
CA3401E, CA3401G
ELECTRICAL CHARACTERISTICS AT TA = 25°C, V+ = 15 V (Unless Indicated Otherwise I 1
, AIIIIIENT HIIIPEIIATUAE ITAI·2~·C
, fDA nST CIACUIT SEE F'IGUIt£ 4
LIMITS
;
CHARACTERISTIC TEST CONDITIONS UNITS ~ r
Min. Typ. Max.
STATIC
Output Voltage:
High, VOH 13.5 14.2 -
Low, VOL - 0.03 0.1 V
Max. Undistorted Output Swing, ,
VOP-P aoC<T A<750C 10 13.5 - o 10 IS
SUPPLY VOlT"at tv+ I-v
Output Current: Fig. 10 - Supply current vs. supply voltage.
Source, ISOURCE 5 10 -
rnA
Sink,ISINK 0.5 1 -
Total Ouiescent Current: 10 MlIlINT n:MPUA'UA[ n A )o2S·C
lOAD AESIS'ANC[ [Link]
Noninverting inputs open - 6.9 10 '2 ~IS FDA TIEST CIACUIT sr:e.: FIGUAE 5
rnA I
Noninverting inputs grounded - 7.8 14
Input Bias Current, liB
RL=oo TA = 25°C - 50 300
nA
1
. ; -10
RL = ~ OOC Q"A';;750C - - 500
DYNAMIC
TA - 25°C 1000 2000 -
-,
Open·Loop Voltage Gain, AOL V!V
OOCQ"A';;750C 800 - -
Input Resistance, RI 0.1 1 - M!1 o
OSlO I~
SUPPLY VOLTAGE (Vtl_v
Slew Rate, SR CL = 100pF, RL = 5 k!1 - 0.6 - V/l1s
Unity Gain Gandwidth, BW - 5 - MHz Fig. 11 - Source current vs. supply voltagtJ.
Phase Margin. ¢ - 70 - Degrees
Power Supply Rejection f= 100Hz - 55 - dB
Channel Separation, eOl le02 f = 1 kHz - 65 - dB AMBIENT TEMP[AATUAE 'T"I .2S"C
lOAD RESISTANCE fAll'SKA
FOlt TEST CIRCUIT SEE flGUAE 3
1
I
TEST CIRCUITS
) I
v,
S 10 IS
SUPPLY [Link] (y+)-y
Fig. 12 - Sink current vs. supply voltBgtJ.
RI &~;~B AMPLIFIER MUST 8E BIASED
BY VI IN THE LINEAR OPERATING
101 IS TOTAL QUIESCENT CURRENT WITH
"+M INPUT oPEN.
"vo REGION
A\lOl.·~ IQ2 ~S+T"O~:~UQTU~~~~EN~[Link] WITH
9ZCS-:!16,1RI
Fig.6 - [Link] gain and input resistance,
input bias current and output current fig.7 - Quiescent power supply current
test circuit. test circuit.
Y+·'5V
(OKa
., V
1
Vo
Vo
YoH MEASURED WITH "-" INPUT GROUNDED
VOL MEASURED WITH "-"INPUT BIASED AS SHOWN V,-+15\1
92CS-Z16l9RI
Fig.9 - Peak-ta-peak output voltage
Fig.8 - Output voltage swing test circuit. test circuit.
____________________________________________ ~---------------------281
CA3600E
ELECTRICAL CHARACTERISTICS, At TA ~ 25"C
~
"".Wi-'OUiC' VO',_ 'Vo,).
10 AMBIENT TEMPERATURE ITAI. 25·C
"Ov
TYPICAL
LIMITS p-CHANNEL ,/
CHARACTERISTIC SYMBOL TEST CONDITIONS
CURVE OR
UNIT 1
CIRCUIT
Min. Typ. Mo •.
I
FIG. NO. "'9'
FDr Each [Link].1 MOS Tr.,.inor II ,/
Drain Current
Gate-te-Source Threshold Voltage
'0
VGSlthl
VOS"'-10 V,V GS =-3.6 V
10= 10,..A
2,3,4 -O.S -1.1
1.75
-2.0 mA
V i!:O.I
t'IIIS~1
}V"2)
Gate-to-Source Voltage
~
I
Differential (PI VI. P2) IVGS1'-VGS21 10=-100 ,..A,VOS-"-lO V ±4 ±:IO mV
Forward Transconductance 10" 1 mA,f-l kHz 920 ,umho
'h
Low-FrequencV Noise Voltage 'N 10 "'--1 rnA.f=. kHz,As.:Q H 0.03 /lV JH'Z 0.01
Low-Ftequency Noise Current 'N 10=-1 mA,f-1 kHz,As=. MU 0.2 - pA .JHz o rn w m ~ • m
GATE -TO- SOURCE VOLTAGE DIFFERENTIAL jVosl-VoS2j-mV
Current-Mirror
Transfer Ratto Ip,/P21 'MTR '1",-100 [Link],VOS"·-lO V 30 0.7 1.1 1.5
Gale-Terminal Current 'GT VOS=-10 V,V GS "-3.5 V :!:O.D1S -40 oA Fig. 5- Gare-to-$ource volta(Jfl differentia/lis. drain currBf/t.
Input Capacitance C, 6.3 pF
Output Capacitance pF
Co
'0 AMB"NT TEM"' . . TU"f"A'.25OO
Input-Ie-Output Capacitance CI_Q 0.75 pF i,
For Each n-Channel MOS Transistor I ~
2,3,4 0.4 i I
#'
Drain Current '0 VOS - tlO v,VGS~t3.6 V 0.9 1.6 mA
Gate·to-Source Threshold Voltage VGSfth) 10~10 ",A 1.5 V ~ ,,~(.'i<~~\.
Gate·to-Source Voltage [; ,,-
Differential (nl vs n2) V GS1 10 ,'100 [Link],V OS ·+10 V ±30 mV ~ 0.1
VGS>!
Forward Transconductance
Low·Frequency NOise Voltage
Low·Frequency Noise Current
'"
'N
'N
IO"'lmA,f=1 kHl
'0"-1 mA,f-l kHz,Rs=Oll
'0 1 mA,f·1 kHl,As" Mn
860
0.2
0.3
",mho
I.I v ..('HZ
pA V.
i
io.O I
;
/
Current·Mirror
Transfer Ratio (nl /n 2) 'MTA 1, "100 [Link],VOS:t10 V 29 0.7 1.3 2.0 ~
Gate·Terminal Current 'GT VoS-t10 V,VGS""t3.7 V ±[Link] '40 oA 0,001 QOI 0,1 . .0
Input Capacitance C, 5.5 pF DRAIN CURRENT l'ol-mA
Output Capacitance Co 2.0 pF
Input·to·Output Capacitance C I·O 0.35 pF Fig. 6- Forward transcDnductance vs. drain currsnt.
For Each COS/MOS Transistor Pair
Drain Current 'DO VOO"""O V 9,10 1.0 2.2 4.0 AMBIENT TEMPERATURE ITA J.25-C
Orain·to-Source Cutoff Current V OO -+l0 V,VSS"'O V FOR tN,AS·OD: FOR iN,[Link]
10010ff)
eN -EQUIVALENT INPUT NOISE VOLTAGE
Gale VoltageIV G 'oo-tl0 V or 0 V 0.5 100 oA
iN ·EOUIVALENT INPUT NOISE CURRENT
DC Output Voltage Vo V OD "+10 V 10 4.2 5.0 5.8
Forward Transconductance VOO"-tl0 V, f -1 kHz 2300 ",mho
'"
Slew Rale (Open, Loop)
Amplifier Voltage Gain
SA
AOL
VOO=+15 V
V OO "'+10 V,f=1 kHz.A b "22 Mn
10
'" V'I.I S
Rs=50U 10.11 32 d8
Gate·Terminal Current V OO =-t10V 10 ±o.OO5 ±:IO nA
'GT
Broadband Output Noise Voltage VOO=+10 [Link]=[Link]=10 kU 10,11 500 ,v
EON
Input Capacitance 11.8 pF
C,
Output Capacitance 5.0 pF
Co
0.001
Input·lo·Output Capacitance CI_Q 1.1 1"
102 loJ 104 10' .0'
.0
OPERATING FREQUENCY HI-HI
Fig. 1- Noi$. IIOIt.,. lind noi$tI current vs. operating frequency.
10 AMBIENT TEMPERATURE (TA!=25-<; Rb. 22 NO
~
• ")00 VOO"+IOV
., . SEE CIRCUIT IN FIG. 10 V~ ~ l-
~
~ K>O / I /'
r-
/
g
/
B r-;,,{~
~ !:! 0.1
t! 10
/ i /
0 .r-- tJ.. GNO u 0.0'
§
0.' ~
/
,/
i I
~
0.001
! :I I
~ OD! ./
V
0.0001
~ 2 4 8 '0
~ooo SUPPLY VOLTAGE {Vool-VOLTS
-75 -'0 -2 5 250
AMBIENT TEMPERATURE (TAl _·C
100 125
Fig. 8- Orain-ro-$ourcecutoif current 1'5'. ambient temperature. Fig.9 - Typical VOO vs. IOD characteristiC$ (or amplifier circuits
of Fig. 70 and Fig. , 5_
___________________________________________________________________ 283
CA3600E
APPLICATIONS - Post-Amplifiers for Op-Amps (Cont'dl
120
"!+6vl
SUPPLYWLTAG£IVoO'·";5'v--'" '\ 2 '0
100 ,
10V ....... , '\ 2,11,14
22KO
~1~~+-U-~.,~,~,=+~~~~.T,~--+---1
~--+---~--4---+---~~1----
1\\
\
L-~~~IO~'~~IO~,-[Link]~'~~IO~'~~I~O.r-~IO"'~~'O'
OPERATING FREOUENCYUI-Hr
Fig. 11- Typica' voltll~ ,.in n. opera fin, frequlllJCY chafllCteriwcs Fig. 18- COS/MOS rrlJllsistor.".ir u * as post..",p/ifier to OP-llfnP in Fig. 19- COSIMOS tl1lnsistor-pmr uUld lIS post-amplifi(lf' to [Link]
for thrH"st.,. COS/MOS r,,,,,listor"pair flmp/ifi.,- in Fig. 16. tJpM-Ioopcirr:uit. in unity·flllin circuit.
Multivibrators. Threshold Detectors. and Comparators
Descriptions of several circuits using COS/MOS transistor-
pairs in both monostable and astable multivibrators have been
... CA3600£
published, The characteristics of COS/MOS pairs are also
ideal for mating with micropower op-amps in circuits such as
the precision multistable circuits shown in Fig. 22. In these
circuits precise timing and thresholds are assured by the stable
characteristics of the input differential amplifier in the CA3080
Operational Transconductance Amplifier. Moreover, speed
vs. power consumption tradeoffs can be made by adjustment
of the Amplifier·Bias-Current (I ABCI supplied to terminal 5 of
the CA3080. The quiescent power consumption of the circuits
shown in Fig. 22 is typically 6 mW, but can be made to operate
in the micropower region by suitable modifications.
The schematic diagram of a programmable micropower com·
parator, shown in Fig. 23 employs the combination of an
op-amp (CA3080AI and COS/MOS transistor-pairs in the
CA3600E. Quiescent power consumption of the circuit is
about 10 IJW(typ.l. When the comparator is strobed "ON",
transistor P1 is driven into conduction and the OTA becomes
active. Under these conditions, the circuit consumes 420 lAW
and responds to a differential-input signal in about 8 ps. Fig. 20- COSMOS 'I1ImislOr·,./rs USBd as two·stage post-amplifier to Fifl. 21- Unity"gIIin amplifier u,., COSIMOS trsnsistor..".irs as
By suitably biasing the CA30BOA. the circuit response time op-amp in opfIn-loop circuit. two-st.", pcnt-amplifler to op-amp.
can be decreased to about 150 ns but the power consumption
is increased to 21 mW. The differential amplifier input
common-mode range for this circuit is -1 V to +10.5 V.
Voltage gain of this micropower comparator is typically 130 dB.
t.~
...
,--=-----~r-----_:,----, ,.", \li;.~
100kA
,.
,.
10MO
. v-
bl MONOSTABLE MULTlV1BRATOR
1/3 CA3600E
," y'
Fig. 22- Mu/[Link]" citeuit. using COSIMOS trem/sto,.".ir,.
STROBE
10 10'
'lCS·215l5
Fig. 23- Pro"ammabl. micropower [Link]. FJ,. 24- ()pfIn-ioop (JIlIn char.:ter;stic for op-emp.
________ ~ ___________________________________________________________ ~5
CA3724G,CA3725G
High-Current N-P-N Features:
• High Current - t A
Transistor Arrays • High Breakdown Voltage:
CA3725G = 80 V dc min. V(BR)CES
@IC= tOIlA
Four Individual Sealed-Junction
CA3724G = 70 V dc min. V(BR)CES
High-Current N-P-N Transistors @IC= tOIlA
• Fast Switching Speeds:
The RCA-CA3724G and -CA3725G are high- ton = 30 ns typ_@ IC = 500 mA
92CS-24299
current n-p-n transistor arrays each containing toff = 36 ns typo @ IC = 500 mA
4 individual sealed-junction high-current
Fig. 1- Terminal diagram (top lIiew).
n-p-n transistors_ They are intended for high- • "Hermetic Chip" Construction
current, high-speed switching and driver • Silicon Nitride Passivated
applications.
• Platinum Silicide Ohmic Contacts
These devices are alike except for break- • Gold Chip-Metallization
down voltage ratings.
• Electrically similar and pin compatible
The CA3724G and CA3725G are supplied in with industry types MP03724, MP03725;
a 14-lead dual-in-line plastic package and
operate aver the full military temperature FP03724, FP03725; DH3724, DH3725;
range of -55 0 C to +125 0 C. The transistor SP3724, SP3725 in similar packages
chips used in these packages are of the
sealed-junction type to provide protection
against the deteriorating effects of humidity
and other surface contaminants without the MAXIMUM RATINGS, Absolute-Maximum Values at TA = 250C
need for a hermetic package enclosure.
The semiconductor junctions are sealed by CA3724G CA3725G
utilizing a sil icon nitride passivation layer. COLLECTOR-TO-EMITTER VOLTAGE V CEO 40 50 V
A multi-layered, highly corrosion-resistant, With Base Open
terminal-connection system of unique design COLLECTOR-TO-BASE VOLTAGE V CBO 70 80 V
is employed. With Emitter Open
EMITTER-TO-BASE VOLTAGE VEBO 6 6 V
With Collector Open
Applications: COLLECTOR CURRENT IC 1.0 1.0 A
• Core-Memory Driver POWER DISSIPATION: Po
• High-Speed Switching At T A up to 25 o C:
• High-Current LED Driver For Each Transistor ................ 1.0 1.0
• High-Voltage Switching Total Pack age ................ 2.0 2.0
• Relay and Solenoid Driver
At T A above 25°C derate linearly ...................... 20
• Lamp Driver AMBIENT TEMPERATURE RANGE:
Operating ................ -55 to +125 -55 to +125
Storage ................ -66 to +150 -66 to +150
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1132" 13.17 mm) from
seating plane for 105 max. 300 300
I I
JTtl
I I
."'V I,o",:
I I
-3·8V I~F . INPUT I)
I-OVo I I I
Ion TO SAMP\.IHG SCOPE I I I
1,< I., I I
".,oo.n OUTPUT T - Il LI Fto1
..
V'N~'" I I
VIN. + 9.7 V
t, < Ins
PULSE WIDTH _I po.
162n 100
I.....
I I
I
I
zl·~on
DUTY CYCLE <2% = ~, ON...! I. 'OFF.J
lC Illl ![Link]~~OmA
1B2A1-!50mA 92CM- 24300
Fig. 2-Switching time test circuit.
___________________________________________________________________ 287
CA6078, CA6741 Types
~T
Opwational Anapl.......
................
._----
CA6078AT - M~ Type
CA6741T - GeneraI-Purpase Type
FOf" Applications where low Noise
~TZ ·-.DC .........
(Burst + l/fl is a Prime Requirement • . . . . . - . • • • •kc
. h_ _......
1GI£._ ... ~'JOCoUE" • T-...ry
Virtually free from "popmrn" lbuntl noise:
.-= 40)Il10_'''_.
FeBtJIIB: • - ........
device rejected if any noise burst eou:eeds 2O,.V lpeakl, • ap..Iaap _ _
referred to input over a [Link] time period. FeBtutes: • ..... _"""-:[Link].v_.
.............. 0=_·
RCA-CA6078AT and CA6741T are Iow-noise linear Ie
operational amplifiers that are virt...lly free of '''popcorn''
Cb&ntt noise.
These Iow-noise wersions of the CA3078AT and CA3741T
• "-____
....... _ _
A_.
~IIA
• 0p00N0ap"""-....: - . - ...... --
__
........-...-.---.--
• a.-- ---......,,"""-:
1-5V __ ltG.75V1
.............. ...........
• ..... _ _ . . . -... _ _ 111A
• ...... _ " " " - : S.V_.
are a resulr: of improved processing cIevek:JpIMnts and ~igid
burst-noise inspection aUra. A ~ selective test ci..cuit
(See Fig. 2) asans thR .... type IM8tS the rigid Iow-noise
standards shown in the data SIClion. This Iowbunt-ooise
property also assures excellent pafor_nce throUJlhout the
1/f noise spectrum.
In addition the· CAIi078AT _ CA674IT 0_ the same DCSupplyV",-c-.v+_V-terminolsJ ............... .
CM741T
44V
~T
36V
features inc::orporated in the CA3J78AT and CA3741T
~ively. including output short-circuit fWOtKtion.
Iatdt-.... openrrion. wide CX)~ and differential-
:::r.:::=::=:.•. :::: :::::::::::::::::::::::::
Dowico DisoipoIian:
ot3OV
±15V
±6V
mode signal ranges. aNi Iow~ffset nulling capKtilitv. Up ... 7!iDC 1CA6741T), Up ... 125<> ICAIi078An •••••..•.•.... 500mW 250mW
_ _ 7!iDC .•.•.•.•...•.......••....•....•.....•.•.•.... Derate linurly 5 mW/DC
For detailed data, dwacterislics curves, sc:IIeIndic d ......
T_IIongo:
dimensional outline" and test circuits, refer to the Opera- o,.noo;................................................ . -55 ... +12SOC -55 ... +12SOC
tional Amplifier Data Bulletins File No. 531 and 535. In Sbngo •.•.•.•••••.•.•......•.......••..•.•.•.•.•...... -«i ... +I50OC
-«ito+I50OC
addition, to.. deQils of considerations in bwSl-noise [Link]~ •...•..•..•..•..••••..••.•.....• No limitation No limitation
~. I't!fa to Application Note. 1CAN-6732.
......T_IIluri.. -ing): .......................... .
' _ _ mont dllknt 1"Popmm', Noise in U _ lC"s".
"'_1116 tl/32 indIl1li11 to.79 mm)
The CAIi078AT _ CA6741T utilize the _""'IIy . .1ed 10 a:onds rn.x. _. _. _______ . __________ . ____ .. _
frum~for
JOOOC
~ TO-!i type~. The CAIi078AT _ the CA6741T
can also be supplied on requnt with d ..[Link]-li. . formed ·If Supply VohIiII is . . . ,.... ±[Link].. ... ~ Muimum [Link] v ..... is . . . . lOtM Supply v . . . . ._
leads. These types . . _ os the CAIi078AS _ -Shartcin:uit..., ........ to ........ _to . . . . :wppIy.
CA674IS. This .........._ configurotian ...._ to thot
of the ft..1ead d ..l-in-line (Mini-Dip) JIKbge.
• A_
\j' ....... ,,,- .......................... "....,."""
F.. ,-Typ. ....."".. of trPI' [Link] "". , . . . . . . and typII
r:ontnrI'-I forbtlnt"....
$UPl'LT ~T": V··"Y, Y- __ IIV
~- AIIIEJfT TE.-[Link] IW-ZS·C
I . ·J.U..[Link]."!.
of
:I , I.,..!.
~ ..
=
~
i .
list .1Isr "!DOd f(It C¥14T AId) 2IOOd FOR CMO'lIIM ~
~
. , ... ...
• CA614n OR C'AI078AT
II , .. ••WI' 2 .. a-wi
289
Linear Integrated Circuits
for Consumer Applications
Technical Data
_ _ _ _ _ _ _ _ _ _ _ _ _ 291
CA270 Types
v+ (CA210AW AND
12V I kQ 50kll CA210SW ONLY)
AFC >
I
...~
5
OL------------------+H--O~R.~S~~N
92CS-2S93'
Fig. 5- Typical waveforms for vidtlo outputs.
IOkA
IOO,..F 18011
I ~F
> 12
100.0 AGe TO
hl",kn~_--l_ _ _ _ _ _ _ _R~F()AMPL.
...~I 9
v+ ...
5
12 V 1.2 kQ AGe TO
I.F AMPL. .
u
.. 3
6
Fig. 4- Test circuit for CA270AW, CA270BW, and CA270CW.
FREQUENCY-MHz
ELECTRICAL CHARACTERISTICS at TA = 250 C, Supply Yoitage (Y+I z 12 Y, 92CS-2S9!!
and Referenced to Test Circuit (Fig. 41.
Fig. 6- Typical AFC characteristic.
CHARACTERISTIC TEST CONDITIONS MIN. TYP. MAX. UNITS
Supply Yoltage, y+ Y+=12Y 10.2 12 13.8 V
Supply Current, 1+ V+=12 V 22 40 56 rnA
(See Fig. 21
Video Characteristics:
DC Output Voltage, CA270AW 5.7 6 6.3
Terrn.9 (See Fig. 51 Zero Signal CA270BW 5.8 6 6.2 V > 12
CA270CW 5.5 6 6.5 I
~ 9
DC Output Voltage, CA270AW 5.6 6 6.4
§ 6
Term.l0 (See Fig. 51 Zero Signal CA270BW 5:7 6 6.3 V
CA270CW 5.5 6 6.5 ~ 3
Sync Tip Output Output=AGC thres· - 3 - V [Link]~
10
_ __
Voltage, Term.9 hold (non·gated) SIGNAL INPUT-mV
AC Input Voltage, Input for output= 50 70 100 mV
Terms. 1,2 AGC threshold Fig. 7- Typical AGC [Link].
Input Res., Term. 1 - 3.3 - Kn
Input Res., Term.2 - 3.3 - Kn
Video Bandwidth, At output = -3 dB - 5 - MHz
Term.9
Differential Gain See Note 1 - - 10 %
Differential Phase See Note 1 - - 10 deg
Intermod. Products:
Beat Freq.,l.6 MHz See Note 1 (95% sat. - - -60 dB VIc)
Beat Freq.,2.8 MHz bl ue colour bar) - - -67 dB
Rejection at Carrier F=Video Carripr;VIN -40 - - dB V9
Freq., Terms.9,10,ll for Term.9(dc)=3.7V
OL-------------~IOO~-
Rejection, Twice Carrier F-2X Video Carrier; -40 - - dB SIGNAL INPUT-mV
Freq.,Terms.9,10,ll VIN for Term.9(dc) 92C5-26934
=3.7 V
Fig. 8- Typical transf. chBl7ICttJriltics.
AGC Characteristics:
[Link], Term.4 Zero Sig.; 14 = 10 mA - - 0.3 V
Sat. Voltage, Term.5 Zero Sig.; 15 = 10 mA 0.7 - 1.2 V
____________________________________________ ~ __________________ ~3
CA758E
RC Phase-Locked-Loop Stereo Decoder Features:
• Low ci....ni ... (THO): 0.4% (typ.)
For FM Multiplex Systems • ExceHent SCA rejection: 70 dB typo
• RC oscillator
• Hi"'-audio~annel separation: 45 dB
RCA-CA758E i!. a monolithic silicon integrated circuit RC The decoder uses a minimum of external components. and
• Power supply range: 10 to 16 V de
phase-lock loop stereo decoder intended for FM solid-state requires one adjustment (oscillator frequency) for complete
stereo multiplex systems. alignment. In addition, the CA758E provides automatic mono- • Requires only one adjustment for complete ali",ment
stereo made switching and energizes a stereo indicator lamp_ • Lo..empedance outputs
The CA758E is pin compatible and electrically equivalent to
industry types p.A758, MC1311P, LMl800, and ULX2244. The CA758E is supplied in a 16-lead dual·in·line plastic • Stereo inclcator lamp drive: 150 mA typo
The CA758E decodes the multiplexed stereo input signal into package and operates over an ambient temperature range of
left and right channel audio output signals. The decoder also -40 to +850 C.
suppresses SCA !storecast) transmissions when present in the
\..OOP ST£MD O$C.
composite stereo signal. v' FILTER LAMP AC NETWORK
7
MAXIMUM RATINGS. Alnoluts-Maximum Value'" TA = 25"c
DC SupplV Voltage. +18 V
DC Supply Voltage (for <;a 1S'lecond period) . +22 V
DC Voltage at Term. 11Lamp Drivar Circuit with Lamp "OFF"}. +22 V
Device Dissipation:
Up to TA -700C 730 rritJ DETECTOR
INPUT
Above T Po • 70Dc derate linearly 9.1mWfJC
Ambient Temperature Range:
Operating. . -40 to +8SOC
Storage . . . -65 to +1S00c
L-__________~--------1_------------------~--_i~ITUT~~
,.kMl:
Laad Temperature lOuring soldering):
At a distance not less than 1J32" 10.79 mml
from case for 10 s max.
M~~~~~EXQI}-t-______________.J
GROUND LEFT RIGHT
CHANNEL
DE-EMPHASIS
Fig. 1 - Functional block dhlgnlm of the CA758E.
ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
IRet..nc1lCl to Fil 7 unl. . om_i. speclfledl
V.'2V.T A o 25:'"
CHARACTERISTIC Multiple. Input Stgnal (L-A. pilot "OFF") LIMITS UNITS
-300mVRMS
190kHz Pilot Level - 30 mV AMS
f (modulationl- 400 Hz or 1 kHz Min. .Ty•. Max.
Static Charactaoistics
Total Current Lamp "OFF" 26 36 mA
Maximum Available Lamp Current 75 '50 mA
DC Voltage at Term. 7 (Lamp Driver) I (lamp) = SO mA 1.3 '.8 V
DC Voltage Shift at either Term. 4
orS (Output) Stereo-to-Mono Operation 30 '50 mV
Dynamic Charactaoistici
Power Supply Ripple Rejection For a 2OO·Hz. 200.",V AMS Signal 36 45 dB
Input Resistance 20 36 kl1
Output Resistance 0 .• f.3 2.0 kl1
Channel Separation (Stereo) Atf= 100Hz 40 dB
f '" 400Hz 30 45 dB
f· 10kHz 45 dB
Channel Balance (Monaural) 0.3 ,.5 dB
Voltage Gain At f= 1 kHz 0.5 0 .• '.4 V/V
Pilot Input Level:
19·kHz Input Lamp "ON" '5 20 mVRMS
19-kHz Input Lamp "OFF" 2.0 7.0 mVRMS
Hysteresis Lamp "OFF" 3.0 7.0 dB
Capture Range (Deviation from
±2.0 ±4.0 ±6.0
76-kHz Center Frequ:ncy)
Total Harmonic Distortion
Multiplex Input Signal = 600 mV RMS
0.4 '.0
"
19·kHz Rejection
Pi! t "OFF"
25 35
"
dB
38-kHz Rejection 25 45 dB
Measured Composite Signal: 80% Stereo.
SCA (Storecast) Rejection 70 dB
10% Pilot. 10% SCA
Voltaga-Controlled Oscillator (VeO) Total Resistance (Term. 1S to 8)
Tuning Resistance
Voltage-Controlled Oscillator·
Frequency Drift
requirad to set
fRFF = 19 kHz ± 10 Hz (Term. 11)
Ooor;;;;T A S;;;25oC
25 0 S;;;T A "'700 C
21.0 23.3
+0.1
0.4
..
25.5
±2
'"
"
"
___________________________________________________________________ 295
CA758E
.......
NOTES,
T ....... _ ........ :!:SS
" ' _ _ _ on...-..nil
:!:2IM ....................
'---'_a.u_ ~ -+111DS.-285
Ca ·±''S .. _ciIaIit ....
f:Rintypicll ..............
"3-±'"
R4 -:l:l.
Fig.7- ·T_ _ .... _ _ _ _
--.
H, .... ..,-:l:1Sin ... . .
miI .... *R .. .......
TYPICAL PERFORMANCE CHARACTERISTICS (R"'--d to Fig.. 71
. . . . . . ~ITaI-~ ,...:. . .
,.. II -0IdJIImr"-,.....~.,.., ............ ____.
___________________________________________________________________ 297
CA810, CA810A Types
BOOTSTRAP Thermal Shut-Down
The thermal-limiting network incorporated in
the CABIO Series circuits provides protection
against damage due to excessive semiconductor
NOTE: temperatures that may result from high ambient
Pin numbering conventions temperatures and/or excessive dissipation, e.g.,
for these devices may differ as encountered in sustained overloads. As in·
from manufacturer to manu
facturer. however the devices
dicated in Fig.2 the thermal-limiting feature
are pin compatible and inter- automatically reduces the supply current (and
changeability is not affected.
o. output power) at the higher temperatures.
FEE~~ 8}---------.---+---~--~~~--_1------~--r__1~------~_+
.kR
RIPPLE
REJECTION
INPUT SUPPLY VOLTAGE (Y+).I ..... Y
LOAD RESISTANCE (RLI ... .D
DISTORTION .10 '"
10
COMPENSATION 7}-----+---.
.2 08
50 100 ISO 200
CASE TEMPERATURE (Tcl--C
9!:CM-Z.. 13ZRI
Fig. 2 - Typical output power and drain current as
a function of case temperature for all types.
·WING TABS AM TO BE GftOUHDED.
Fig. / - Schematic diagram of CA8/00, CA8/OQM.
Load-Dump Voltage-Surge Protection
The maximum operating supply voltage of
the CABIOAO and CA810AOM is 20 V, and
internal protection is provided for peaks of
up to 40 V, as shown in Fig. 4. Supply-
voltage peaks of more than 40 V will require
an LC network between the supply and
terminal 5. An LC network, such as the
one shown in Fig. B, provides protection
against supply-voltage surges of up to 120 V
for 2 ms. This type of protection is ON when
the supply voltage (pulsed or dc) exceeds
20V.
v+ (VI
40
JUl
'I" 50 ms
'2 ·1000 ms
14.4
FROM L·3mh
SUPPLy~TO TERM. I
LINE +J5·
13~~~F 92(:5-29632
Fig. 4 - Load-dump (oveNO/tage) ·voltage surge pro-
tection network and timing diagram for
CA810AO and CA8/0AOM.
Fig. 3 - Schematic diagram of CA810AQ. CA8/0AOM.
______________________________________________________________-----299
Preliminary Data CA920AE
Features:
TV Horizontal Oscillator • Sync separawr
• Noise gate input
For Color and Monochrome Receivers
• Internal precision timing ramp
• Dual-time-constant phase-locked loop
The RCA-CA920AE* is a silicon monolithic fast edge switching drive for transistor or • Output suitable for transistor or
integrated circuit intended for use in the thyristor horizontal output stages. thyristor deflection systems
horizontal stages of color and monochrome • Reduced power dissipation
The CA920AE is compatible with the indus-
television receivers. This device performs try type TBA920 in both lead arrangement
the functions of a sync separator, noise gate, and electrical operation, although the CA-
and horizontal oscillator with dual-time-con- 920AE features reduced operating current.
stant switching in the fly-wheel loop. It
also generates automatic phase control be- The CA920AE is supplied in the 16-lead
tween horizontal flyback pulses and the dual-in-line plastic package.
horizontal oscillator frequency and provides * Formerly Dev. Type No. TA6773.
MAXIMUM RATINGS, Absolute Maximum Values:
DC SUPPL V VOLT AGE 13.2V
DEVICE DISSIPATION:
Up to T A = 5500C • . . • • . • 750mW
AboveT",=55 C . Derate linearly at 7.9 mW/oC
"'MBIENT TEMPERATURE RANGE:
Operating -40 to +85°C
Storage -65 to +150oC
LEAD TEMPERATURE (During soldering):
At a distance not less than 1/32" (0.79 mm) from case for
10 seconds max. . +2650 C
JJ.
[Link]
INPUT
NOR·
DRIVE
OUTPUT ozv
TERMINAL ASSIGNMENT
POSITIVE
SUPPLY [Link] (v+J I
15 OSCILLATOR FREQUENCY
CONTROL
14 RAMp· PRODUCING
CAPACITOR
IS OSCiLlATOR DECOUPUNG
12 Ctl~~5;ETECTO.
SHAPED-SYNC PlLSE INP 6 11 DUAL MODE fLYWHEEL FILTER
TIME CONSTANT CONTROL
I ~~8L~t~~i DETECTOR
9 NOISE GATE INPUT
TOP VIEW
92C5-21479
ALL RESISTANCES ARE IN OHMS
Fig. 1 - Functional block diagram of the CA920AE with typic.1 peripheral circuitry.
________________________________________________________________ ~1
CA1190GQ
TV Sound IF and Audio Output Subsystems
"GQ" Suffix Type - Hermetic Gold-CHIP in Features:
Quad-In-Line Plastic Package • Nominal power output: 4 W at V+=24 V, RL =16n, dist.
= 10%; 2Wat v+=12 V, RL =8n,dist.-10%
The RCA-CA 119000 combines the sound • Wide power-supply range: 9 to 28 V • Excellent AM rejection: 50 dB typo
I F and audio output subsystems on a single • Low quiescent current: 25 mA typo • Differential peak detector - requires one
monolithic integrated circuit to provide a • 5-kHz deviation sensitivity: 1 W output typ_ tuned coil
television sound system. Each device in- • 3-dB limiting sensitivity: 50 IJ-V typo • Electronic volume control with improved
cludes a multistage I F amplifier-limiter, an taper and single. wire control
FM detector, and an audio power amplifier
that is designed to drive, primarily, an 8-, ELECTRICAL CHARACTERISTICS at TA = 250 C, v+ = 24 V, DC Volume Control Rx = 0 n,
16-, or 32-ohm speaker. R L = 16 n unless otherwise indicated_ Refer to Fig. 1.
The CA 1190GO is electrically and mechani-
cally equivalent to industry type TDA 1190Z. I LIMITS
CHARACTERISTIC TEST CONDITIONS UNITS
The CAl190GO differs from the TDA1190Z Min. Typ. Max.
primarily in its provisions for external feed- Static Characteristics
back components and a higher value volume
control. Current into Term. 14 Po = 0 10 25 40 mA
The CA 119000 is supplied in the hermetic Dynamic Characteristics
Gold-CHIP (G suffix) 16-lead quad-in-line IF Amplifier:
plastic package with an integral bent-down fo : 4.5 MHz, fm = 400 Hz
wing-tab heat sink (0 suffix), intended for
Input Limiting Voltage, - 50 100 IJ-V
(At -3 dB point), Vl (lim) Ll.f = ± 25 kHz
printed circuit board mounting.
fo = 4.5 MHz, fm = 400 Hz.
The transistor chips used in the hermetic AM Rejection, AMR Modulation Index = 0.3, 40 50 - dB
Gold-CHIP plastic package are of the sealed- VIN = 1 mV
junction type designed to provide protection
against the deteriorating effects of humidity fo = 4.5 MHz. fm = 400 Hz
and other surface contaminants without the Ll.f = ± 25 kHz, VI = 1 mV
need for a hermetic package enclosure. The
semiconductor junctions are sealed by utili-
Deviation Sensitivity Rx = 0, Deviation necessary - 5 - kHz
to obtain 4 Vrms across
zing a silicon nitride passivation layer. A 16n(lW)
multi-layered, highly corrosion-resistant, ter-
minal-connection system of unique design fo = 4.5 MHz, fm = 400 Hz
is employed. Minimum Audio Output Ll.f = ± 25 kHz, VI = 1 mV - - 10 mVrms
Rx= 15kn
fo = 4.5 MHz, fm = 400 Hz
Distortion at Po = 1.5 W
LI.f = ± 25 kHz, VIN = 1 mV
- - 3 %
Vout atLl.f = owith Rx
Signal to Noise Ratio adjusted for Vout = 4 Vrms 50 - - dB
at llf = ± 25 kHz
MAXIMUM RATINGS, Absolute-Maximum Valul
DC SUPPLY VOLTAGE (Between Term. 14
"
V+ and ground tabs) . +28 V 22 kll
OUTPUT PEAK CURRENT:
Repetitive. • 1.5 A
Non-repetitive .
INPUT SIGNAL VOLTAGE (Between Terms. 1 and 2)
DEVICE DISSIPATION:
With Infinite Heat Sink -
±3
2 A
V :}.
rO.221LF
Up to TA =9o"C • derate linearly 5 W
Above T A = 90°C . 83.3 mW/oC
With No Heat Sink - (free air) -
Up to T A = 25°C • . 1.75 W
Above TA = 25°C • derate linearly 14 mW/oC
THERMAL RESISTANCE:
Junction to ground tabs . 12 0C/W
AMBIENT TEMPERATURE RANGE:
Operating . . . • . . . . --40 to +85 °c
Storage'. ..... -65 to +150 °c
LEAD TEMPERATURE (During Soldering):
At a distance 1/16 in. ± 1/32 in. (1.59 ±0.79 mm)
from case for 10 seconds max. . +265 92CM-29273
Fig.l - Block diagram of the CA 1190GO in a typical application.
________________________________________________________________ ~3
CA1190GQ
DC VOLUME CONTROL MIOIO AMPUFlER
15
A~---;--------1r------t-------~--4---~--~--~---r--~~
B--~--+---------~r-----~--------rt--~---1r--+--~
R~
6.2K
E-;r-----------' Q50 051
F'~C=========~~~~=====±==C===~
6-;r-----------,
K--f--...l
lICTI1IE FILTER FII DETEClllR TUNING AUDIO AMPLIFIER
Fig.2 - St:hematic diagram (cont'd}.
[Link]-29272
Fig.3 - TIHminaI r r - .
-----------------------------------------------------------------~
CA1310E
..
,'m '"
2.'
Fig. 2 - Schematic diagrllm of the CA 1310E (Cant'd).
NOTES
A buffered 3-volt positive-going square wave is available at Term. 10.
The alignment of the free-running oscillator frequency may be checked
at this point with a frequency counter.
C1: A lower value input coupling capacitor may be used in place of
the [Link] value if reduced separation at low frequencies is acceptable.
C4: The time constant for the stereo switch level detector circuit is
calculated by C4 x 53,000 ohms ±30% with a maximum de
voltage drop across C4 of 0.25 lIolt (Term. 8 positive) and a
pilot level voltage of 100 mV RMS. Signal voltage across C4
is negligible.
C5: The recommended [Link] capacitor provides a 1.750 phase
lead at 19 kHz.
R1, R2: Load resistance values are related to supply voltage as follows:
Minimum Supply Voltage 8 10 12 V
Maximum Load Resistance 2.7 4.3 6.2 kfl
R3, C6, C8: C8 may be omitted. R3"" 100 ohms and C6 ;; 0.25 .uF,
if relaxed circuit performance is acceptable.
R4, R5, C7: If a capture range greater than ±3% typo is required,
reduce value of C7 and increase values of R4. R5 pro-
RESISTANCE VALUES ARE IN OHMS
CAPACITANCE VALUES ARE IN MICROFARAOS. portionally. However. beat-note distortion is increased
at high signal levels because of oscillator-phase jitter.
R4. C7 = ±1 % in test circuit and ±5% in typical application.
Fig. 3 - Telt circuit for mfHJsuremtmt of dynamic chartlCtBristics.
_____________________________________________________________________ ~7
CA1352E
TV Video IF Amplifier Features TYPICAL STATIC CHARACTERISTICS
atTA =25°C,V+"'2V
• High 45-MHz gain - 53 dB (typ.)
With AGC and Keyer Circuit • High-gain gaUd AGe system - with either positive- or Total Current 117 + 18 + 1,,1 ...•.. 27mA
negative-going sync. Output Stage Current tl7 + 181 ..............•.... ' •. 5.7mA
• Adjustable rf AGe delay to tuner
TYPICAL DYNAMIC CHARACTERISTICS
The ACA·CA1352E is a monolithic integrated circuit designed for • AGe gain reduction - 68 dB (typ.) atT A " 25D C, v+ -t2V
use as an if amplifier in monochrome or color TV receivers. It
AGe Range ..........•..•.....•. ""dB
features a high-gain gated AGe system with a 68-dB range Powar Gain ................... . 53 dB
(typ.). A delaved forward AGe output is adjustable by means Minimum rf AGe Range !term. 12) •. 0.2 V
of a potentiometer. Either positive- or negative-going sync may Maximum rf AGC Range (term. 121 .. lV
be used for this system.
The CA1352E is supplied in the 14·lead dual-in-line plastic
package, and is directly interchangeable with the industry type
1352 in similar packages.
MAXIMUM RATINGS, AbsolufB·MaJtimum Valuel
AtTA -25
SUPPLY VOLTAGE:
Between terminels 4 and 11 ..... 18V
Between terminals 7 or 8 and 4 ...... ,..18 V
INPUT VOLTAGE (terminal 1 or 21 .. ' .... 10V pop
AGe INPUT VOLTAGE (terminal6or 10) .. 6V
DEVICE DISSIPATION:
UptoTA =65D C ........... . . ... 750mW
Above T A .. 5SD C derate linearlv at .. 7.9mW/D C
AMBIENT TEMPERATURE RANGE:
Operating -40 to +8S:C
Storage ... -65 to +150 C
LEAD TEMPERATURE lOuring Soldering):
At distance 1/16 ± 1/32 in. (1.59 ±0.79 mm)
from Case for 10 seconds max. . ..
IF
f
RF AGe
OUTPUT
=
RF AGe
DELAY
6IF
INPUT
ADJUST
SYNC
*
VOLTAGE AT
*
VOLTAGE AT VALUE OF
*
POLARITY TERMINAL 6 TERMINAL 10 RI-n
-u::-
~.5
NEGATIVE I TO 4 V 0
NOM"2 V
-OV
POSITIVE
I TO B V
NOM=4.5 .-fLV
--OV
3.9k
92CS-24136RI
Fig. , - CA 1352E block disgrllm lind typic'" AGe tint .t-up.
_____________________________________________________________________ ~9
CA1391E, CA1394E
OSC
PRE- TIMING v' PHASE-
DRIVER REGULATOR DETECTOR
"31
560
R29 R"30
1.5k 1.5k
"'
2.6~
""
200
"3 NOTE: ALL RESISTANCES ARE
IN OHMS
Fig.2 - Schematic diagram of CA 1391E, CA 1394E.
The phase detector is isolated from the period. The current in 022 is turned around
remainder of the circuit by R31, Z2, 015 by current mirror 020 and 021 so that there
and 016. The phase detector consists of is no net output current at terminal 5 for
the comparator 022 and 023, and the gated balanced conditons. When a phase offset
current source 018. Negative-going sync occurs, current flows either in or out of
pulses at terminal 3 turn off 017, and the terminal 5. In circuit applications, this ter-
current division between 022 and 023 is minal is connected to terminal 7 through an
then determined by the phase relationship external low·pass filter, thereby controlling
of the sync and the sawtooth waveform at the oscillator.
terminal 4, which is derived from the hori- Shunt regulation for the circuit is obtained
zontal flyback pulse. If there is no phase by using a VBE and zener multiplier. Re- I
POSITIVE
difference between the sync and sawtooth, sistors R 13 and R 14 multiply the VBE of
equal currents flow in the collectors of 022 011, and the ratio of R15 and R16 mul-
and 023 during each half of the sync pulse tiplies the voltage Df the zener diode Zl. Fig.3 - Duty cycle at the pre-drive output (term. 1)
as it is affected by the input at term. 8.
+6V
+25'1 620n
IW
,." 200.n
I 2
14 ~n 150.n
430n
150 6aoo loon
55 ~'F
I.'
1.65
kll
150n
1.5 lin
OI'~OI~
390 3.9
kn kit
TO
DRIVER
TRANS-
FORMER
1.2 kfi
OUTPUT
LJ
20'1 p-p
\J
60 V p-p
5., 10 p.S
92CM-2.S749
FigA - DC test circuit. Fig.5 - Typical circuit application.
____________________________________________________________________ 311
CA1398E
R~
TEST SET-UP PROCEDURE FOR OIICILLATOR
die oo,i_ keying ............. i_a.nd odjust
Cx to obbin • fraoHunning _ I..... Iioquency of 3.579545
,-",<. 20 ,,"I _
initial_far .....,._ .... phMO _ _ _... p.
_n
MHz ±10 Hz. ~ die ..... Test Conditions cIoseri.... in die
EI_a a....:[Link]..t far Oocil"- Loct-\lp. wory L 1
Cl '-'>x. 1I11III pFI to die
____ ~ ________________________________________________________ 313
CA2002, CA2002M
ELECTRICAL CHARACTERISTICS at T A = 25°C, V+ = 14.4 V
Unless otherwise specified (See Figure 2)
LIMITS
CHARACTERISTIC TEST CONDITIONS UNITS
Min. Typ. Max.
Supply Voltage, V+ 8 - 18 V
Quiescent Output Voltage, Vo Measu re at Term. 4 6.4 7.2 8 V
Quiescent Orain Current, ID Measure at Term. 5 - 45 80 mA
THD = 10%, A = 40 dB.
f = 1 KHz
Output Power,PO RL =4 S1. 4.8 5.2 - SUPPLY VOLTAGE (I/+)-V
V+= 14.4V RL =2S1. 7 8 - W Fig. 4 - Typical quiescent drain current as a
function of supply voltage.
V+= 16V RL =4 S1. - 6.5 -
RL = 2 S1. - 10 -
Input Saturation Voltage, VI IRMS) 400 - - mV
A=40dB,f=1 KHz
PO =0.5W, RL =4S1. - 15 -
Input Sensitivity, el PO =0.5W,RL =2S1. - 11 - mV
Po = 5.2 W , R L = 4 S1. - 55 -
PO =8W, RL = 2S1. - 50 -
R L = 4 S1., Cx = 39 nF,
Frequency Response 1-3 dB) 40 to 15000 Hz
R X = 39 S1. ISee Figs.15,20)
I
- SUPPLY VOLTAGE (\1+1-1/
Input Resistance, RIITerm. 1) f = 1 KHz 70 150 KS1.
Open· Loop Voltage Gain, AOL RL=4S1.,f=IKHz - 80 - dB Fig. 5 - Typical output power as a function of
supply voltage.
Closed·Loop Voltage Gain, A RL -4S1., f-l KHz 39.5 40 40.5 dB
Input Noise Voltage, eN Freq. Resp. = 40 to
15,000 Hz 1-3 dB) - 4 - fJ.V
Input Noise Current, iN Freq. Resp. = 40 to
15,000 Hz 1-3 dB) - 60 - pA
A=40dB,f=IKHz
Efficiency, 7J
PO=5.2W,RL =4S1. - 68 -
%
PO=8W,RL=2S1. - 58 -
RI:=4S1.,A=40dB,
Power Supply Rejection Ratio, PSRR Rg= 10 KS1., fripple = 100Hz, 30 35 - dB
Vripple = 0.5 V
LOAD RESISTANCE {RLI-O
Fig. 6 - Typical output power as a function of
load resistance.
CLOSED-LOOP VOLTAGE GAIN (AI-dB
CLOSED-LOOP VOLTAGE GAIN (AI CLOSED-LOOP [Link] GAIN (AI
Fig. 1 - Typical input voltage as a function of Fig. 8 - Typical input voltage as a function of Fig. 9 - Typical power supply. rejection ratio as a
closed-loop voltage gain. closed-loop voltage gain. function of closed-loop voltage gain.
___________________________________________________________________ 315
Preliminary Data CA2004, CA2004M
12-Watt Audio Power Amplifier Features:
• Hermetic Gold·CHIP encapsulated in a S·lead
plastic TO·220·style package (VERSA·V)
The RCA·CA2004 is a monolithic silicon plastic TO·nO·style VERSA·V package. All
leads (except term. 3) are electrically in· • Thermal overload protection
class B audio power amplifier designed for
sulated from the mounting flange. elimi· • Drives load impedance as low as 3.2 12
driving loads as low as 3.2 H. It provides a
high output current capability (up to 3.5 Al. nating the need for insulating hardware. The • Deflection amplifier capability
and very low harmonic and cross·over dis· VERSA·V package is available with two • Output current capability of up to 3.5 A
tortion. lead configurations. The CA2004 has a • Few external components
vertical·mount lead form. and the CA2004M • VERSA·V power transistor package·requires no
The CA2004 is supplied in a hermetic trio
has a horizontal·mount lead form. electrical insulation
metal Gold·CHIP encapsulated in the 5·lead
MAXIMUM RATINGS. Absolute-Maximum Values:
DCSUPPLYVOLTAGE. 28 V
OPERATING SUPPLY VOLTAGE 26 V v+
OUTPUT PEAK CURRENT: OUTPUT
GROUND
REPETITIVE 3.5 A INVERTING INPUT
NON-REPETITIVE. . . . . . 4.5 A LON. INVERTING
INPUT
POWER DISSIPATION. Po at TA " 90°C 15 W
TOP VIEW
THERMAL RESISTANCE. JUNCTION TO CASE 4°C/W ,IeS -29223RI
AMBIENT-TERMPERATURE RANGE:
OPERATING o to +12SoC TERMINAL ASSIGNMENT
STORAGE -40 to +IS0oC
LEAD TEMPERATURE lOURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 125 max.
r---------~---4~v·
Thermal Shut·Down
Thermal shut·down occurs if the output
overloads (temporary or permanent). the
ambient temperature is excessive. or the
junction temperature is excessive. None of
these conditions results in device damage.
.2 They merely cause a temporary automatic
2.2.0.
reduction of output power and drain cur·
41OI£F
5V 5% rent.
92CS-308S9
Fig. 2 - Typical application.
Fig. 1 - Test circuit.
••
1M II
..........____.... ,0
100110.
• coo
10,..'
5V
C2
100~F
.,
22n
5'1 C3
33nF
•2
20n .7 C8
C•
100,..F
5V
••
3900.
3111 18nF
.0
3900 .8 3900.
2.2.0
Fig. 3 - 25 W circuit-bridge application.
__________________________________________________________ 317
CA3035, CA3035V1
SCHEMATIC DIAGRAM FOR CA303s AND CAlO35Vl
Ultra-High-Gain Wide-Band Amplifier Array IAMPL. N-;-,
I
• Three Individual [Link] Amplifiers
I
• Ideal for service in Remote·Control Amplifiers - - e.,., TV Receivers I
• Available in two electrically identical versions: C43035 with straight I,
leads; CA3035Vl with formed leads
1
HIGHLIGHTS 1
• Thr•••• parat. amplifle,s - • All o",plifiers sing I.-ended -
[Link] anel Hnelwlelth for each amplifier can III. adlusted _I, one power .upply requireel L~
with ..,i •• bl. external circuitry • Wiel. operoting t ... p."'u'. ,ang8 - r-
• Amplifier. op.,obl. [Link] or in cOlcad. .55 0 C to +125°C
• Exceptionally high cascade yoltage lain - • [Link] temperature compenutiCHI
I
129 dB .yp. at 40 kHz • H.,,,,eticoll, .[Link], .[Link].d lO·leaei TO·5-•• ,I. 1.,..,0
• Low noi .. performance • Wid ... bancl rupans.. m.t.1 packag. with straight or formecl I•• d •
ABSOLUTE·MAXIMUM RATINGS: I
Operating Temperature Range ..... ·SSoC to +12S oC J
Storage Temperature Range ......... . ... ·6S oC to +ISOoC
Device Dissipation ..................................... 300 mW TYPICAL REMOTE COtlTROL SYSTEM
Input Voltage ... . . . . . . . . . . . . . . . . . . . . . . . . . . . 1V p.p
Supply Voltage ........................ ,.,.... , .. +lSV
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79mm)
from case for 10 seconds max. . .. , .......... , .......... +26S oC
ELECTRICAL CHARACTERISTICS AT TA = 2SoC
TEST
CIRCUITS LI MI TS
SPEC I AL TEST AND
CHARACTERISTICS SYMBOLS CONDITIONS CHARAC- CA3035, CA3035V I UN I TS
TER ISTICS
CURVES Mi n. I Typ. I Max.
STATIC CHARACTER I ST I CS
Qu i escent Ope rat ing
V3 - 2 - V
Vo! tage V5 VCC · +9V Fi g. 3 - 1.9 - V
V7 - 4.9 - V
Tota I Current Orai n Id VCC ·
+9V,
RL3 • 5!ill
Fi g. 3 3.5 5 7.5 mA
DYNAMI C CHARACTER I ST I CS
Vo ! tag e Ga in:
Amp I i fie r No. I
Amll' ifier No.2
AI
A2
f
· .
VCC
40 kHz,
+9V
40
40
44
46 -
- dB
dB
.
COtfTIIOLFUNCTIOtfS
Ampl ifier No.3 A3 3B 42 - dB
FI•. 2
Output Vo 1tage Swing Vout
V lout
V20ut
RLI • I !ill
RL2 • I o !ill
o -- 2
2.6
-
-
Vp-p
Vp-p
STATIC CHARACTERISTICS TEST CIRCUIT
Vcc' +9V
V3 0ut RL3 • 5!ill
S i nuso i da I
- B - Vp-p
Output,
Vec • +9V
Input Res i stance:
Amplifier No.1 R lin -- 50K - n
Ampl ifier No.2 R2in f
· 40 kHz 2K - n
Amplifier No.3 R3 i n - 67D - n
Out put Res i stance R [out - 270 - n
~2out f
· 40 kHz - 170 - n
R3 0ut - lOOK - n flg.3
Bandw i dt h at
-3dB point: NOISE FIGURE TEST CIRCUIT
Ampl ifier No.1 BWI F 9.5 .- 500 - kHz .tv
Ampl ifier No.2
Ampl ifier No.3
BW2
BW3
VCC
· +9V F g.6
F g.7
-
-
2.5
2.5
-
-
MHz
MHz
No i se Fig ure
Ampl ifier No. [ NF I f • I kHz, Fig.4 - 6 7 dB
QUAN nCH
LABORATORIES
RS ·
I !ill Moon No.31!
NOISE ANALYZER
VCC ·
+ 13 V
- CSEE NOTE.
Sensitivity Relay IKII
Current .
7.5 mA
Flg.2 100 150 JJ.V
NOT£: SET ALL INTERNAL POWER SUPPLIES ON QUAN TECH
NOISE ANALYZER TO ZERO VOLT$.
fl ....
319
CA3041
ELECTRICAL CHARACTERISTICS, 0' an Amb"' .. T............ , T A, 01 25 oe, and. DC s."p/y '7' ~'... IT..• ... e
,...
Voltqe. Vee> 0/ +140 Volts applied eo Tenninal14 throqh a reBistance 0(6.2~. unle., otIu!,..
wise indicated. Any olher combination or
DC Supply Volta,e and Serie. [Link] which will " lTJ 1~1 n- ~I
:1
. ....... i
not cause the Maximum Di."ipalion Limit or any of the Maximum VoltCJBe or CUmtnl Limit. {or , .1
1M CA3041'0 bit esceetIed may be "Bed.
~ ~-
TEST CONDITIOHS LIMITS TYPICAL I ,j
..
CHARAC·
SETUP
TYPE TERIS- I" !~ ~
CHARACTERISTICS SYMBOLS AND SPECIAL CONDITIONS TICS ~ <GO!
(See p... 7 for Delinltions 01 Torms) PROCEDURE CA3041
I CURVES
51
f- ...- ... i
. ... . ... . ...
Fig. IIln. Typ. Max. Units Fig.
IJOc 2lD 245 270 \
Total Device Dissipation Py II TA = +25OC 225 250 1m mW "'" 2 ~, 10 100
+1Ii"C 230255 2110 mW FREQUlMCY (f1-....
FI,.4 - [Link].r yolfoge ",in anJ
Zener Relllliating Voltage (DC Sup-
ply VoltallO at Terminal 14) VI4 - 10.5 11.2 '12.3 V - inpu,.Ii."'n, YO'to,.
(Ie .... ) characteristics.
Quiescent Ope/8Iing Cuneot
(into Terminal 11)
111 11 0.25 0.63 I rnA -
9-Volt Cuneot Drain (Quiescent Op- VCC = +9 Vapplied directly
erating C....nt into Terminal 14) 114 11
to Terminal 14 7 II 16 rnA -
Input-Impedance Components:
Parallel Input Resistance Ri 3
- 11 - kl1 -
Parallel Input CapaCitance
Output-Impedance [Link]:
Ci 3 - 5 - pF -
Parallel Oulput Resistance Ro - - 100 - kl1 -
Parallel Oulput Capacitance Co - - 4 - pF -
~V
Input Limiting VoltallO (Knee) V~lim) 7 - 150 200 (rms) 4
Amplitude-Modulation Rejection AMR 10 45 58 - dB 9
[Link] Voltag. Gain
RecoverarI AF VoltallO:
A(IF}
[Link]
5 1=
4.5 MHz
- 67 - dB 4 PROCEDURE;
A • [Link].. G.'n:
RL' 50 kl1,1I1' _25 kHz mV 1) Set input frequency at desired value. Vi • 100 J.' V rlDa.
1. At FM-Detector Output - THD • 0.1S (typ.) - 250 - (rms) - 2) Recont vo'
3) Calculate Voltqe Gain A from A • 20 10110 vo/vi
2. At AF-Driver Output V
in Test Setup - THD < s.; 8 9 - (nos) - 4) Repeat Steps I. 2. and 3 for- each frequency and/or
for temperature desired.
Total Harmonic Distortion THD 7 Vo(aO' 8 V(rms) - 1.5 5 \\ -
Discriminator Oulput Resistance Ro(dis) - t - 10 - kO - FI,.S. T•• f ••fup 101 ,._sure,..n' oIlF."mplil'er
AF·Amptilie< Input Resistance R~af) - 1= - 100 - kO - yo/tap go;n.
[Link] Output Resist...ce R.,<aO - I kHz - 30 - kl1 -
AF-Driver Voltase Gain A.I 6 I - 41 - dB 8
PROCEDURESI
Recovered AF Volta..;
1. Set Input Silnai Generator 88 follow.:
Output !tequency • 4.5 MHz
~~::!:s. ~LuekH~ 1 kHz •
Output leVi'll for Vin • 100 mV nne
2. Set volume control fOl' maximum
af output.
3. Measure af output voltap and record Fig.' • T •• , se'up lor measur.m.n' 01
a8 Recovered AF Voltaae.
AF-omplili., volfag. 9G;n.
Total Harmonic Dbtortlon;
1. Adjust volume control for an af output
voltage of 300 mV rms.
.. [Link] 2. Measure Total Harmonic Diatortion of
the output silnal in accordance, with .1 AM8JENT TEMPERATURE ITA,-e·c
do- . ' the Operatinl Instructions for the Dis-
tortion Analyzer.
Input Limiting Voltote (!Cn. .); 4O
1. Decrease Vin until the at output voltale i"-
ie 3 dB Lees than the value set in SteP 1
of the procedure for measurement of f s.
Total Harmonic Distortion l!
:• '6
(300 mV - 3 dB • 210 mV)
2. Measure reaultin, value of Vin and re-
cord a. Input Limitinl Volta,e (Knee).
+140'1 --""""-4 ~
~ .. 1\
\
,.
~
QI 2 .. I I, 2 .. 6810 2 .. , 8100 2 .. &00
61
• TRW Electronics, 0 .. Plaines, illinois. Part No. E023174. or equivalent. FREQUENCY HI-11Hz
Fi9.7 _ res' s.'up lor measure. .a' o/l"put IImitln, vo/fo,_ (Kn_.).
recoye,.cI AF YO'to,., ami tota' harmonic .1;1'01';0". F;g.8. Typical AF~J,;v., voltage.g,,;" [Link];c
____________________________________ --------------------------~1
Wideband Amplifier, FM Detector, CA3042
FEATURES
AF Preamplifier/Driver • high sensitivity - input limiting voltage (knee) =
150 IlV typo at 4.5 MHz
• 6-mA audio drive capability
• internally Zener-diode-regulated voltage supply
_,ow harmonic radiation
• wide frequency capability - <100 kHz to >20 MHz
• eKeeliant AM rejection - 58 dB typo at 4.5 MHz
For Sound Sections of TV Receiver. Using Transistor. • low harmonic distortion
• inherent high stability - internally shielded
T fPeo AF Output Alllpli'[Link]
RCA Integrated Circuit TyPf' CA3()42 provides, in a sing!£' monolithic Hilicon chip, a MAXIMUM RATINGS,Absolute·Maximum Values:
major sub-system for the ~()und sec-lions of TV recciv(>rs. As :oIhown in the &'hcmati(' Dia~ OPERATlNG·TEMPERATURE RANGE ......•...............•. -40° to +86°C
gram (Fig. I) and the TV Receiver Bloc'k Diagrams <Figs.2A and 28) the CA3042 contains a STORAGE·TEMPERATURE RANGE ..........•.•............. _65° to +1 50°C
mUltistage wide-band if·amplifil·r H(>dion, an FM-detcctor [Link], a Zl·ner-diodl'-n·gulated LEAD TEMPERATURE (During Soldering):
power-supply sedion, and an af-amplifier s('ction specifically designcd to drive direl'll:v an At distance 1'16 ± 1/32 inch (lo59 ± 0.79 mml
n-JHl audio output transistor or a high-gain audio output p('otod(' tuhe. from case for 10 seconds max. ................................ +265 Q C
In FM receivers, the CA3042 ('an bc.! used to provide if amillifi(:atit)n and limiting. FM MAXIMUM INPUT·SIGNALVOLTAGE,
detection, and af preamplification. Between Terminals 1 and 3 .....•....••..............•.•........•.• ±3 V
MAXIMUM OEVICE DISSIPATION,
The CA3042 provides exceptional versatility uf l'ircuit d(~sign bc(,8UH(, th(' if-umplifi('r/
At Ambient Ju p to +25°C ...................................... 950 mW
limiter section. FM detector·scdion, and af-pwamillifier/drivl'r Hedinn ('an lx' u!'\ed indl'-
Temperatures above +25Q C .......................... Derate at 10.8 mwtc
pendently of each other.
The CA:3042 utiliz{'s a 14-I(>ad dual-in-line plastic packagl' with \('ads SI)('("i<1l1y funnl'rl
to facilitate automatic insertion uf' th(· dl'vice in suitably pundwd printl'fi-(.'in.'uit bU(l['ds.
'.
------~I Fig. 1 - Schematic Jiqram.
* for XFMR Details see flg.2(a)
Fig.2(L) - alock diagram 01 typical TV receiver utilizing
the CA3042 and a J2FX5, 6EH5, or equivalent.
PROCEDURES:
Total Device Dissipation:
1. Set switch S in position A
2. Measure and record V14 and 114'
3. DetennineTotalDeviceDissipation from PT '" V14I14
Quiescent Operoting Cur,ent Into Terminal 11:
1. Tum switch S to position B
2. ~:tt:::o It!r!i~[Link] as Quiescent Operating Cur-
9-Volt Current Drain:
1. Set switch S in position B
Fig. 2(a) • Block diagram of typical TV receiver utilizing 2. Measure 114 and record as 9-Volt Current Drain.
transistor RCA-40313. Fig.3 _ Test setup lor menurement 01 toto' device diu;-
potion, quiescent current into terminal No. J J, and
[Link]/t current Jro;n.
_____________________________________________________________________ ~3
CA3042
ELECTRICAL CHARACTERISTICS. at an Ambi•• , T.""' ......... TA. of 26°C. and. DC Supply
Voltage, Vee. of +140 Volt. applied '0 TenninGl14 Ihl'ou,h a "[Link] 0(6.21&0.. unl... tnh.,..
wi.e indicated. Any other comboinotioll of DC Supply Vol&QS'e and Serle. R.. ;'tanee which will
not cause the Masimum Dissipation Limit or any of the Ma:dmum VoltGJ'1f or CurreM Limit. for
the CA304~ to be exceeded may be used.
TEST CONDITIONS liMITS nPICAl
CHARAC'
SETUP TERIS·
CHARACTERISTICS SYMBOLS AND SPECIAL CONDITIONS TYPE
(See Page 7 for Definitions of Tenns) CA3OI2 TICS
PROCEDURE
Fig. Min. Typ. Max. Units ~
FIg.
Total Device Dissipation PT 3 TA' +25 UC
+85UC
DOC 200
210
220
230
240
250
260 mW
270 mW
280 mW
4 [Link]
A.20~~
'0'''. ....
Zener Regulating Voltage (DC Sup-
ply Voltage atT enninal 14) VI4 - 10.5 11.2 12.3 V - Fig.9. Tes, ..'up lor measurement of AF (llbp'ili.,
yo/tag. gain.
Quiescent Operating Cunent
(into Tenninalll)
III 3 0.25 0.63 I mA -
9-Volt Cunent Drain (Quiescent Op-
erating Current into TenniRall4) 114 3 VCC - +9 Vapplied directly
to Tennl.al14 8 12 18 mA - ,.
AMBIENT T£MPEIlATURE (TAI'2S·C [
I I ~I III
R.-50A
Input·lmpedance Components: R!.~6~
Parallel Input Resistance RI 5 - 11 - kO - I e lj50 pf
CiaO
Parallel Input Capacitance CI 5 - 5 - pF - ~20 W
Output· Impedance Componenls:
Parallel Output Resistance Ro - - 100 - kO - ~
w" \ I r\ I~
Parallel Output Capacitance Co - - 4 - pF - S
~ '0
Rs -IOU
C,-50PF I RS-IO KG
CiaO
Input Limiting Voltage (Knee) V~lim) 11 - "V
ISO 200 (nns) 8
• ~ I ~
Amplitude-Modulation Rejection AMR 7 45 58 - dB I. I
IF·Amplifiel Voltage Gain
Recovered AF Voltage:
A(IF) 6 f-
4.5 MHz
- 67 - dB 8 to 10
FREQUENC'fCfl-k",
10' 10'
'0'
[Link] t2CS-I4,1O
I
Rl-5OkO mV FI9.10. Typical AF amplifier yo/tag. fIG;n
1. At FM-Detector Output 11 THO • 0.7~ (typ.) - 250 - (nns) - cIIaract.,[Link].
mV
2. At AF·Driver Output
in Test Setup 11
RV 322!l
THD<~ 500 800 - (nns) -
<'>f= V
3. At AF·Oriver Outpul in
TV·Receiver Sound System 2A 0.28 .25 kHz
Rl' ISO kO
THO· I~ (typ.) - 3 - (.ms) -
I
Total Hannonic Distortion: THO
1. In Test Setup 11 VO<aO- 500mV(nns - 1.5I 5 ~ -
2. In TV Receive. Sound System 2A 0.2B Vo(aO = 1.3 V(nns) - - ~ -
FM-Oetecto. Output Resistance Ro(det) - t - 10010 - kll -
AF·Orive. Input Resistance RKaO - f= - 250 - kO -
AF·Q.i... Output Resistance R.,(aO - I kHz - - 0 -
AF·Ori ... Voltage Gain Aaf 9 I Rs' [Link]" 0 - 30 - dB 10
PROCEDURES,
Recovered AF Vol'atI.,
1. Set Input Signal Generator 8S follows:
Output frequency = 4.5 MHz
Modulating frequency'" 1 kHz
Deviation = f: 25 kHz
Output level for Vin .. 100 mV me
2. Set volume control for maximum of output
3, Measure af output voltqe and record as Recovered
AF Voltage.
Total Harmonic D,[Link]
1. :3du~~ :~~me control for aD at output ¥oILlIP' of
2. [Link] Total Harmonlc [Link] of the output
aapel in accorclance with the Operating Instructions
tor the Distortion Analyzer.
Input Limiting Voltag. (Kne.):
1. f:~:: tt!nY:l~~1 s!~in~:tf~f ~hc!t~c~:u! 1!
measurement of Total Harmonic Distortion (500mV -
3 dB· 350 mV)
2. Measure rellultinl value of Vin and record all Input
Limitinl Voltaae (Kneel.
Fig.1J ~ Tes, se'up la, me•• ",ement 01 'nput limiting vo/tag. (kn ..).
,eco.,.,eJ AF vo/,age, anti totalltarmonlc [Link].
_________________________________________________________________ ~5
CA3043
MAXIMUM VOLTAGE RATINGS
The following chart gives the range of voltages which can be applied to the terminals
listed horizontally with respect to the terminals listed vertically. For example, the MAXIMUM
voltage range between horizontal terminal 5 and vertical terminal 3 is -t6 to 0 volts. CURRENT RATINGS
TERM-
INAL 10 11 12 1~~ [IN loUT
No. No. rnA rnA
0 Note(l)
·5
.,
o .,
0
.o
+6
o
+15
.,
.,o .,o .,o Note (21 .,
0 0.1 40
Voltage Gain = 20 loglO 100 ~
.,
·4
0
-6
20
vi
Cb - Bypass Capacitor, 0.1 JolF electrolytic in parallel with 0.01 }IF
0
-6
..• I6 (lim) '"2~' vi "" 100 mV(RMS)
.,
·15
* Output circuit should be completely shielded (rom the input
circuit at the socket.
Fig.4 - Vo/tag. gain test circuit.
Note~l)
0
-6
0 100 vCC'+30V
-6
RL'750n
90 TA'25'C
0 20
-6 m
Note{2)
., i
10 0 0
10 0.1 40
g
~
z 1'\
11 11 40 0.1
12 12
i
Note 1: These terminals should be connected through a de
4 '8 4' 8
resistance to any terminal wbich does not exceed I ~ ~
lOOohma. FREQUENCY (f)-MHz
• Voltqes are not normally applied batween tbese tenninals.
Note 2: Pin 11 may be connected to any positive voltage Volt8l'es appear~ between these terminals will be safe if
source through 8 suitable resistor provided its eta'- the specified limits between all other terminals are not Fig.S ' Voltage gain ys frequency.
rent ratina is not exceeded. exceeded.
200 \lCC'+30\l
RL,7$OA
T,,'2e."C
i 160'r--+--t-rtt--+--t-rrt--+--~-H
'i
~ IW'~-t--t-rtt--t--t-rtt-~--~-H
i 'O'r-+--r+++-+--r++~J+--rrH
g V
~
,
FREQUENCV (f)-MHz
... '0
. .. '00
PROCEDURE:
1. Recovered Audio Volt_fie vo(aO -
Fig.7 . Input IImllln, "'''''. (~...J al -3 fiB point
Set input rrequency to 10.7 MHz, PROCEDURE:
VI frequency.
vi'" 1 m V(RMS), modulating frequency '" 1 kHz A. Connect FM Generator to CA3043 input.
Deviation == ±75 kHz Set frequency to 10.7 MHz, Vi '" 10 mY, modulating frequen.
cy=lld{z
62lJJi u"
n~
Re~O;:1:.0 a8 measured on the Distortion Analyzer meter
Deviation = ± 75 kHz.
This is the recovered Audio Voltage Vo(af) Tune Wave Analyzer to peak reading at 1 kHz and record
recovered Audio Voltage Vo(aOFM.
2. 3 dB Limiting Sensitivity vi(lim) - B. Disconnect FM Generator and Connect A.... Generator to
Reduce vi until Vo(aO drops 3dB. CA3043 input.
Record this value or vi a8 Vi(lim) Set frequency to 10.7 MHz, Vi '" 10 mY, modulating frequen-
cy = 1 kHz, percent modulation = 500/•.
3. Total HarQ:Ionic: Distortion THD - Tune Wave Analyzer to peak reading and record recovered
Re:~n:~~~t!;:~!~:lr:~~oise~~t~!!i::::ntD~DalYZer per Coil Fonn, Outside Diameter'" 7/32 11 ~:;;it:~~a::d:~~~~~MRejeCtiOn Ratio'" 20 10g10 vo(aOFM
Can = 1/211 square X 1.1/8 11 long
* See Fig.9 (or details on Discrirninator Transformer. vo(aOAM
Slugs - Radio Industries Type MP34/MPlOO Material
Fig.6 - Input limiting yoltage (lenee), recoyereJ AF Ll & L3 =
20 Turns 5·44 1Hz wire universal wound Fig.8. Amplitude moJulation rejection test circuit.
voltage, and tata/harmonic Jistortion test circuit. L2 =
10 Turns 5-44 litz wire wound bifilar with Lt
Ll & L3 coupling adjusted to 520 kHz peak to peak separation
on S curve when operated in circuit shown in Fig.5.
Fig.9 - lO.7-MHz discriminator transformer for CA3043.
___________________________________________________________________ 327
CA3044, CA3044V1
ELECTRICAL CHARACTERISTICS ot TA * 25"C. U.I ... OtIooowl •• s,..lflod DYNAMIC CONTROL VOLTAGE
UMITS CHARAC·
CHARACTERISTICS
TEST
TEST CAlII44 and CAlIl44VI TERISTIC The CA3044 and CA3044VI .... [Link] in-
CHARACTERISTICS SYMBOLS CIRCUITS CONDITIONS UNITS I CURVES tended (or use in the AFT system of color television
~ MIN. I TYP. MAX. FIG. receivers. Each device is tested so that the control
STATIC CHARACTERISTICS voltages generated by the circuit meet the critical re-
quirements of the system. Figure 5 is the schematic
VCC .jOV diagram of the test circuit.
Device Dissipation PT 3 RS -1.5kO 00 120 ISO .w
TA··55"c Figure 6 and 7 show the control voltages gener-
ated at terminals 4 and 5 of the Integrated Circuit as a
VCC·JOV
Device Dissipation PT 3 RS ·1.5kO 110 140 170 .w fWICtion of the frequency deviation from the nominal
..
TA·250C center frequency. Figure 6 shows the region within
25 KHz of the center frequency while Figure 7 covers
VCC' JOV
Device Dissipation 3 RS·1.5kO 130 1611 100 the entire bandwidth of the system. The horizontal
PT
T. - .125oC reference lines on the figures are generated by a volt-
age divider connected between the power supply volt-
9-Von CUlleaI Drain IT 3 V10·9V 2.5 4 5.5 mA
age on Terminal 10 and ground. The dynamic control
Z- Replatin. Vol.... -
I
VIO 3 10.5 11.2 11.9 V voltages are compared with these references according
DC Sappl, Vol.... at TermilrallO to the Output vs Frequency Deviation Table. For ex-
Qui.-l Operlli.. Curre1ll into 3 I 2 4 orA ample: when the frequency deviation is -25 KHz the
IZ
Terminal 2 control voltage at Terminal 4 is greater than the refer-
Qui.....1Operali .. Volta.. at Vce' JOV 5.0 6.5 8.0 V ence A voltage;: the control voltage at TerminalS is
V4
Terminal 4 RS = l.5kO
. less than the reference B voltage.
I
Quiescent Op!rlli'a Volta", 01 V5 5.0 6.5 8.0 V The shape of the correction voltage character..
T....ilra15 istics is dependent to a large decree upon transformer
Output Offset Von..,_en V4-/j ·1.5 0 1.5 V characteristics and the parts layout. In order to
[Link] 4 and 5 closely duplicate the curves shown, the printed circuit
OYNAIIIC CHARACTERISTICS (AS RF AMPLIFIER) board shown in Figure 8 and the parts layout shown
Vi in Figure 9 should be followed a8 closely as possible.
Inpollimili.. V.I.... (Knee) 4 f=45.75 IIHI 75 mV
Input Adllittance
limiiinL
YI\ [Link].1 .....
Rover.. Transfer [Link] '12
f· 45.75 MHz
Vee· 30 V
3.8.j3.4 ......
Forward Transfer Adlllittance ·11.7 .10.1 IIMIIho
'21 RS'LSkO
Output Admittanct [Link]'jO.9 IIIIIho
'22
OUTPUT vs FREQUENCY DEVIATION - AFC
VCC' .JOV
Vi. ·200 oV RMS \of '01
fo'MHz .. VIO VIO
iadicated
45.750·0.025 85 V
V
.-..
Correclion-Conlrol [Link] at 6.7
~
~:.
corr. S 45.750 • 0.025 33 V
Terminal 4
(4) .8
45.750·0.000
45.750 , 0.900
75
43
V
V
"
7
45.750 • 1.500 85 V IV ;;GHAL
G£N€RATOR 6
45.750,1.500
45.750·0.025
,33
33
V
V
= I noo,
~F
6.7
[Link] 85 V lll!l'Mi~'rI)Ef ;-.Q~~:J.I~ICAl BAMDWIDTH ON L.'O:~~:i~!.I:Mll7S4
V 45.750·0.000 43 V
Conectilll·Conlrol Vol.... ,I COlI. 5 lZa:T:~:-~JPMR,1sE:~::i~~~~'!i ~r:~.~ l2'oJ'rO:tv~UNT~1S5
TerllinalS (5) 45.750 • 0.900 7S V
7
45.750·1.500 33 V
Flg.S ~ CorNet/orr vol,.,. ,.s, circui' lor
45.750 • 1.500 85 V
CA3044 onJ CA3044VI.
DIFINITIDNS DF TIRMS
input Llmltinl Vol.... (Ku.) [y,(II .. ))
The iaput signal voltap which win eau•• the output sigDal to
[Link] 3 dB from it. maximWll level.
Totol [Link]. [Link] (P T )
The total power drain of the device with no aiena1 applied and
no exteraalload current.
Qui •• [Link] [Link] Volta,.
'l'he de: voltage .t the output temdnal, with [Link] to lP'ouad,
with no 8ipal applied.
Oul •• cant O,.ratlng Curra..t
The avenge (dc) value of tbe current in either output, terminal,
with no .ianal applied.
Ou'put Off••• V.I••••
......". FR£QU£NCY DEVIATION-MMI:
'I1le de voltale between output terminal. with no signal applied.
C_lr.1 Volt•••
Fi,.' - T)'pice" narrow-6anJ Jynamlc control yoltage Flg.7. Ty"ical w;ft..OonJ t/ynfllfllc confrol vo/'age The de voltace at either output terminal with reapect to Found
c6."c"rl."c •. characteristics. ",itban Rlf signal of specified frequency applied.
_______________________________________________________________ ~9
CA3052
Four Independent AC Amplifiers APPLICA TIONS
Special-Function Sub-System for Stereo Preamplifiers, • Full-function stereo preamplifiers
• Tape recorder and playback preamplifiers
Magnetic Pickups, Tape Heads, etc_
• Tone Generators
FEATURES ABSOLUTE-MAXIMUM RATING at TA = 25 0 C:
• Four AC amplifiers on a common substrate POWER SUPPLY VOLTAGE +16V
• Independently accessible inputs and outputs
• Operates from single-ended supply AC INPUT VOLTAGE . . . . • . . . . . . . . . . . . • . . . . . 0.5 V rms
DISSIPATION:
EACH AMPLIFIER
53 dB min_ Up to T A; 55°C •........•..•.....•.•.......•...•...••.••.•• 750 mW
• High voltage gain _
• High input resistance 90 k Otyp_ Above T A; 55°C • . . . . . . . . . . . . . . • • . • . . . . . . . . . . . . . . Derate linearly at 7.7 mW/oC
• Undistorted output voltage 2 V rms min_
1 k 0 typ_ TEMPERATURE RANGE:
• Output Impedance _
• Open-loop bandwidth 300 kHz typo Oparating . . . . . . • . . . . . . . . . • • . . . . . • . • . . • . . . . . . . -40o C to +850 C
The RCA-CA3052 is a silicon monolithic Storage . . . . . . . . . .. -Ss"C to +150o C
integrated circuit designed specifically for LEAD TEMPERATURE lOuring Solderingl:
stereo preamplifier service. The circuit con-
At distance 1/16 ±1(32 inch 11.59 ±o.79 mml
sists of four independent ac amplifiers which from case for 10 seconds max. . . . • . . . . • . • . . . +265°C
can operate from a single-ended supply.
The CA3052 can operate as an equalizer
amplifier in tape recorders, magnetic car- MAXIMUM VOLTAGE RATINGS
tridge phonograph applications, and tone The following chart gives the range of voltages which can be applied to the terminals
control amplifiers. It can provide all of the listed vertically with respect to the terminals listed horizontally. For example. the
voltage range between vertical terminal 2 and horizontal terminal 4 is +2to-3.6 volts.
amplification necessary for a. full-function
stereo preamplifier.
1~:t 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
The CA3052 is supplied in a 16-lead dual-
in-line plastic package.
No.
1 +16
0
. . . · · · · · · · · · 0
-16
·
. · · · ·
. ··
+2 +2 +2 +16 +2 +16 0
2 -3.6 0 -3.6 -3.6 0 -3.6 0 -16
RCA-CA3052 is schematically identical with
the CA3048 Amplifier Array (File No. 377). 3 +5
-5
· · · · · · · · · ·
Each amplifier of the CA3048 is tightly
specified for equivalent output noise under 4
· +3.6
-2
· · · · · · · · · ·
a variety of test methods. The CA3052 is
specified using RIAA test methods for equiv-
5 0
-16
· ·
+2
-3.6
+2
-3.6
0
-16
+16
0
+2
-3.6
· +16
0
·
alent input noise using one test method for
amplifiers 1 and 4, and an appropriately
6
· · · · · · 0
-16
· · ·
different method for amplifiers 2 and 3. 7
· ·+5
-s · · · · · ·
8
· · · · · · · ·
9 +5
-5
· · · · · ·
10
· · · · · ·
11
· · · · ·
12 0
-16 · · ·
13 +5
-5
· ·
14
· ·
'16
15 0
16
• Volta.e. are not normally applied between these terminal •.
Fig. 1 - Block diagram of stereo preamplifier VoU. . . . .ppearing ~tween the.e terminals will be .afe if the
using CA3052. specified limits between an other terminal. are not exceeded.
______________________________________ ~ _________________________ ~1
CA3052
R"
lOOK
R"
IK
R27
IK
-52
IK
'''cc
:oNMECTTO U'PROPRIATEHhlNALTOIt£AO¥OLTAGE
Fig. 3 - Test circuit for measurement of collactor
.upply 1101,... and currents.
04
0,
NOTE: ALL RESISTOR VALUES ARE IN OHMS
Fig. 2 - Schematic diagrem for CA3052.
.. •.J.::; .....
:!:::: ::;;
n [Link]:f~· • ~~~ :~u~iv~en~. low dl stoftion type (0.211& THO Of less)
• Adjustment Of EI to 2 voltl wi II make Es 0: 2m ".
DC SUPPLY VOLTS IVeel AMBI[lIT TEW£ltATURE llAl--C '''' Test Circuit shOws Amplifier 111 IIldef lest, to test Amplifiers 2, 3,
or 4; connec:t terminals as shown in Table.
Fig. 4 - TypicBl DC supply cur,."t .. supply Fig. 5 - Typical DC supply current .. embient TERMINALS
IMPLIFIE.R
Il0l,.... tflmperaturtl. 1
OUTPUT
1
INPUT
•
BYPASS
3
2 S 8 7
3
•
11
IS 13
• I•
14
Fig. 6 - rillt circuit for mtIIISurement of
[Link], open-loop gain, and
bandwidth characteristics.
COLLECTO.w....... vY(JLn(Vcc)··12
AllIIEMTTEMP!IATURIIT,f,,·n·c
~ M R"++tl"-t-+H+..Jr--
!~ -+l~t~~~~
~
§a
~
IX S\.PP\.Y YOLTStVccl AMIII!NTTEIIPERAruREIT,I_OC
Fig. 7 - Typical amplifier gain ... DC supply Fig. 8 - Typical open-loop gain .. ambient
voltags. temperature.
Fig. 9 - Typical open-loop gain VB frequency.
___________________________________________________________________ 333
CA3064,CA3064E
TV Automatic Fine Tuning Circuit
RCA·CA3064 and CAJ064E represent the third generation of
integrated circuits designed primarily for AFC (Automatic-
Frequency-Control) applications. They provide all of the
signal-processing components needed (with the exception of
the tuned-phase-detector transformer) to derive the AFT cor·
rection signals from the output of the video-if amplifier. The
CA3064 is supplied in the 10-formed-lead TO-S style pack·
age. and the CA3064E in the 14-lead dual-jn-line plastic
package .. Both types operate over the temperature range of rAOM
-55 to +12SoC.
~~o
The CA3064 and CA3064E are functionally similar to the CORRECTION VOLTAGE
CA3044 and CA3044Vl but embody a higher-gain input TO VHF AND UHF
TUNERS
amplifier which provides a 2()"dB improvement in sensi-
tivity. The increased sensitivity extends the application of I Ikll
__'-_-_-_-_-_-_-_-_-_-_-:-_=~I •~i~~!;tE~~M~~:~-::l'tl:~N~~~:~~c
a proven AFT system to the low-level if-amplifier stages SEE riG - 6 (bl FOA cort.. OATA
in TV receivers.
ARE
Because the CA3064 and CA3064E are functionally similar to
the CA3044 and CA3044Vl. refer to Application Note
ICAN-6831. "Application of the RCA CA3044 and CA3044 Vl
Integrated Circuits in Automatic fine- Tuning S~tem5" for Fig.l - Block diagram of ryph:aJ operating circuit utilizing the CA3064 and CA3064E.
general application information.
Features: ELECTRICAL CHARACTERISTICS at T" = 25a C, Unl ... [Link]. SpeCified
• Cascade type high-gain amplifie;r (18 mV input for rated output! LIMITS CHARAC·
TEST TERISTIC
• Internal voltage regulator TEST CA3064. CA3064E
CHARACTERISTICS SYMBOLS CIRCUITS CONDITIONS UNITS CURVES
• Differential detector
• For use with either color or monochrome ~ MIN:.! TYP. MAX. r---ru;,-
• Differential amplifier STATIC CHARACTERISTICS
• Bipolar outpuu
• Wide operating-temperature range; -55 to +1250 C ~ 135 150
V+'" -25°C
30V r----
Device Dissipation Po 3 +25 0C 130 140 150 mW
MAXIMUM RATINGS, Absolute-Msximum Values:
RS =
DEVICE DISSIPATION:
1.5kll
r----
UptoTA"'250C • • • • • • 700 mW
+B50C 145 150
Above T A • 25°C. • • • • • derate linearly 5.6 mWJOC
AMBIENT TEMPERATURE RANGE:
Operating . • . • . • • • -55 to +12SoC Currenl Drain a11O.5 Volts IT 3 VIOI1l = 10.5 V 4 6.5 9.5 mA
Storage . • . • • . . • . -65 to +1 SOOc Zener Regulated Voltage DC
LEAD TEMPERATURE lOuring Soldering): VlOl1I 3 10.9 11.B 11.B V
SupplV Voltagaat terminal 10(1)*
At distance 1/16" ± 1/32"
Quiescent Operating Current into
(1.59mm±O.79mm)
fram case for 10. mIDI.. • • . • • Terminal 2(3) 12(3) 3
1 1 1 4 mA
Quiescent Operating Voltage at V4(5) V+=30V 5 6.9 S V
TerminaI4!5) RS=1.5 kr!
Quiescent Operating Voltage at 5 6.9 8 V
I
TerminaI5(S) V5IS)
Output Offset Voltage between V4J.i ·1 0 1 V
Terminals 4 and 5(S and S) 15·8)
DYNAMIC CHARACTERISTICS (AS RF AMPLIFIER IN TO·5 STYLE PACKAGE)
V+=+30V Correction Voltage Dutpul
Inpul Voltage Sensitivity 5
sensYtlvity VI'" 18 mV as shown in table below.
Input Admittance ill 0.41 + il.O mmho
Reverse Trlllsfll Admittance f = 45.75 MHz 0·il.4 ~mho
il1 V+=lOV
Forward Transfer Admittance i21 R8 = 1.5 kr! 14.5· i29 mmho
(a) CA3tJ64 (b) CA3064E Output Admitt.,ce i22 0.04 + iO.9 mmho
Fig.2 - Terminal auignmsnt diagram•• OUTPUT vs FREQUENCY DEVIATION - AFC
v+ =+30 V %of %of
VI'" 18 mV RMS
fo"'MHzas Vl0 Vl0
indicated 111 11)
V 45.750·0.030 85 V
Correction-Control Voltage at 6.7
TerminaI4(S) carr. 5 45.750 • 0.030 25 V
415) 45.750·0.900 BO V
[Link] 35 V
7
45.750·1.500 BO V
[Link] 35 V
45.750·0.030 25 V
6.7
45.750 • 0.030 85 V
Correction-Control Voltage at V 45.750 ·0.900 35 V
TerminalS(8) corr. 5
[Link] BO V
Fig. 3 - Test setup: Measurement of total device 5181 7
45.750·1.500 35 V
dissipation, zener regulating voltage,
45.750,1.51l1l 80 V
quiescent operating current at
terminal 2 (3). * Terminal numbers in parentheses are for 14-lead dual-in-line plastic package.
335
CA3065
IF Amplifier-Limiter, FM Detector, FEATURES,
• Electronic attenuator· rep'aces conventional
volume control
Electronic Attenuator, Audio Driver • Differential peak detector. requires one single
tuned coil
• Internal Zener diode regulated supply
For Telnisi.. SOInd- System Applications • Inherent high stability
The RCA CA.'1065 Television Sound System i. a performs the conventional volume control function. Vol- • Excellent AM rejection.5O dB typo at [Link]:
monolithic integrated circuit which combines a multi... ume control is accomplished when the bias levels in the • Low harmonic distortion
stage IF amplifier limiter, an liM detector, an electronic attenuator are changed by means of a variable resistor • High sensitivity .200 J..LV limiting (knee) ot 4.5 MHz:
attenuator, a zener diode regulated power supply, and connected between Terminal 6 and ground (attenuation in • Audio drive capability-6mA p.p
an audio amplifier-driver that is designed to directly excess of 60 dB is attained). Because no audio signal is • Undistorted audio output voltage - 7 V pop
drive an npn power transistor or high-transconductance present in this control. hum or noise pickup can be by-
tube. Because the circuit is 80 inclusive. a minimum passed. In most cases. only a single unshielded wire is
Dumber of extemal components is required. A block required between the IF board and the variable resistor
diagram of the integrated circuit television sound sys- <volume cootroD.
tem is shown in Fig. 1. The CA3065 utilizes a 14-1ead dual~in-line plastic
The CA3065 with its advanced circuit design pr0- package with leads specially formed to facilitate auto-
vides a high-performance multistage subsystem for the matic insertion of the device into suitably punched printed--
sound system of a television receiver. A particular fea- circuit boards.
ture of the CA3065 is the electronic attenuator which
MAXIMUM RATINGS, Ahso/ut. MGK;mUm Volues, at TA. :: 2So C
Input Signal Voltage (between Terminals 1 and 2) ••• ±3 V
Power Supply Current (Tenninal 5) ••••.•...•.•. 50 mA
Power Dissipation:
Up to TA = 25°C.............. .••••••• . 850 mW
Above TA =25°C •••••••••••••.•••.•..•• Derate linearly 6.67 mW/oC
Ambient Temperature Range: ·LI·I& ..H _........
Operating ........................................ . -40to +85 QnJM..OAO£DI·Ii~ TO e~
ALL~[Link])ESAREIHDHMS
Storage ...•••••••••••••••••••.•...•. -65 to + 150
Fig. ,. Blocle Jiagram 01 CA3065 i" a typical circuit application .
Lead Temperature (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79mm)
from case for 10 seconds max. .. ................... . +265
MAXIMUM VOLTAGE RATINGS at T A = 2Sa C
The following chart gives the range of voltages which can be applied to the terminals
listed vertically with respect to the terminals listed horimntally. For example, the MAXIMUM
voltage range of the vertical tenninal9 with respect to terminal 3 is 0 to +4 volts. CURRENT RATINGS
TERM-- TERM- tou
',N
INAL 10 11 12 13 14 INAL rnA mA
No. N••
SUBSTRATE:
SUBSTRATE CONNECTION - ALWAVS CONNECT TO TERMINAL 3 4 CONNECT TO
TERMINAL 3
+13 +13 +13 +13 +13 NOTE
o 0 0 0 0 1 5 50 1
+13
is -5 • 1 1
~--+---+---+---+---+-~+---+-~~
+1 2!
~ +13 1
V)
7 1
-4 z ~ 0
r---+---+---+---+---+---+---+-~8
.J Z
b
r-__+-__+-__+-__+-__+-__+-__+-~z"00 8 0.5 6
~-r~--+--r-+--r-~~
~ +4
0 • 1 1
+4 10 1 0.1
10
-5
INTERNAL CONNECTION INT. CONN.
11 11
DO NOT USE DO NOT USE
+4 12 0.5 6
12
-1
13 13 1 2
14 +3 14 1 0.1
-5
+5 +5 1 1 0.1
-5 -5
+, 2 1 0.1
-5
3 0.1 50
Note 1: Taminal No.5 may be connected to any positive
voltage throulh 8 suitable resistor provided that
the current.d dissipation ratinls of the CA3065
are not exceeded.
*Voltales are not normally applied between these terminals.
Voltages appearing between these terminals will be safe If
specified limits between aU other terminals twe not exceeded.
__________________________________________________________________ 337
CA3065
OPERATING CONSIDERATIONS
The CA3065 may be used. to drive a video output
transistor or a high-tJ"ansconductance output tube.
As in all TV receivers, precaution should be
taken to prevent destruction of the CA3065 in the event
of cascade arcs originatir,g in the picture tube or in the
output tube. In the case of arcing in the output tube a
resistor of 150 k in series with tenninal No. 12 and the
grid of the tube is usually sumcient protection.
To prevent damage from picture tube arcs, a careful
(a) rest circuit
lit
. .. 10M 100 It
RESISTANCE IRxl FROM TERMINAL 6 TO GNO-OHMS
... "'EO
analysis of board layout and coupling modes <electro--
static or magnetic) may be necessary to suggest alter-
nate ll!U'outs or appropriate locations for the placement
~
. 92CS·I$118 of spark gaps to absorb the high energy discharge•
Fig. 7. Gain reduction ys. resistance
(terminal 6 to gnd)
M
1'.
15
"
"
5
\
FREQUEMCY _IIIHa
(b) Response curve
Fig. 6 . Frequency response 01 of-amplifier
section of CAJ065
02SS'4438
(d) Printed circuit board - bottom view· (b) Parts layout - top view *
Fig. 8 . Recommendea parts layout for TV receiver
sounG strip using CA3065.
• A 200 mil square grid was used in the layout of passive components on the
printed circuit board. The Quad·in·line formed leads conform to a standard
grid spacing of 100 mil centers.
___________________________________________________________________ 339
CA3066,CA3067
rT-;=~+=1=I====~ +11.2 V +11.2\1
20
•4
. .4
" . '.2
,_
OUTPUT
'--'V'>I'v--+-____ +20V
AU. RESISTANCE VALUES ARE IN OHIIS
Fig. 2· Static chsnH:teristic. test circuit for CA3Q66.
UNLEUOTHERWISEIHOICATEO. OSCILLATOR
OUTPUT
ALLCAPACITANCEVALun
LE5STHAHI.OAAEIHIIICROFARA05
I o OR GREATER "RE IN PICOF"RAOS
AU. COILS "AVE A 000 >:JJ
Fig. 4 . Dynamic characteristics telt circuit for CA3066.
DYNAMIC CHARACTERISTICS TEST PROCEDURE
Steps 1, 2, and 3 are performed with no Chroma input of the "line" amplitude. The chroma input ('111) is in
IV1· 0) peak·to-peak volts of "Iine" amplitude,
1. Adjust ACC potentiometer for V2 '" +O.65V. 6. The chroma output (v14) is the same as the chroma
2. Adjust Killer potentiometer for V4 '" +1.2V. input ('111) except that the burst is removed and keying
3. Adjust capacitor ex (crystal trimmer) so that overshoot occurs in the retrace period. The chroma
frequency of oscillator is 3.579545 MHz. output is in peak-to·peak volts of ··line" amplitude.
CHROIfA INPUT-PERCENT 4. Unless otherwise noted, the chroma gain control is at 7. The oscillator output (va) is the CW output at terminal
maximum gain (fully clockwise), NO.8 and is in peak-to-peak volts. Some modulation
Fig. 3· TypicB/ ACC ch8rac/1Jl'[Link] of chroma output ...
5. The chroma input test signal is a 52.5 p,s "line" at of oscillation dampening between burst injection is
Chroma input fDr CA3066.
subearrier frequency, and 10 cycles of burst at 46.5% visible.
CA3067 CHROMA OEMODULATOR
The CA3067 contains the separate functional systems of a
de tint control and a demodulator. The phase shift of the tint
amplifi.. system is accomplished by functional control of the
fixed phase signal from the CA3066 oscillator output. This
regenerated reference subearrier is applied to terminal No.3
and driven differentially into phase shift circuits. The tint
adjustment controls the vector addition of phase shifted
signals after which a limiting amplifier removes any remain-
ing ampUtude modulation. The output of the tint amplifier
at terminal No. 1 is phase separated for the required
reference subcarrier phase at terminal No. 6 and No. 12
(terminal No. 12 lags terminal No, 6 by approximately 7601.
These terminals are inputs to the demodulator drive amp-
lifiers. The demodulators consist of two sets of balanced
detectors which receive their [Link] subcarrier from the
demodulator drive amplifiers. The chroma signal input from-
the CA3066 is applied to terminal No. 14. The chroma signal
differentially drives the demodulators. The demodulation
components are matrixed and dc·shifted in voltage to give
R-Y, G-Y, and a-y color difference components with
close de balance and proper amplitude ratios. The output
amplifiers of the CA3067 are specially designed to meet the
low-impedance driving source requirements of the high-level
color output amplifiers. A special feature of the CA3067 is
R-C filtering of high frequency demodulation components.
Terminal No.4 is a zener diode for use as a regulated voltage
reference at 11 ,9V, When the zener reference element is not
used, the power supply should be maintained at +11.2 ±O.5
volts.
,-----..---<7)..!...----.. . . +11.2 v
NOTE'Q51THROUGH~IAREE"ITTtRF(lLLOWERS
llLL RESlSTANCE VAW£S AIIl" IN OHMS
ALLCA""CITANCE\lALUUAIIl"IN,F
'----~W;::....-_+20\l
92CS-11~O'
Fig. 5 - Static characteristics test circuit for CA3067. Fig. 6 - CA3067rchemlltic dia,sm.
341
CA3068
Television Video IF System FEATURES:
• [Link] wide-band I F amplifier: 75 dB typo at 45 MHz
• Gain reduction with [Link] stability: 50 dB typo at 46 MHz
RCA·CA3068 is a monolithic integrated circuit that in· noise immunity and minimal airplane flutter. An isolated • Video detector with linear characteristic.
corporates an entire video TV-IF subsystem on a single chip. zener reference diode. incorporated in the IC. provides a • Vi~ amplifier: 12 dB gain
Innovations in integrated circuit design, in addition to the convenient and economical means for controlling the regu· • Impuhe noise limiter
many active devices and closely matched components uti- lated voltage supply. The inherent wide bandwidth capability • Keyed AGe with noise immunity circuits
lized in the circuit, make the CA3068 ideally suited for use 110·70 MHz) and high overallgoin IB7 dB) make the CA306B • Dolayod AGe for tuner
in color and black-and-white TV receivers. suitable for other AM IF applications whose frequencies • 8ufferod AFT output
The ~imarv functions performed by the I F subsystem are range within this bandwidth. • Sepal'llta sound IF interclrri.
video IF amplification. linear detection. video output ampli- amplification
The CA3068 utilizes a unique 2O·lead quad·in·line plastic
fication, AGe from a keyed supply. AGe delay for tuner. • Sound Clmer detector
package. This package also includes a wrap·around shield • 4.5 MHz sound carrier amplifier
sound carrier detection, sound carrier amplification. and a
that serves to minimize intertead capacitances.
buffered AFT output. The advanced circuit design of the • Isolated zen. [Link] for
CA3068 also includes secondary functions for improved ngulatod [Link]
• See ICAN-6303. or. Si..... IC lor
tho Complete PIX·I F Systam In
MAXIMUM RATINGS, Absolute Maximum VoIUBI. at TA - 2ft'C TV Raeeivers" for Schematic Diagram
DC Supply Voltage:
Between Terminals 15 and 6- ................................•..................... 11.3 V
Terminal 7 (Collector to ground) •................................................... 20 V
Terminal 9 tColiector to ground) ....................................... . 20 V
DC Current (into Terminal 18) ••••.....•............•..........•.••.................. 2 mA
Device Dissipation:
~to~-~C ................................................. . 600 mW
AboveTA-60·C ••••.•..•••................••.........•.•....•..... derate linearly 6.7 mWfC
Ambient Temperature Range:
Operating ........................................................ . -40 to +85 ·C
Storage .............................. . - 65 to +150 ·C
Lead Temperature (During soldering):
At distance not less than 1/32" (0.79 mm) from case for 10 seconds max. +265 ·C
- Thil rating does not apply when using the internal zener reference in
conjunction with tklt pau transistor.
HI-50 IUlPOTENTIOMETER
kEYING L.I"Z.Z,.H'ADJUST Mo. OF TUltNS FOR ALIGNMENT
~'" LZ"1,5 ,.H'AO.,lUST No- OF TURNS FOR ALIGNMENT
C .. I pF: AO.,lUST FOR PROPER AUGJlMENT
AlL RESISTANCE VALUES ARE IN OHMS
UNLESS OTHERWISE INJ)ICATEO. ALL CAPACITANCE VALUES;
LESS THAN 1.0 ARE IN MICROFARADS
1.0 OR GREATER ARE IN PICOFARAOS
Fig. ,. Functiomlblod< diagram of"," CA3068.
(a) Test lfltup for meastlnNTUlflt of video sensitivity. sync. tip ItlWII. delay bias. AFT drive volta,..
'0
'0
_'~""1r-
,. 1.-.0...-1
,
ALL REStSTAHCE VALUES ARE IN OHMS
./1.
[Link] LEVEL "a"1OGIV£
ATTEMJATION OF IIfXER
2- "b" 10 THAT
4:~I'i!?,o
WlWIFO....
(b) Tsst 6Btup for mBiIIuremlllt of BOund and chroma outpUtI.
Fig. 2 - T... circuit for ""*"'IrtlmlJllt of white lelfli IV,g) and terminlll2 001_ IV2). Fig. 3 - TypiCBI dynamic hilt circuit dillfll'lllnS.
_________________________________________________________________ M3
CA3070, CA3071, CA3072 Types
Television Chroma System SYSTEM FEATURES
parforms the demodulation function.
~
The RCA CA3070. CA3071. and CAJ072 ar. monolithic
silicon in_ated circuits that constitute a complete chroma • Vo~ Controlled Oscillator
The CA3070 utilizes the 16-1..t plastic [Link]-line package; • Koyad APC. A c e _
system for color television receivws. The CA3070 is 8
the CAJ071 and CAJ072 •• supplild 14:leod plastic
complete subcarrier regeneration system featuring a new dual-in-line packages. • DC Hue Control
concept of phase controlappliaj to the oscillator circuit. The • _ Regulator
CA3071 is a chroma ampUfHr system and the CA3072
CAJ071
• Ace Contra". Chrome Amplifier
• DC Chrome Goin Control
.•.,....,,"
• Color Klier
CA3070 • Amplifi. -.·Clrcult_on
CA3072
Chroma Signa. [Link] • Synchronou, D _ with Col.. D _ Matrix
The CA3070 Is a oom.... ,,-,,1. _ation _
willi automatic phno oontrol applied to ilia _illator. N1
amplilled c:IIrorna ....1 from ilia CAJ071 i, appIlld to
IIrminals No. 13 and No. 14. which .-.1111 autometie phno
p-.
• Emlttar·Fol_ Output Amplifiers willi Short-Circuit
oontrol lApel and ilia automatic chroma oontrol (Acel in·
puts. APC and Ace _ . . . I, keyed by the horizontal
pulso which also Inhibits ilia _1I1ator output amplifier
during the bunt interval.
The Ace _ UIII a syn\:hronOUI _ ... to _lop a
COfI'ection ""~ at tho dlfforenti.1 output IIrminli Nos. 15
• 16. This oontrollipl i, epplled to tho Input IIrmlnll NOI.
1 • 14 of tho CAJ071. The Ape _ eioo .... e synchro-
nous detector. The Ape error ...~ is InWnaI'y coupled to
tho 3.66 MHz oscillator at balance; tho pi.- 01 ilia ,ipl.t
!arminll No. 13 I, In quadratura willi ilia _1I1ator.
To acoompllsh phasing "-Iremants. In RC phno shift
network is ulld t:.etw.. the chroma Input a'td terminll NOI.
13 and 14. The _ loop 01 tho oscillator Is from
[Link] Nos. 7 and 8 back to No.8. The some ocillator
signal is available at terminal No.. 7 and 8. bUt the de output
01 the Ape d _ controls tho relative slgnel 1_ It
_minll Nos. 7 or 8. BeceUil the output at terminal No.8
is shlftod In phase comporod to ilia output It _mlnel No.7. I
which is Ippilld directly to tho crystal circuit, control of ilia I
_ amplltud. It tarmlf1l\l Nos. 7 and 8 ai_ilia phase I
In ilia _back loop. thereby chenging tho frequency 01 tho I
crystal oscill'tor. 8alenca Idlu_ts of dc . - ere L_~ ______ -cS'a;1>-~
provided to _blilh an Initial no·lignal offIet oontrol in 1111
Ace output. and a no-sl...... on·frequency I d l u _ FIll- , - Simp/1fIIId bIocIc d;.,.m of TV chrome_.
through tho Ape dltlCtor..mpllll. circuit which controls
the _iIIator frequency. The _lIIator output stage is
d_tlllly _1I1d at IIrminei No,. 2 and 3 by tho hue
control Input to tarmlnal No.1. The hue pi.- shift i, 13 12 II
IOOOmpli_ by 1110 ...tarnal R. L. Ind C componants _
couple tho oscillator output to the demodulator Input
tarminals. TheCA3070includ.,
a 12"'1Olt de supply.
"'unt regulator to _blish
.
-..
Mlxlmum Vo..... and Current Ratings at TA - +25°C
Voitaga'" Current
T_minll Min. Terminal 11 10
No. Volts VollS No. mA mA
1 0 1 20 1
2 0 +16 2 - -
3 0 +16 3 - -
4 -5 N2 4 20 1
6 - - 10 N3 1
7 - - 11 - -
8 - - 12 - -
10 0 N3 13 20 1
11 0 Nl 14 20 1
12 0 Nl
• With respect to terminal
13 0 Nl No.6 and with _mina'
14 0 Nl No. 10 connectod IIIrough
4700 to +24 V.
15 0 +16
Nl Regulatod voltage It tarmi
16 0 +16 nol No. 10.
N2 Controilld by mex. ,nput ALU'£SI'TANC£ YALUfI AilE: INOHMS
current
[Link] by dissipation.
Fig. 2 - _tic dlllll''''' CAJ070.
-----------------------------------------------------~
CA3070, CA3071, CA3072 Types
CA3071 Chroma Amplifier MAXIMUM RATINGS, AbsoIuiw Mllximum· VsI_ at TA ~ 21f'C
The CA3071 is a combined two-stage chroma amplifier and The de voltage level at terminal No. 13 rises as the ACe
DC Supply Voltage ( I erminal 8
functional control circuit. The input signal is received from differential voltage decreases with a reduction in the burst
the video amplifier and applied to terminal No. 2 of the amplitude. At a pre-set condition determined by the killer to Terminal 4) 30 voe
adjustment resistor the killer circuit is activated and cau_ Device Dissipation:
input amplifier stage. The first amplifier stage is part of the
the 2nd chroma amplifier stage to be cut off. The 2nd UptoTA=+70°C ................ 530 mW
ACe system and is controlled by differential adjustment
Above TA '" +70°C .... Derate Linearly at 6.7 mWfC
from the Ace input terminal Nos. 1 and 14. The output of chroma amplifier stage is also gain controlled by the
adjustment of de voltage at terminal No. 10. The output of Ambient Temperature Range:
the 1st amplifier is directed to terminal No.6 from where
the signal may be applied to the Ace detection system of the 2nd chroma amplifier stage is available at terminal No.9. Operating .:.............. -40'0+86 'e
the CA3070 or an equivalent circuit. The output at terminal The typical output termination circuit that is shown. Storage ,............. . . . . . -65 to +150 °c
provides differential chroma drive signal to the demodulator Lead Temperature (During Soldering):
No.6 is also applied to terminal No.7 which is the input to
circuit. Both amplifier outputs utiliz. eminer·followers with At distance 1/32 in (3.17 mm)
the 2nd amplifier stage. Another output of the 1st amplifier
at terminal No. 13 is directed to the killer adjustment circuit. short-circuit protection. from seating plane for 10. mBX. • • • • •• +265 °e
Maximum Vol.... Ind Current Rltin. . . TA • +25°C
Current V.....•
.~
[Link] '"
3.711:
T....I... II 10 Terml'" MIN MAX
No. mA mA No. VOLTS VOLTS
1 6 1.0 1 -5 +16
2 6 1.0 2 -6 +5
3 10 10 3 0 +2
6 1.0 20 6 0 +24
7 6 1.0 7 -5 +5
9 1.0 20 8 0 +30
12 1.0 5 9 0 +24
14 5 1.0 10 0 +24
• With reference to 11 0 +24
terminal No.4 and
with +24 V on terminal 12 0 +20
" No. 8 except for the
rating given for terminal
13 0 +20
14 -6 +16
No.8.
"
,
ALLft[SIITAtIC[YAI..UESAR[UliOItMS
Fig. 6 -Schemtltic diogram for CA3On.
Voltage,
Bin Relerence T... mlnal V" Sl Open. S20pen 173
Ampl No I Cltroma
I~OUI V2 S, 0 pen,52()p1f1 17.
Ampl No I Ouoma
7
OulpulBalanced
Unbalanced
V,
V,
51 Open. 52 Open
51 Open, 52 Closed
'"
13'
Fig. 7 - Static chNBcttlristics rest circuit-CA3071.
Ampl NO 2 Chro~
Input
Ampl No 2 Chroma
V, 5,0Dl!f1.S20~
I.' +14'1
V. 5, CloMd, S2 Open "'6
~t 5, Open. 52 Open 17 24.5 31
Dy... mlcCh ...acII1'IMIC.
"
Amplifier NO.1 Vall. G,1n
Amphloirr No.2 Volt.
Glln
AVI
AV2
E, 30mVRM5 M. .su •• 116
V, . I 0 V IRMS! M.,s"".117
14
,. dB
dB
B
Malt Chrol"lUl Outpul
Vollage ·9 vRMS 11
10'!1. Chroma Gain ContrOl
Reference Voltage VS-V,O
Eg • 50 mVRMS. ad!un Chroma
Glln Control to Change vg to
10% of Mallimum Chroma
Oulput
2.1 3 .• ..• 'Of
B
Output Voltlge. 1(,II,r 011 SI,nPoslhon2
mV
I:g . 50 mVRMS, ildiust "I(,lIer
·9 12 RMS
AdJU$I" 'or an abruptdecrea.e
inVg
Output Volt.,., Chroma Olf ·9 Eg • 50 mVRMS. ad!U$1 [Link]
12 mv
conuol to min Chroma Oulput "MS
Bandwidth
Amplihl1' No.1 12
OW MM, 9, 10
Amph" ... No 2 30
[Link] I!IIpur
,,' k!!
I. SWITCH II IN POSITION I UNLISS OTHlRWt. NOTE:O
lmpadarIC' <,' pF IN TA8L£ OF OTNAlilIC CHMACTE:"ISTtCS
Ampl. No 1 OutP1.I1 2. CHROMA OAIN CONTftOL SIT TO GROUNO UNLESS OTHERWISE
'0' 85 !! NOTE:O !N TAILE OF DYNAMIC CHA"ACTERiSTICS
Impadance
21 k!!
B 3. ALL REI/STANCES IN OHMS
Amp!. No 2111pul 'i2
Impedance
Amp!. No 2 Output
Impedance
<,2
'0 2 .
35 p<
II
Fig. 8 - Dynamic characteristics circuit..cA3071.
____________________________________________________________ ~7
CA3070, CA3071, CA3072 Types
Fig. 14· - OynMnic clwKterl,r;CI fftt circuit for CA3072.
Application Inforlllation
TI =,=,.~:::=iRo.
Lo n .• I'"-_·SO
TYPICAL APPLICATION CIRCUIT FOR THE CHROMA
SYSTEM
Tt =~vi=-~~r~~~.10
The circuit of F;'.15 i is I compl... signli proceaing system ......n"MClIhI,UO_ .. _
lor color TV. The RCA ty.... CA3010. CA3011 and CA3012 LtIt_u
" . _ . . .... _ _..[Link]'_.1LIIII1
_
....
..... . __ , •.
11_ . . .' . _ _ - -
monolithic integrltld circuits .... respectively used IS the
subcarriw ragenerltor. chroml Implifier. and chroml ~,
demodulator.
The input to the system is the chrOml signal which may be
liken from the first or second video . . n il coupt.:l into
tho CA3071 chromo ampliliw th..,..., a ~ filter. The
..""
........t,..
outputs from the system .e the color [Link] sigMls F;'. '5 - Typicol ellrom. ._ fo, colM·TV _ _ utillzln, RCA.cAJ070. CAJOn. and CA3072.
which ... intended to drive high .." amplifiers. luminance
mixing may' be external to the picture tube 011. the difference
signals may be Implified lAd _lied to the picture tube ..id oscillitor transistor (017). when the oscillator output ampll· the different'" drive from the APe detector to transistors
or cathode. where they . . internally mbced with the fl. transistors (02" 031 we cutoff. Tho chroma signal is 012 • 015 which controllha balance 01 013 & 0,4. The
luminence signal. applied to twminll Nos. 13 and 14. There is o.:illator resulting ptw. of the feedback loop is determined by the
Othw Input require....... to tho system in tho _ ..ppty current drive to tho APC and Ace d - . du,l,. tho relltive amplitudes of the oscillator output signal at terminal
...... of +24 volts and tho horizontal koylng pu". The keying inttrwl; bunt separltion is effectivtly accomplished Nos. 7 and 8. The 66 pF capacitor between tanninal No.7
_ .,ppty vo. . . Ihould be maintained within %3 vol.. by tho lilting action 01 Iha detectors. A lurther advan_ 01 end 8 provides the ph. . Ihifting component .as the balance
of the _moncIad value of +24 ....... The total cumnt I ... the keying ICtton is the high lIin mlde po_lble as IIWJIt of of 013 and 014 is varied. In this way the APC detector
tho systwm Is _xlmotaly 70 mililampom. The horl_1 the low lver. current flow of the APC Ind ACe detectors. controls the crystal frequency at which the phase shift is
keyi,. pu" Input to tho su_l. ' - " " ' " Is Ipproxl· High resistor vatues of 82 kUohms at the detector output cancelled in tho leedback loop.
w_
-.
motoIy +4 volts pook and _ _ on tho burst IS _ It
_mml, provide proP« detector bias consistent with the The controls for the CA3070 IU~_ regenerator circuit
. .mlnel NOI. 13 end 14 01 tho CA3070. The pu . . width duty loctor 01 the keying pu". Fo, a keying pu... it are the APC hllance. the ACC balance. and the hue control.
Ihould be mlintlined H clote II poIIible to the recom- is ~ thIt smell.. values of detector ktId resistors be The hue control is I de bllWIce adjustment of the olCillator
mended wlue of 4.5 mil:rosKonch.
output Impllfi.. transistors Cl2 It Q3. A phase delay network
CA3070 Clrcult~ In the abMnc:e of the keying pulse (line period). the resistor, between the output terminals Nos. 2 8t 3 datermin.. the
The CA3070 circuit IS mown In Fig. 2, consists of on R20. biases the oscillltor's output Impfifier trlnsistors 102 a range of the hue control. which for the value shown in Fig.
_il....... au_Ie pheR control (APeI _ ••u.... 031 on by keep;,. their omi_s It a higher po",ntial then 15. is Ipprc»eimately 9d'.
_Ie chroma control (ACCI _ . 1IIb111 00011...... tho _ bi. voI,- as. as.
of ag. and 010. Tho 3.58 The ACC adjustment sets the initial balance of the ACe drive
MHz ..... is now ~t at terminal Nos. 2 • 3.
pray_
output ompIiI;' and. tI1unt 'lIul_. The "unt ..... iator
tho - - , bios liability lor tho 3.5795oC5 MHz Photo(Japhs of OICillOJCOPil traces for one line period at the
twminel Nos. " 2. a'MI 3 1ft shown in Fig.1&. The effect of
to the input of the CA3071 in Fig. 15 (t«minal Nos. 1 and
14 of the CA,3071). The APC is a frequency adjustment of
000I11at..........1 as tho bias to ali lunotlans 01 tho CA3070
tho keying pul. is mown in FIg.16a. Ind th. cutoff 01 tho the oscillator through the balance control of the APe
circuit. The ....1otIon vo. . . is nomlnlily +12 volts .. detector.
moosured It tlrmlnal No. 10. _il...... output .mplHiar I, mown in FIg.16( b) and 16c.
AJ a setup adiustment. for both the ACC and APC, switch S1
The APC end Ace - . we synchronous - . The _II...... _on 01 Iha CA3070 consist. of the loop is or-ned and S2 is closed. The chroma input to the system is
which we keyed by tho horizontal Input pul•. This lorm 01 formed by 018 end the omlttllr driven dillerantill pai,. 013
_ion oIim_ tho need for • burst _ _ as ~n
• 014. The signal output from tlrminal NOI. 7 • 8 is
removed and the de voltage at terminal No.6 of the CA3071
_L
Is nobill. The switch S2 is then ~ and the Ace ad)u_
Indlvicluallmpllflw ...... _ a pooIti. . pul. is ~t It coupled through the _its tuned cryltll circuit beck through to set the voltage at terminal No.6 to that previously noted.
tlrminll No.4. tho olCiliator output is cutoff and th. ...mlnal No.6 to Q1B. 011. The coMector of 011 d,1ves Alternatively. the differential de voltage at terminal Nos. 15
_II ...... drive s.... is diverted to th. APe and ACC
RelerTl,. to Fig. 2, th. APC d _ (Og • 0101
and tho Ace _ (Os. 0eI'" amlttllr driven from tho
_..-L
tho _II...... output ImplH;' and tho APC • ACC do·
011 il amlttllr coupiad to transistor 018. The
000111..... froquoncy and Aha. control is Iccompli_ by
• 16 of the CA3070 may be sot to 0 mV (%2 mVI whon 51
.,d 82 are or-no Ind the CA3071 is removed· from the
circuit .
•••
Fig. 16(a) - CA3070 ..",ino! No. , Fig. 16(bi-CA3070 ..,mlnol No. 2. 3.5 Vp.p O/ICiII."" Fig. 16(ei· CAJ070 ."",ino! No.3. 2.0 Vp-p _";"'0'
7.5 V ooc/'' tor
"flit'" off'" pu/Ie. output; OIHI horizon"" lina. (flitted off during bum). output; "',. horizontJI' lina, (gated off during bum).
_______________________________________________________________ M9
CA3070, CA3071, CA3072 Types
Fig. 21 (a) • CA3072 . terminal No.3 or 4. chroma input Fig. 21(bi- CA3072· ,erminal No.6 or 7. reierence Fig. 21(c) • CA3072 terminal No. 13,4.8 vp-p [Link]~
s;gnilt.220 mVp_p.one horizonralline subcarrier 1.2Vp 'p' one horizontal line
one horizoritalline
Fig. 21(d) , CA3072· 'erminsl No. 11,5.2 vp-p [Link]'pu" Fig. 21(e) • CA3072· terminal No.9, 1.2 vp.p G·Y outpUt,
one horizont.1 Nne one [Link]
___________________________________________________________________ 351
CA3088E
TYPICAL ELECTRICAL CHARACTERISTICS
TEST CONDITIONS
CHARACTERISTIC SYMBOL TA-:ZSOC TEST TYPICAL UNITS
V+-1ZV CIRCUIT VALUES
FIG. NO.
SInk: (DC) C..,...illics
OCV<>,-:
Terms. 1,4.9. 11 Vt. 4,9.11 0.7 V
TermL2,7,8 V2.7.S 1.4 V
Term. 10 V,O 5.6 V
1
Term.f2 V,2 0 V
T.. m.15 V,5 3.5 V
OCC""""':
Tarm.3 13 0.35 mA
Term.S IS 1.0 mA
T.m.l0 110 20 mA
1
Term. 13 1,3 0 mA
Term. 16 1,6 1.2 mA
Dynamic Characteristics
DetactorOutput 30% Modulatton 4 75 mVRMS
Audio Amplifier Gain AAF f= 1 kHz 4 30 dS
4
Audio Distortion
Sensitivity:
VOUT '" l(X)mV
'IN = 1 MHz
0.2
"
At Converter Stage Input Stgnal-to-Noise Ratio (SIN I = 20dB 2 200 pV/m
At R F Stage Input 4 100 pV/m
Total Harmonic Olstonion THO JO% Modulation 4 1.0
Input Resistance: RI
"
At Transistor 01 3500 n
At Transistor 05
NoAGC.
2000 n
Input Capacitance: CI
At Transistor 01 Input signa' frequency 12 pF
At Transistor 05 "INI-l MHz 17 pF
Feedbec:k Capeeitance: CFS
At Transistor 01 1.5 pF
At Transistor as 1.5 pF
The tyPical characteriSttcs for the CA3088E are Intended for Cjuidanca purposes In evaluating thtS devICe for ~Ulpment deugn.
v· ••!!v
Q. RC"·40841 I DUAL GATE'PROTECTEO lIIos/rEn
ALL RiESISTAfrIC[ VALUES .HE IN OHIIIS
ALL CAPACIr"NCE VALUES ARE INIoIICRo'aRAOS
Fig.4- Typical AM broadcast receiver using the CA3088E with optional RF amplifier stage.
353
CA3089E
MAxiMUM 'RAt'NGS~ Absolute Maximum Values, at TA = 2!P C
DC Supply Voltage:
Between Terminals 11 and 4 16 v
Between Terminals 11 and 14. 16 V
DC Current (out of Terminal 15) rnA
Device Dissipation:
Up to TA = 600 C 600 rnW
Above TA • eo<>c derate linearly 6.7 mWPC
AmbientTempe:rature Range:
Operating . -55to+125
Storage ·65 to +150
Lead Temperature (During Soldering):
At distance not less than 1/32" (0.79mm) fl1Jfn case for 10 secQnds max. +265
ALL RESISTANCE VALUES ARE IN OHMS
*L TUNES WITI-lIOOpF(C) AT 10,7 MHr
00(UNLOAOEO)_15 WI AUTOMATIC MFe DIV EX22141 OR EOUIVALENT)
Fig. 3- Test circuit for CA3089E using a single-tuned detector
coil
.•.
·c·
ALL RESISTANCE V"LUES ARE IN OHMS
"T: PRL -Qo(UNLOAOEOHr 15(TUNES WITH 100 pf (CI) 201 Of 34. ON 7132" OIA FORM
SEC -Oo(UNlOAOEO!;r7~(TUNES WITH IOOpF(C2) 201 OF 3'1. ON 7/32"01A FORM
~Q(PER CENT OF CRITICAL COUPLING) AI 10 %
(ADJUSTED FOR COIL VOLTAGE 'Ie )-150 mV
ABOVE VALUES PERMIT PROPER OPERATION OF MUTE ISQUELCH) CiRCUIT
MUTE "E" TYPE SLUGS,SPACING 4mm
CONTROL
FigA· Test circuit for CA3089E using a double-tuned detector
coil.
m
OUTPUT
AFC AMPL IF IER
IFRAME
.,. 100 IX
INPUT SIGNAL-I'V
ALL RESISTANCE VALUES ARE IN OHMS
ALL CAPACTANCE VALUES ME IN PICOFARAOS
Fig. 5-Muting sction, tlCCer AGC, and tuning meter output as a
function of input signal voltage.
Fig.2·Schematic diagram of 'the CA3089E.
________________________________________________________ ----------~5
CA3090AQ
Stereo Multiplex Decoder Features:
• Requires the use of onlv one low-inductance tuning coil
For FM Stereo Multiplex Systems • Automatic stereo switching
RCA·CA3090AQ . a monolithic silicon integrated circuit, is a voltage controlled oscillator (VCQ) so that it produces • Directly drives a stereo indicator lamp up to 100 mA
stereo multiplex decoder intended for FM mUltiplex systems. an output signal to phase-lock the stereo decoder with the • Includes driver for stereo-lamp indicator
The CA3090AQ is the successor to the CA3090Q; it offers pilot tone. A second synchronous detector compares the • Operates from a wide range of power supplies: 10 to 16 volts
three major advantages over the CA3090a ~s follows: locally generated 19-kHz signal with the 19-kHz pilot tone. If • Requires only one adjustment for alignment
1. Can directly drive a stereo indicator lamp with a current the pilot tone exceeds an externally adjustable threshold • Switching from monaural to stereo and stereo to monaural
drain of up to 100 rnA. voltage, a Schmitt trigger circuit is energized. The signal from produces no audible thumps
the Schmitt trigger lights the stereo indicator, enables the
2. Stereo Defeat/Enable control:voltage specifications. • Low distortion: under G.22%(typ.)
38-kHz synchronous detector, and automatically switches
3, Capable of operation with lower distortion. the CA3090AO from monaural to stereo operation. The • Separate dc input permits stereo defeat or enable
output signal from the 38-kHz detector and the composite • High signal output: directly drives audio amplifiers
This stereo multiplex decoder requires only one low-inductance
signal from the preamplifier are applied to a matrixing circuit • Excellent SCA (storecalt) rejection: 55 dB typo
tuning coil (requires only one adjustment for complete
from which emerge the resultant left and right channel audio • High audio channel separation: 40 dB typo
alignment). provides automatic stereo switching, energizes a
signals. These signals are applied to their respective left and
stereo indicator lamp, and operates from a wide range of
voltage suppl ies.
fight post amplifiers for amplification to a level sufficient to
drive most audio amplifiers.
Figure 1 shows the 'block diagram for the CA3090AO. The
The CA3090AO may be used without the stereo defeat/enable MAXIMUM RATINGS, Ab6o!u,...MBxlmum Va'u. at TA - 2fiOc
input signal from the detector is amplified by a low- DCSUPPLVVOLTAGE • • • • • • 16V
function (see Fig. 6) if a control voltage for this function is not
distortion preamplifier and simultaneously applied to both CURRENT AT TERM. 12 • __ • • . • . • 100mA
readily available. In this case, Terminal 4 should be grounded.
the 19·kHz and 38-kHz synchronous detectors. A 76·kHz INPUT SIGNAL VOLTAGE (COMPOSITE)- _ . . 400 mV
signal, generated by a local voltage-controlled oscillator The CA3090AO utilizes the 16·lead quad·in·line plastic pack- AMBIENT TEMPERATURE RANGE:
(VCo), is counted down by two frequency dividers to a age and operates over the ambient temperature range of Operating . _ _ _ . • _ • _ • -56 to +12sOC
-SSoC to +125°C. Storage. . _ • . . . . • • • . -86 to +1 soOc
38-kHz signal and to two 19-kHz signals in phase quadrature.
LEAD TEMPERATUAE (DURING SOLDEAING):
At distance not less than 1/32" 10.79 mm)
The 19-kHz pilot-tone supplied by the FM detector is from case for 10 s max. . • • _ • • . . . _ • +2660 C
compared to the locally generated 19-kHz signal in a
• For ltereo operation, a minimum Input signal vol. . (compotite) of
synchronous detector. The resultant signal controls the 40 mV il required
". to ...'IS,lES'"UL
,8. snREOh ... u S'~""L
,C, s"O£Or.o.l,"[Link]"L
LD,O,HERE"CEsLGUL
L "Y.'OO"', ... ~
t,.C, .. AOV'OE .... ATI.LCE_E .. ""AS'S
Sf~":.\"c."rUf
• HiS'''~Cl .... luES ... E '~OM"S FIg.' -Functional block di• .", of the CA309OAO• Fig.2 - rast circuit for DC characteristics.
:::: ::::J,;.j.
:~~~ ~~~:~
.....•.. ~ t
.~~...
....... - ...., ~~~
~.
:::: ;::. +T~~ .
••• - .- ..... T
V4 > 1.6\1 TO ACTIVATE STEREO
COLLECTOR-TO-EMITTER VOLTAGE IVCEI-V V4< 0.9 V TO DEACTIVATE ST£AEO
Fig. 3 - IndicatorlampcheractBristics (lCw. VCE)- Fig. 4 - Test circuit for use with stereo cklfBat/enabie. Fig. 5 - rest circuit for usa without .tereo dtlftMt!eTlllbl••
_____________________________________________________________________ 357
CA3120E, CA3142E
TV Signal Processors
(uJungle" Circuits)
For Color and Monochrome Receivers
The RCA-CA3120E and CA3142E are mono-
lithic silicon integrated circuit TV signal
processors for use in color or monochrome
receivers_ These circuits provide low-imped-
ance video output signals, stripped synchro-
nization signals in both polarities, and AGC
output signals for IF (reversel and tuner
(forward andlor reverseL
The circuit designs of the CA3120E and
CA3142E feature impulse noise inversion,
delay techniques to reduce the deleterious
effects of impulse noise in the receiver AGC
and sync circuits. In addition, they in-
corporate standard AGC strobing techniques.
The AGC noise lockout circuit is deleted in Fig. 1 - Simplified block disgram of the CA3120E end CA3142E.
the CA3142E.
MAXIMUM RATINGS, Absolute-Maximum Values at TA = 250 C
These devices are supplied in the 16-lead dual-
DC SUPPLY VOLTAGE 30V
in-line plastic package.
DEVICE DISSIPATION:
Features: Up to T A = 55°C . 750mW
- Internal impulse noise processing Above T A ::: 5SoC . Derate linearly at 7.9 mWf'C
- Sync separator - low impedance, AMBIENT TEMPERATURE RANGE:
dual polarity Operating . -40 to +85 °c
- Strobed AGC system - IF AGC output Storage. ~5to+l50oC
- Delayed outputs for forward or LEAD TEMPERATURE (During soldering):
reverse AGC tuners At a distance not less than 1/32" (0.79 mml
- Automatic noise threshold and from case for 10 seconds max. . +265 0 C
AGC detector level control
v'
_ High-impedance video input
_ Low-impedance video output SYNC-
NOISE ([Link]· STAIPP[ItIN
- Choice of external time constants VIDEO OUTPUT
for sync separator
- Negative power supply not required
- R F AGC delay externally controlled
...
".
.n
""
CAll20E
OR
CA3142E
BOTTOM VIEW
I\. LOWZ
RESISTANCE VALUES ..; , VIO£O
ARE IN OHMS OUT'UT GROUNO OIEL..."IOMC
24V
Fig.2- Test circuit for measuring tJlectrical ChllfSC- *
IiIUISTAN(:£ V"'LUU Aft£ IN OttMS
INCLUDEO IN C""120f; ONLY :cr.="
[Link] of the CA3120E snd CA3142E. Fig.3 - Schematic diagram of the CA3120E snd CA3142E.
Refer to Fitp. 7 and 8 for switch .lector
positions.
__________________________________________________________________ 359
CA3120E, CA3142E
TEST CONDITIONS
CHARAC· SWITCH !\lUMBERS TERMINAL
TERISTIC t!21314151819111112113[ 14it5it6111it8it9120 MEASURED
SWITCH POSITION
IT24 2 3 1 2 1 2 3 1 1 3 2 1 2 2 2 1 5 2 6 79 14 •
O----OI,V
8
~ ,:.22!.Fl:
VTH 2 1 2 1 1 4 3 4 4 3 1 2 2 2 2 1 3 1~.V
-.;;:,:;r-v
V5 2 1 2 1 1 4 3 4 4 3 1 2 2 2 2 2 3 19 SW
/I' 15~
VTH(SEP) 3 1 2 1
1 •
3 3 4 1 1 2 1 2 2 2 1 * 1
t '--l~""""''''
14(OFF) 3 1 2 4 2 1 1 1 1 1 1 2 1 2 2 1 1 14 -=- 6V
V2L 1 2 2 3 2 1 1 1 1 1 1 2 1 1 2 1 1 V17
~:. "'F~'
V2H 3 3 1 1 2 1 1 1 1 1 1 2 1 1 2 1 1 V17
V3L 3 3 1 1 2 1 1 1 1 1 1 2 1 2 1 1 1 V18
V3H 3 3 1 3 2 1 1 1 1 1 1 2 1 2 1 1 1 V18 @]
111(CH) 2 1 2 5 2 1 1 5 4 3 1 2 2 2 2 1 5 111 ....
111 (DISCH) 2 1 2 5 1 2 3 6 4 3 1 2 2 2 2 1 5 111
111(LEAK) 2 1 2 5 2 1
Vll 2 1 2 5 1 2
1
3
6
2
4
3
3
3
2
1
2
2
1
2
2
2
2
2
1
1
5
5
111
Vll
0-}J---oov
sw
IJ
1
2
0
V12 3 1 2 5 2 1 1 3 4 3 1 2 1 2 2 1 5 V12
....
VI3(LOW) 3 1 2 5 2 2 3 1 1 2 1 2 1 2 2 1 2 V13
VI3(HIGH) 3 1 2 5 2 2 3 7 4 3 2 1 1 2 2 1 4 V20
114(OFF) 3 1 2 5 2 2 3 3 4 3 3 1 1 2 2 1 5 114
w ~o
114(ON)
115(OFF)
3 1 2 5 2 2
3 1 2 5 2 2
3
3
8
3
4
4
3
3
3
2 3
1 1
1
2
2
2
2
1
1
5
5
114
115
~ "
1
Z
"A.
115(ON) 3 1 2 5 2 2 3 8 4 3 2 3 1 2 2 1 5 115
CAUTION: Remove power before selecting or adjusting switches.
* Reduce voltage at TerminalS until V19 decreases. VTH(SEPI '" VTH - Va-
NOTE: Switch numbers In italics correspond to numbers In square boxes In Figs. 2 and 8.
~02
~.-~
Fig.1 - Telt condition values for [Link] switches' through 20 (switches 6~ 7, and 10 are omitted). MEASURE VOLTAGE
Refer to Figs.. 2 snd B for test circuit and test-condition selector-switch arrllnllflments.
~02
~ ~ MEASURE VOLTAGE
IS!L-.!-- MEASURE \IOL TAGE:
~ ~I
o· •
~ 2~
0-----0 II[ASURE YOLTAGE
~~
- L!.J I ~24Y
10 on
tieL-II •••••
NOTE: The 11IIIIdZ1ld numbers in the _ 110_ ""'"
to the 17 switches (switches., 7, encIl0 . .
_t
omItuclI of the test cir...lt end carreopand to
th ... gi_ in FIIII;2 ~nd 7.
CAUTION: Rem.... . . - r before ..Iectlno '" -.11_·
inglWitch..
fII["'I$TANCI IIALUES
.... E IN OHMS F/fI.B - Tilt CDndlritm
~
""trw
IWiIt:h for
_ _,.,.i#It:I of'" CA372DE _ CA37GE.
-rillf'"
U4V
Fig.9 - TyplCIIlsppliClltion using the CA3720E and CA3742E. (Figure 8 continued on the next page)
___________________________________________________________________ 361
CA3121G
Features:
TV Chroma Amplifierl
• Excellent linearity in dc chroma gain-control circuit
Demodulator • Improved filtering resulting in reduced 7_2 MHz output
from the color demodulators
Provides Complete System for Processing Chroma
• Current limiting for short-circuit protection
When Used with RCA-CA3070 or CA3170
• Good tolerance to B+ supply variations
uG" Suffix Type-Hermetic Gold-CHIP in
• Good temperature coefficient stability
Dual-in-Line Plastic Package • Gold-CHIP for increased reliability
RCA-CA3121G is a monolithic silicon inte- The transistor chips used in the hermetic
grated circuit chroma amplifier/demodulator Gold-CH IP plastic packages are of the sealed- :.. 2500
with ACC and killer control for color-TV junction type designed to provide protection ~
receivers. It is designed to function com- lzooo
against the deteriorating effects of humidity
patibly with the CA3070 or CA3170 in a and other surface contaminents without the ~ 1500
two-package chroma system. Figs. 5 and 6
show a functional block diagram and the
need for a hermetic package enclosure. The
semiconductor junctions are sealed by util-
•
~ 1000
outboard circuitry of a typical two-package izing a silicon nitride passivation layer. A' .00
chroma system incorporating the CA3121G multilayered, highly corrosion-resistant, ter-
and CA3170, respectively. minal-connection system of unique design 100 200 300 400 500 600 100
NTSC CHROMA INPUT SIGNALtTERM.21-mv p_p 9ztS-Z2687
The CA3121G is supplied in a 16-lead dual- is employed.
in-line plastic package with hermetic Gold- Fig. 2 - .Tvpical ACC plot for the CA3121G when
CHIP (G suffix). used with the CA3010.
CIRCUIT OPERATION
MAXIMUM RATINGS, Absolute-Maximum Values at T A • 25°C The CA3121G consists of three basic circuit
Supply Voltage . 30V sections: (1) amplifier No.1, (2) amplifier
Device Dissipation: No.2, and (3) demodulator. Amplifier No.1
up to TA = IS o C lW contains the circuitry for automatic chroma
Above T A = 55 0 C derate lineerly 10.5 mW/oC control (ACC) and color-killer sensing. The
Operating Temperature Range. . -40 to +85 0 C
output of amplifier No.1 (Terminal 3) is
Storage Temperature Range -65 to +150o C
Lead Temperature lOuring Soldering) coupled to the Chroma Signal Processor
At distance 1/16" ±1/32" 11.59 ±o.79 mm) from case for 10 s max .. (CA3070, CA3170 or equivalent) for ACC
and automatic phase control (APC) operation
and to the input of amplifier No.2 (Terminal
4) containing the chroma gain control cir-
cuitry. The signal from the color-killer cir-
cuit in amplifier No.1 acts upon amplifier
Ace No.2 to greatly reduce its gain.
INPUT
The output from amplifier No.2 (Terminal
14) is applied, through a filtering network,
to the demodulator input (Terminal 13).
The demodulator also receives the R-V and
B-V demodulation subcarrier signals (Termi-
nals 7 and B) from the oscillator output of
CHROMA the Chroma Signal Processor. The R-V and
INPUT
B-V demodulators and the matrix network
I contained in the demodulator section of the
I CA3121G reconstruct the G-V signal to
I
I achieve the R-V, G-V, and B-V color differ-
I ence signals. These high-level outputs signals
-f- SU~CA:.'E.
I .
I CA3121G with low impedance outputs are suitable for
L ___ _
driving high-level R, G, and B output amp-
TO Ace
APe DET.
8: 3 --- 4 6 "'--.E:' lifiers. Internal capacitors are included on
AMPLIFIED CHROMA INPUT
each output to filter out unwanted har-
Fig. 1 - Functional block diagram of the CA3121G_
monics. For additional operating information
and signal waveforms, refer to Television
Chroma System (utilizing RCA-CA3070,
CA3071 , CA3072), File No. 468.
________________________________________________________________ 363
CA3121G
R 40 R 41
12K 11K
R3B R43
[Link] 4.7K
O' ~
"K I
I
I
I
I
0'"
13K
I
I 026
016
I 2.2 K
Oil I
AMPL
No.1
2.4 Ie
AMPL. I
a No.2 a
ACC.
01.
CHAOMA I BIAS 023 0.0
GAIN I CIA-
CONTROL
RIT
I CUITA RI8 023 R28 02. 031 030 R32
B-Y A-Y
'40 I 1.2K 5.6K 600
DEMOo.
300 6.8IC 300
DEMOD.
6.8 K
RESISTANCE [Link] ARE IN OHMS
Fig. 4 - Schematic diagram of the CA3121G.
v,
KILLER ADJ.
CA3070
I CA~r70 .J
I
L _____ ~___ 'Q - 7
8 _____
CHROMA
GAIN CONTROL
92CM-22731RI
Fig. 5 - Simplified functional diagram of a two-package TV chroma system utilizin9.
the CA3121 G and CA3070 or CA3170 .
______________________________________________________________ 3~
CA3123E
AM Radio Receiver Subsystem Features:
• Low-noise,low-Rb' rf stage in cascade connection- "'---'-I-_ _ _~.§~H""'-"'""X'ER OUTPUT
Includes RF Amplifier, IF Amplifier, Mixer, eliminates Miller-Effect regeneration and allows con- OSCILLATOR TANK Z 13 AF OUTPUT
Oscillator, AGe Detector, and Voltage Regulator trolled power rise by the choice of external components IZ RF INPUT
• Mixer..gscillator stage with internal feedback - MIXER BYPASS 4 II RF BYPASS
eliminates need for tapped or multl-windlng
The CA3123E· is a monolithic silicon integrated circuit i-+_+"o"-,,'G,,,C CAPACITOR
oscillator coils
that provides an rf amplifier, if amplifier, mixer, oscillator,
AGe detector, and voltage regulator on a single chip. It is • Cascode if amplifier with controlled output impedance
8 SUBSTRATE AND
intended for use in super-heterodyne AM radio receiver and negligible Miller Effect - IF AMPL. GROUND
applications particularly in automobiles. The CA3123E is eliminates regeneration and selectivity skewing
supplied in a 14·lead dual-in-line plastic package and operates • Frequency-counter AGe circuit-
over the temperature range of -550 to 125°C. allows control of AGe response by selection of the T8I'minai assignment diagram.
coupling capacitor
• Formerly RCA Oev. No. TA6155
• Integral regulation with built-in surge protection
• Separately accessible amplifiers
MAXIMUM RATINGS, AbtOlute·Maximum Values:
DC SUPPLY VOLTAGE:
At Terminal No.3 (V+) 9V
At Terminal No.6 OF Output) <. 40 V
At Terminal No. t3 (RF Output) . 20 V
At Terminal No. 14 (Mixer Output) 20 V
DC CURRENT:
Into Terminal No.3 (V+) . 35 mA
DEVICE DISSIPATION:
UptQT A =5So C. 750mW
Above T A = 55 0 C.. . ........... derate linearlv 6.67 mW/oC
AMBIENT TEMPERATURE RANGE:
Operating. -56 to +125 0 C
ELECTRICAL CHARACTERISTICS at T A = 2SoC
I
Storage ... -65 to +15OCC
LEAD TEMPERATURE (During Soldering):
CHARACTERISTIC SYMBOL TEST CONDITIONS
I LIMITS UNITS At distance 1/16" ± 1/3"
Min. I Typ. I Max. (1.59 mm ± 0.79 mm)
SUtic Characteristics In Circuit of Fill_ 3 from case for 10 s max.
DC Voltage:
At Terminals " 4 4.7 v
At Terminals 2, 3,14 6.8 v
At TerminalS 0.25 v
At Terminal 6 '2 v
At Terminal 7 0.76 v
At Terminals 8, 9 v TYPICAL CHARACTERISTICS
At Terminals 10, 11 0.71 v
At Terminal 12 V'2 0.71 v
At Terminal 13 4.0 v
Into Terminals '. 4. 6.7 1, ,1 4 ,1 5 ,1 7 ,
mA
8 •.9,10.11.12 18.19,1'0,1".1'2
Into Terminal 2 '.2 mA
Into Terminal 3 '5 mA
Into Terminal 6 '6 4.3 mA
Into Terminal 13 4.5 mA
mA
'nto Terminal 14
"4 0.170
Performance Characteristics In Circuit of Fill_ 3
Input Signal to Dummv
Antenna at fIN"" MHz,
Sensitivity 30% AM Modulation at 2.3
o 100 200 300 400 500 600
f MOD =400 Hz, for 11 ~V
INPUT VOLTAGE ItJN1-mvRMS
output at Vo
Fifl. , - Control of RF stage by signsl into Tflf'minal No.5.
Ratio of Output at Vo
with Modulation ON and then
Signal-to-Noise Ratio SIN OFF, Input Signal"'loo ",V, 34 43 d8
30% AM Modulation at
'MOD"'400Hz
Input Signal set at
1 MHz. 90% AM
Overload Distortion Modulation, Distortion 160000 400000
atV o must be
< '0%
Dynernic Cheracteristicii For Indicated Stages In Circuit of Fig. 3
p.,... ef Capacitance
,.....
Transcond'lCtance
Sta.. Output Input Output
pF pF n n
RF Amplifier 80 6 750 2 x 10ti min, 140000
IF Amplifier 35 3.5 950 ,04 80000
2500 (Mixer)
Mixer 2000 2x 106 min_
3000 (Amplifier)
Fig. 2- Test c;rr:uit for Fig. ,.
______________________________________________________________________ 367
CA3125E
Television Chroma Demodulator
RCA·CA3125E is a monolithic silicon integrated-circuit MAXIMUM RATINGS,Absolute·Maximum Values at TA =2fi"C Features:
chroma demodulator having three separate demodulators SUPPLY VOL TAGE .. .. 25 V
with independent phase control. It is designed to function • Luminance input
SUPPLY CURRENT ... .. .... 20rnA
compatibly with the CA1398E Ie Chroma Processor as well AMBIENT·TEMPERATURE RANGE, • Blanking control input
as other commercially available Chroma Processors in A-G-B Operating. -40°C to +8SoC • Thr. separate demodulators with independent phase control
Systems of color-TV receivers. The CA3125E is supplied Storage -6SoC to +lSO°C
in a 14·lead dual-in-line plastic package.
• Low output offset voltage. . . . . . . . . . . . . • . . . . . .. 0.4 V
LEAD TEMPERATURE IDURING SOLDERING):
At distance 1/16" ± 1/32" 11.S9 ± 0.79 mm)
from case for lOs max. 26SoC
TYPICAL STATIC CHARACTERISTICS AT TA = 25·C, TYPICAL DYNAMIC CHARACTERISTICS AT TA' 25·C,
V+ = +20 VOLTS V+;;; +20lIolts
SUPPLY CURRENT. .. . . .. . . .... . . 9.6 rnA BLUE CHROMA GAIN:
BRIGHTNESS CONTROL VOLTAGE: Peak·to-peak voltage at Terminal 11 with 1.0 volt
Measured with 8 volts at peak-to·peak applied differentially between
Terminals 11, '12. and 13 ...... 1.4 V Terminals 6 and 7. and with a subcarrier
MAX. OUTPUT DIFFERENCE VOLTAGE: injection voltage of 1 volt peak·to-peak 7.36 Vp_p
Measured between any two of RED GAIN RATIO,
Terminals 11. 12. and 13 . . . . . . . . . . . . . . . . .. ±O.4 V Peak·ta-peak voltage at Terminal 13
MAXIMUM DC DETECTOR UNBALANCE [Link]-peakvoltageatTerminaI11 X 100 ........ 100%
VOLTAGE: GREEN GAIN RATIO,
DC voltage shift on Terminals 11.12. and 13 Peak-ta·peak voltage at Terminal 12 X 100 .•.•..•.. 30%
when Terminals 1.2, and 3 are alternately Peak·ta-peak voltage at Terminal 11
biased 0.5 volt positive. then negative with
LUMINANCE GAIN:
reference toTerminaI14... .......... .. +150 mV
Peak-ta·peak voltage measured at Terminals 11,
12. and 13, with a peak·ta·peak voltage of
0.1 volt applied toTerminals 6 and 7
(common mode). and with no subcarrier
injection ......................... . 0.7 Vp-p
B
OUTPUT
.OUTPUT
.OUTPUT
OEMODULATOR
~~'~:~~flR
INPUT
BIAS
Fig. , - Fllnction./ block diagram Df th. CA3125E.
______________________________________________________________ ~9
\
CA3126Q
2. When the overload detector is used. a large resistor (nom- +24 V
inally 47.000 ohms) must be placed in series with Terminal
r-_--<r''
16 to set the required RC time constant. The same RC 10kO
network series serves to set the killer time constant.
3. The setting of the free-running oscillator frequency requires
the presence of the keying pulse. The free-running frequency
will be erroneous if Terminal 1 is de shorted during the
setting operation because of the de offset voltage introduced
to the AFPC detector.
4. Care must be taken in PC board designs to provide
reasonable 1solation between the oscillator portion of the
circuit (Terminals 6. 7. and 8) and the chroma input
(Terminal 1).
Overload Detector
The overload detector accomplishes two purposes:
1. It prevents oversaturation due to low burst·to-chroma
ratios.
2. It prevents overload conditions due to noise.
Both of these conditions are discussed in more detail in
ICAN-6247. The extent to which the overload detector is used
depends upon the individual receiver design goals. If greater
than 0.5-volt peak-to-peak output is desired, the chroma
output at Terminal 15 can be tapped to yield any desired
degree of overload detector action.
OIroma Gain Control _
The chroma gain control operates by varying the base bias on
current source transistor 025. To ensure proper temperature
tracking of the chroma gain control, it is essential that the
control be operated from a supply source derived from the
reference voltage at Terminal 12. Because the control operates
from a current source, chroma gain is much more predictable
and far less temperature sensitive than controls that steer
2.5 P.I--: r----== 63.S p.s---i d
current by means of a differential amplifier. The typical chroma BUR~ 3.579545 MHl ~ -1~CHROMA
gain characteristic for the CA3126Q is shown in Fig. 3. : , ----=t=- -
i i r--- 4 p.l 046 VCHROMA
Subcarrier Regenerator Oscillator
~VPEAKfMINI
The oscillator filter consists of a 3.579545-MHz crystal, a
68O-ohm resistor, and a 10·pF capacitor connected in series -----i I - - s 1£1 CENTERED ON BURST
across Terminals 6 and 7. A 33·pF capacitor, shunt connected
from Terminal 7 to ground, rolls off higher-order harmonics, Fig. 2-TestcircuitforCA31260.
thereby preventing oscillation at the crystal third-harmonic
frequency. A curve of the typjcal static phase error as a
function of the free·running oscillator frequency is shown in
Fig.4.1t should be noted that the slope of the curve determines
the de gain of the phase·locked loop, i.e., 40 Hz per degree.
:::i! !'
i·
AMBIENT TEMPERATURE fTAI-·c
[Link] AT TERM. 16 (VI6I-% OF Vl2 OSCIL.L. ...TOR FREE-RUNNING FREQUENCY - DEVIATION
IN Hz FROM 3.5'79546 MHz
Fig. 6 -Amplitude and pha,e I18riatiorl' of OICillator
Fig.3 -Chroma fJBin control. Fig. 4-Static phase error. output VI. temPflraturtl.
Thermal Considerations
The circuit of the CA31260 is thermally compensated to
achieve the optimal operating characteristics over the normal
operating temperature range of TV receivers. Figs. 5 and 6
show the oscillator· and chroma-output amplitudes and phases
as a function of temperature (Terminals 8 and 151, respectively.
[Link] the oscillator- &o'id chroma-output amplitudes and phases
are measured relative to the chroma-input phase. The per-
formance of the oscillator free-running frequency as a function
of temperature is shown in Fig. 7. All the temperature plots are
characteristic of the test circuit with the indicated component
types and values given in Fig. 2.
AMBIENT T. .'[Link].,:-"<
Fig. 6 -Ampliwde arid phs_ ""rilltions of chroma Fig. 7-Variation of OICillator frtlfHUrlrI;n, frequtlflCy I!$. t."",flrawre.
output I!$. temperature.
_____________________________________________________________________ 371
Preliminary Data CA3131 EM,CA3132EM
MAXIMUM RATINGS, Absolute·Maximum Values:
5-Watt Audio Amplifiers SUPPLYVOLTAGE.V+ 28V
Features:
• Power Output: 4 W min .• 5 W typo
CONTINUOUS OUTPUT POWER, Po (with
With Integral Heat Sink • Complete amplifier including: preamplifier Itages,
RL'" 8 n and V+- = 24 V) ..... ...... 8 W RMS
MINIMUM RECOMMENDED LOAD power·output amplifier. and integral heat sink
RCA-CA3131EM and CA3132EM are audio amplifiers with IMPEDANCE. RL sn • High power·supply rejection ratio
integral preamplifier stages on single integrated-circuit mono- AMBIENT OPERATING TEMPERATURE. T A • Operating voltage: V+ "" 24 V typ"o
lithic chips. (at 6 W RMS Output Power) .. • Available with internal feedback (CA3131 EM)
Utilizing a uniquely designed package with an integral heat STORAGE TEMPERATURE RANGE
or without feedback (CA3132EM)
sink, these devices can provide a power-output signal in
INV INPUT V- ELECTRICAL CHARACTERISTICS at TA • 25"C. V+ = 24 V
excess of five watts at an ambient temperature of 25°C. INPUT CQMP GNO
The CA3131EM employs an internal feedback network that Values
Characteristic Sym- Conditions Unit
sets the over-aU gain of the amplifier to typically 48 dB. bol Min. Typ.
The CA3132EM omits the internal feedback network. This Input
arrangement offers the circuit designer a wide latitude in the Impedance ZI 200k n
choice of an external feedback network more suitable to a
specific application.
Power Output Po At clipping onset
NON-INV BIAS V- RL = an 4 W
Both types are encapsulated in a l6-lead dual-in-line plastic INPUT SOURCE GND
RL - 16 n W
package with 4 center leads removed.
Closed· Loop
The CA3131EM and CA3132EM are electrically equivalent to
Fig. '-Termi".lassignment of the CA3'3'EMandCA3,32EM. Gain -
and pin compatible with types SN76013 and SN76023,
CA3131EM A f=lkHz 46 48 dB
respectively.
Determining External Component Values (Refer to Figs. 2 &. 3) driving reactive speaker loads. Capacitor CO compensates for I-::SU::!P:!:P::!ly~C=u:::,,:.:e:::nt+I:"'+--t.::z::er~o.!si:!gn:':'::.1_ _+-==-+-cl~O-+_!!:m~A~
The dcquiescent output voltage is set by the voltage at Terminal the speaker inductance and A 0 limits the current surges Total
1. This voltage, in turn, is set by the internal voltage at through ca. Harmonic
Terminal 2 less 'I (input current, fixed by AA + RS' for 04). The value of the coupJing capacitor C9 to the load determines Distortion THO PO'" 50 mW-4 W.
The voltage at Terminal 2 is set slightly above half the supply the low-frequency response of the amplifier. RL := 8 n
voltage to allow for the voltage drop across RA + Re· Closed· Loop Gain Po := 50 mW-3 W,
Filter RBC3 attenuates any ac ripple injected from the supply
line and prevents positive feedback to Terminal 1. The rejection The closed-loop gain for either type is set by the ratio RL; 15 n
(R1 + R2)!R1. These resistors are included in the CA3131EM Noise Voltage Vn f:=20 Hz-20 kHz 1.5 mV
of supply voltage is a direct function of the filter attenuation. RMS
circuit and are external when used with the CA3t32EM. In
The input impedance of the audio amplifiers is a function of either type, the low-frequency value (-3 dB point) is reached
the closed-loop gain and the magnitude of the as current. In
when the impedance of C5 equals the value of R 1.
practice the input impedance is well above 1 megohm. The
input signal, applied through C2, sees an impedance equivalent r- - ----- ------ - -- - - ---- - ______ J''''". ...,._ -------------------------------
to the resistance of RA connected in parallel with the ampli- 1 ~~ - 1
fier input impedance. Hence. the value of RA in most cases is
I
dominant in establishing the input signal impedance.
The value of C1 depends on the regulation of the power
supply. It is possible for the amplifier to work with a value of
i
C1 as low as 0.1 iJF to attenuate high·frequency sig'lals in the i
supply line. Ideally. Cl should be placed as near Terminal 10 IJ~\ ,~'o I
as possible. An electrolytic capacitor should be used for C1 if @---v.·~--t
the power supply is poorly regulated to avoid ripple at the
output.
[ :
..i1---0-l
Capacitor C6 at Terminal 15 provides over·all compensation.
If a 1000-pF capacitor is used for C6, then the first breakpoint
for a 46-dB closed·loop gain occurs at 200 kHz. Higher
capacitance values will cause the constant current from 010
to charge C6 on the positive voltage swing and thus limit the
slew rate at high-signal levels. Because p-n·p transistor Q19 has
a lower gain·bandwidth product (t,-I than the n·p-n transistors,
C7 is connected to Terminal 9 to compensate for gain losses NOTE: AMPLIFIER CIRCUIT IS IDENTICAL FOR
aoTH TVPES EXCEPT FOR INV. INPUT AND
occurring in the negative voltage swings. FEEOBACK LOOP (lNCLUOING R1 AND R21.
THESE CIRCUIT ADDITIONS. SHOWN WITH DOT·
The use of the filter networks ca and RD at the output TED LINES, APPLV ONLY TO TVPE CA31JUM. y- 81AS INPUT OJTPUT v-
GNO SOURCE COMPENSATION OND
Terminal 6 is a standard [Link] for class B audio outputs
Fig. 2-SchBfTJaric diagram of types CA3131EMand CA3,32EM.
ez 92CS- 24974
[Link]'F
!
1000* ..
'A
210kfi
., i 'B
120kn
eB
4100pF
I, "·'--'*'~Iti:=:::;;;~-j
100£'1.
, '0
: ODn
i
* A l00O-pF capacitor is required if input has an open circuit. . Bottom view
• External resistors R1 and R2 are used onlv with the CA3132EM. When testing theCA3131EM,
omit Rl and R2 and connect the (+1 termination of C5 to Tenninal16. Fig. 4-Printed-circuit board factual size) containing
Fig. 3- Test circuit for typ6s CA3131 EM and CA3132EM. the test circuit, shown in Fig. 3, for the
CA3737EM,
______________________________________________________________ 373
CA31340, CA31340M, CA31340QM
ELECTRICAL CHARACTERISTICS I••
Ted Condition.: TA· 25·C. V+· +30 V (applied to Tenn. 1). DC Volume ContrQl. • ~
RX· 75 kG. RL • 16 G. unl.., otherwi.. indicated. Refer'to Fig.2.
L LIMITS
;0
I
~
·, ~"..
~" ~\, ~
., .
" ~
CHARACTERISTIC SPECIAL TEST JUNITS c .....
~ I'S:,_.
w
CONDITIONS Min. Typ. Mix.
··
;0
I
f
Stlltic CharacteristiCi ~
~ 4 -.....:; 'oQo.
Current into Term. I, 11 PO=O 15 30 45 mA 5
2
i;; AMBIENT TEMPERATURE (TA )-2S·C ~
Dynamic CharlCtllriltiCi Z FREQUENCY (r)- IliHI
.•• . ••
[Link] YOlTA6E(Y+)- 33Y
:1 THD-IO ..
IF AMPLIFIER: 01 -1. -1. ..1.-1.-1.
Input Limiting Voltage, fa =45MHz • I.
EFFECTIVE LOAD RESISTANCE CRl.I-A nC'.JOI'8
• 110
V15(1im) f m =400Hz - 200 400 p.V Fig. 3 - [Link] output power as a function of
(at -3 dB point) fj,f = ±25 kHz effective load resistance.
AM Rejection, AMR
I nput Resistance, RI
fa = 4.5 MHz, fm = 400 Hz,
Modulation Index = 0.3.
V15=20mV
V15=35mV
40
-
50
25
-
-
dB
kG
I~.
~
E
J.
··
,
-t---,"r--
1--.
1---
..11
t-:-\1'\"'."'(\ .\&n
CURRENT ~.'T",I
~~
Input Capacitance. CI V15=35mV - 3 - pF
..,
~
.,.~ "/~~
;:100 r----~~ 1'\.._'!I1.o."
is •
DETECTOR: ::1 • ....-: ,.....
Recovered af Voltage i3 4 ~
(Term. 9). VO(af) fa = 4.5 MHz. fm = 400 Hz, - 700 - mV ~ •
fj,f = ±25 kHz. V15 = 100 mV
Total Harmonic Distortion,
(THD)
Output Resistance, RO At Term. 9
-
-
0.8
7.5 -
3 %
kG
I
cu . .•• . .•. OUTPUT
I
POWER(POJ-W
10
92CS-101S4
Fig. 4 - Total supply cu"ent as 8 function of
ATTENUATOR: output po wer.
Maximum Attenuation RX = 0 - 10 15 mV
UNATTENUATED AUDIO:
Recovered af Voltage
(Term.81. VO(at) fa = 4.5 MHz, fm = 400 Hz, - 600 - mV
= ±25 kHz. V15= l00mV
fj,f
Total Harmonic Distortion (THD) - 0.8 - %
AUDIO POWER AMPLIFIER:
Voltage Gain, A(af) f = 1 kHz - 35 - dB
System Total Harmonic
Distortion Po = 1 W(lT= 140mA typ.) - 1.5 - %
THD (System) PO= 2W (IT= 180mA typ.) - 1.6 3 %
THD (System) = 10%
POWER OUTPUT IPo)-W 92C$-105,e
Power Output, Po
(IT = 210 mA typ.)
- 5· - W Fig. 5 - Power dissipation as a function of
output power.
Input Resistance, (RI(af) f= 1 kHz - 100 - kG
t ••
.. With suitable heat link for the CA3134G.
o
_IV ~ It
-20~
REFEREN~EO TO RECOVERED AUDIO AT TERM. 9
VOLTAGE CONTROL AT MAX"'O-4.5 NHz"I-400Hz
6'-±2S kHz
- , I
·40
1
:l\ 1 SIGNAl-TO-NOISE RATI0(6f-0)
0.1
. ..1. • .11
..
RF INPUT ~EVEl AT TERMS. 14~?!S-IfIV
• • .. 100.
Fig. 6 - Recovered audio~ and signal-to-noise
ratio as a function of rf input level.
____________________________________________________________________ ~5
CA31340, CA3134GM, CA3134GQM
v·
I 1VOLUME CONTROlS
I-....--h-@ ~~~E~'u~~:ONrC
~[Link]
-=- t @ ~gNNECTION
I
'52
9k
AIJOIO POWER AMPLIFIER WITH CUNfiENT LtMITING
_ _ _ _ ------l
FI,.7 - Schematic diagram of the CA3134 .
________________________________________________________________ 377
CA3135G
DYNAMIC ElECTICAl CHARACTERISTICS at TA =25°C (See Fig. 4) CIRCUIT DESCRIPTION
LIMITS (See fig. 2 for schematic diagram).
CHARACTI!RISTIC TEST CONDITIONS UNITS
Min. Typ. Max. A video (luminance) signal from the reo
ceiver's "second detector" is coupled through
SI, S2 = 1; S3, S4 = 2 a capacitor to term. 15 with sync·negative
Min. Video Gain VIN = 70 mVRMS, 0.2 0.35 0.5 VRMS polarity. For purposes of the following
f=100kHz,V'6=12V amplifier, the level is clamped at the most
negative point (sync tips) at the input (this
S2 = 1; SI, S3, S4 = 2
is .wu the point at which the final "black"-
M~x. Video Gain V,N = 70 mVRMS, 1.6 2.1 2.6 VRMS level clamping, or dc restoration, is per-
f = 100 kHz, V'6= OV formed). The capacitor at term. 15 is charged
on the most negative excursions of the signal
S2,S4 = I,S1,S3 = 2
by conduction of 04. Positive signal excur-
limited Video Gain V,N = 70 mVRMS, - 0.3 - VRMS sions lift the emitter of 04 into cutoff. The
f=100kHz,V'6=OV signal voltage on R 3 develops a signal current
SI,S3=I;S2,S4=2; in 06. The current passes through 07 and
08, the division of current depends on the
Min. Chroma Gain V, 6 = 12 V; chroma in = 530mVRMS, - 0.095 - VRMS condition of the gain-adjusted signal voltage
f = 3.58 MHz on the load resistors (discussed below). The
S3 -1;S2- 2, V,6 -0 V; chroma in; gain·adjusted signal voltage on the load reo
Max. Chroma Gain SI = 2, S4 = 2 0.5 0.65 0.8 sistors is converted to current by the emitter-
VRMS follower 014 into R 9, and fed into the cur·
530 mVRMS, f =.3.58 MHz
rent mirror, 015, 016, and 017. The output
S2 = I, S I, S3, S4 = 2 of the current mirror develops a voltage across
Video Freq. Response V,N = 70 mVRMS; V ,6 = 0 V; 1 1.9 2.8 R 13. The dc level is shifted by withdrawing
VRMS some current from the input to the mirror.
f = 3.58 MHz
The fixed dc-level shifting current is de·
S3 - 1; S2 - 2; V,6 - 0 V; veloped in R6 and its diode string and is
Chroma Phase Angle chroma in; SI = 2, S4 = 2 12 19.5 27 Degrees mirrored in 013. Because the dc level is
530 mVRMS, f = 3.58 MHz altered by adjustment of the gain, compen·
sating dc currents that depend on these ad·
Chroma Gain Vary V+ from 10.8 V (REF.) to 13.2 V justments are fed into the mirrors through
with V+ V,6 = 50% of V+;SI, S3 = 1 - 1.5 - dB R 13 and R29. The compensations are ar·
Variation S2, S4 = 2 ranged so that, as gain is varied, the dc level
Video Gain Vary V+ from 10.8 V (REF.) to 13.2 V of "black" is approximately constant at the
with V+ V,6 = 50% of V+; SI, S2 = 1 - 1.5 - dB output term. 13. The output is driven by
Variation S3, S4 = 2 emitter follower 01 B, which has a short·
circuit pulldown protection circuit, R 14 and
Typical max. luminance Input before clopping (f - 100 kHz):
019. A constant·current source 020 loads
V,6 INPUT the emitter·follower to prevent distortion in
the emitter·follower that may result from
+12 V 2.5 Vp. p using a resistive load. The constant current
+6 V 0.75 Vp. p is derived by mirroring the current in the
OV 0.45 Vp. p diode D23. The resistor R 15 prevents
serious interaction with another current
source mirrored from this point in case 020
saturates.
The video output signal at term. 13 is coupled
by a capacitor- to term. 12. The polarity has
not been inverted by the first amplifier, and
sync is in the negative direction at this point.
Black·level clamping is accomplished by
application of a flyback pulse to term. 10.
TO PIX nBE Between pulse peaks, 029 is not conduct·
CURRENT SENSOR
ing, and the base of 024 goes up to the
supply voltage so that term. 12 can be at any
voltage between ground and the supply.
While the fly back pulse is positive, that is
loon
during the blanking interval, the base of 024
is held at about 2.B volts. The most positive
signal excursion during that time will cause
024 to conduct with the result that the
capacitor feeding term. 12 is charged until
the most positive point of the signal is just
at the conduction point, about 3.5 volts.
The most positive part of the signal during
blanking is the "back porch" or black·level
reference. During trace time, the signal
92C:M-".01O'"
swings more positive, but the dc level of
Fig. 1 - Block diagram. black is preserved regardless of the levels
___________________________________________________________________ 379
CA3135G
BUFFERED
..
LUMINANtE CLAMPED HORIZ·
OUTPUT CLAMP VIDEO PULSE INPUT
II 10
A---
.,. H2O
'OK
02,1
'K I
I
rL------
·----~_r~-~--_rr_+---------+-_,·I
~--- ---r---- I .......
• PIX
! I D47 I
I ••, I IL"":INANCE
I 10K I I OUTPIIT
I I
I I
I I
I I
I. I
I
zion
...
'2K
I
I
I ."'.
.,.
KlOA
."..
Hili:
ROO
100.
I
I
•••
nOll
I
1
I
I
L --.:'~ ____I
BLANKER
0--- --~
ALL RESISTANCES M£ IN OHMS
'ND
ItcL-ZIOl'IItZ
Fig. 2 - Schematic diagram
+ '2 V o-..,.-----.,------r----,
r+----..,
Fig. 3 - Static characteristics test circuit.
___________________________________________________________________ 381
Preliminary Data CA3136E
TV Video IF Features:
- PLL carrier oscillator with wide pull-in and hold-in range
Phase-Locked-Loop - Excellent low-level detector linearity - Automatic Fine Tuning (AFT) Detector
Synchronous Detector • Noise inversion at video output - Separate output for sound take-off
- Wide range, variable zero-carrier - 12-volt power supnly
for Color TV Receivers level adjustment
The RCA-CA3136E is a linear IC synchro- terminal; an amplifier arrangement for in- LIMITER
verting noise impulses toward the black TUNING
nous detector employing a phase-locked
LIMITER
oscillator to demodulate the 45.75-MHz level; and a separate output terminal (non- TUNING
video if signals in color-TV receivers. The inverting) for the sound if.
GROUND (v-) 3
CA3136E features AFT voltage for dc con-
VIDEO IF
trol of the tuner; an adjustment for the The CA3136E is supplied in a 16-lead INPUT
zero-carrier dc level at the video output plastic "power-stud" dual-in-line package_ APe FILTER 5
MAXIMUM RATINGS, Absolute-Maximum Values: vco TUNING 6
Power Supply Voltage . 15V
10 (:~~~~f!'UT
Power Supply Current 100mA GOING SYNC.)
Input Signal Voltage ~ 1 Vrms
9 ~A~uE~gFF
Device Dissipation: OUTPUT
TOP VIEW
With no Heat Sink:
Up to T A = 25 0 e 1.4 W 92CS-28845
Above T A = 25 0 e derate Iinearly at 11.1 mW/oC TERMINAL DIAGRAM
With Infinite Heat Sink:
Up to T A = lO0e 6.5W
SUGGESTED GENERAL ALIGNMENT
Above T A = 700 e . derate I inearly at 83.3 mW/oC
PROCEDURE
Thermal Resistance:
. 12 0 e/W Fig. 1 shows a block diagram of the CA3136
R8JS (Junction to Stud)
Ambient Temperature Range: in a typical circuit indicating the internal
Operating -40 to +85 0 e functions as well as the external circuitry
Storage -65 to + 1500 e and signals. A 45.75-MHz, 100-mVrms (50-
Lead Temperature (During Soldering): ohm) signal is applied to the VIDEO IF IN-
At a distance 1/16 in. ± 1/32 in. (1.59 ± 0.79 mm) from case PUT (Terminal 4). While monitoring the
for 10 seconds max. VIDEO OUTPUT (Terminal 10). make the
following adjustments in the indicated se-
quence; (1) adjust the VCO TUNING coil
for a dc signal (lock). (2) Adjust the LIMITER
TUNING coil for a minimum dc voltage on
Terminal 10. (3) Adjust the VCO TUNING
coil for 5.2 Vdc on Terminal 5 (with 12 volt
r- - - - - - supply on Terminal 8). (4) Close the AFT
I DEFEAT switch and note the dc voltage at
I the AFT OUTPUT (Terminal 12). (5) Return
I the AFT DEFEAT switch to its open po-
AFT TUNING I sition, and adjust the AFT TUNING coil
I for the same dc voltage noted when the
AFT DEFEAT switch was closed. (6) Re-
move the rf input and adjust the ZERO
INV. AMPL. CARRIER BIAS potentiometer for 7 volts
dc on the VIDEO OUTPUT (Terminal 10).
This final adjustment completes the alignment
procedure.
I
I
I --r-
1>--f --
V'N
I 150 mVrmt
L ~ ~ 'J 7v-----Ob--I. (MODULATION
- • - - - ---- -- - - -.;:;: ;;;S;T;:;C;; ';:;0;';.- - - ENVELOPE)
VIDEO IF INPUT 'v
ov
~
92CM-28848
Fig. 1 - Block diagram of the CA3136 in a typical circuit application. Fig. 2 - Typical detector output linearity.
_________________________________________________________________ ~3
CA3136E
TYPICAL ELECTRICAL CHARACTERISTICS
At V+ =12 VDC, fc =45 MHz, T A =25°C
CHARACTERISTIC SYMBOL TEST CONDITIONS VALUE UNITS
Supply Current IS + 110 60 mA
Video·Output Voltage VlO Zero Carrier Bias Adjust 7 VOC
Noise·lnversion Offset VlO Referenced to Zero· 0.3 VOC
Voltage Carrier Level
Sound I F·Take·Off Output Vg VlO= 7V OC 7.7 VOC
Voltage
AFT Output Voltage V12 AFT Defeat Switch Closed 3 VDC
CARRIER FREQUENCY (fC)-MHz
Oscillator Pull·ln Range 3 MHz 92CS~28846
Fig. 4 - Tvpical AFT output of CA3136.
Oscillator Hold·ln Range 6 MHz
Detector Conversion Gain 30 dB
Video Bandwidth 9 MHz
Carrier Rejection at Video
Output:
fc = 45 MHz 30 dB
2 fc = gO MHz 40 dB
Video IF
Parallel I nput Impedance:
Resistance at Term. 4 Rp 4 kn
Capacitance at Term. 4 Cp 5 pF
Sound Take·Off Output
Resistance at Term. 9 Ro 1 MHz 50 n
Video Output Resistance at
Term. 10 Ro 1 MHz 50 n
- - - - - - - - - - - - - - - - - - - -______________________________________ ~5
CA3137E
ELECTRICAL CHARACTER ISTICS AT T A = 25°C. V+ = 11.2 V
CHARACTER ISTIC SYMBOL TEST CONDITIONS LIMITS UNITS
I Min·1 Typ. I Max. I
STATIC (See Fig.2)
Supply Current IT - 35 47 mA
Reference Subcarrier Input V16 - 6.7 - VDC
Oscillator Reference Inputs V9. VlO - 3.S - VDC
R·Y, G·Y, B·Y Outputs V6.V7. VS - 5 - VDC
Chroma Input V3 - 1.2 - VDC
DYNAMIC (See Fig,3)
Tint and Sensitivity
Limiting Vl1 VI6:200 mV p·p@3.5SMHz 200 300 - mVp·p
Tint Limiting VII VI6=SOO mV p·p@3.5SMHz - 425 600 mVp·p
Tint Amplifier* <1>V11 V16=400 mV P'p,
Phase Reference Term.l = 11.2 VDC -35 -25 -15 Degrees
Tint Control'" V16=SOO mV p.p,
.1>.<1>11
Range Term.l = 1.2 VDC -130 -110 -SO Degrees
Ratio G·Y to R·Y V7 N 6 V16=400 mV p.p, 2S 33 3S %
Ratio B·Y to R·Y VSN6 V3 =40 mV p.p lOS 120 132 %
Demodulated Chroma V16=400 mV p.p,
Output R·Y V6 V3=40mVp·p 350 550 - mVp·p
Color Difference Output
(Bandwidth at 3 dB) V3=40 mV p.p - 900 - kHz
Maximum Color Differ·
ence Outputs:
R·Y V6 1.5 2.2 - Vp.p
V16=400 mV p.p,
G·Y V7 0.42 0.7 -
V3 = 300 mVp·p
B·Y Vs 1.6 2.65 -
"F lesh Detector" Set·Up:
Reference: Term.2=1.6V
Term.l = 11.2 V
Term.16=400 mV p.p Reference
@Oo Reference Angle Set·Up
Term.3= 40 mV p.p
@ 100 Reference Angle
Sl Closed (Term.15 atGND)
"Flesh Detector":
Phase <1>11 - 0 - Degrees
Same Set-up except 51 open
Amplitude VII - 275 - %
"Flesh Detector":
Phase <1>11 Same Set·up except - 0 - Degrees
Amplitude VII Term.3 at 1900 angle - 100 - %
Small·SignalOutput
Resistance (Terms.6,7,S) ro - 50 - n
Small-Signal Input
Resistance:
Term.3 - 3 - kn
ri
Terms.9&10 - 2.5 -
• Phase angle of term. 11 referenced to term. 16 phase angle.
'" Phase angle of term. 11 with term. 1 = 1.2 V minus phase angle of term. 11 with term. 1 = 11.2 V.
_____________________________________________________________________ 387
CA3137E
R24
620
,----
_____________ ___
~ ~--------------J
Fig.4 - CA3137E Schematic diagram.
________________________________________________________________ ~9
CA3139E, CA3139Q
ELECTRICAL CHARACTERISTICS at TA • 25o C, y+", 28 Y CUniess Oth_iseSpecified) CIRCUIT DESCRIPTION
See Test Circuit, Fig. 2 The CA3139 consists of five functional cir·
cuits as shown in the block diagram, Fig. 1
LIMITS
CHARACTE RISTIC TEST CONDITIONS UNITS (see Fig. 5 for schematic diagram) .
• Min. Max.
1) Cascode Amplifier - Consists of emitter·
NO SIGNAL INPUT
follower 01, common-emitter amplifier
Supply Current, 1+ 15 20 mA 02, and common-base amplifier OJ.
Low Voltage at Term. 7' V+ = 20.8 V 11 14.5 V 2) Bias Circuit - Consists of 04 and resistors
Shunt Reg. Voltage 14.5 Rl, R4, R5, and an external resistor (user
12 V
selectable) connected to the voltage regu-
Ouiescent Voltage at Term. 3 4.5 10 V lator, terminal 7. The nominal value of
Ouiescent Voltage 2 at Terms. the external resistor is 9.1 kO. Reduced
Term. 13 connected to Term. 14 6 8.5 V
13 and 14 values will raise the gain of the cascade
amplilier chain, and higher values will
Ouiescent Difference Voltage,
-0.8 +0.8 V reduce the gain. If the gain is increased,
Terms. 13 to 14
the AFT "Bow Tie" width will increase
Ouiescent Voltage at Term. 6 1.4 2.6 V and the crossover slope will increase
SIGNAL INPUT = 15 mVRMS (Unless Otherwise Specilied), Note 3 (become steeper). The input transistor
01 is internally biased, so AC coupling
1= 44.65 MHz 2.2 4.7 is normally used to the input terminal 5.
Correction Voltage at 1= 45.69 MHz 1.2 4.4
V 3) Intercarrier Mixer/ Amplifier - The out-
Term. 13 f = 45.81 MHz 9.6 13.8
1= 46.85 MHz 9.1 12.1 put 01 the cascade amplifier at terminal 9
is also internally connected to the inter-
f = 44.65 MHz 9.1 12.1 carrier mixer/amplifier chain consisting
Correction Voltage at f = 45.69 MHz 9.6 13.8 V
of transistors 013 through 017 and as-
Term. 14 f = 45.81 MHz 1.2 4.4 sociated components. The video IF carrier
f - 46.85 MHz 2.2 4.7 at 45.75-MHz and the FM sound IF
Two·Tone Input carrier at 41.25-MHz are down-converted
4.5 MHz Output f1 = 45.75 MHz at 15 mV 50 200 mVRMS to a 4.5-MHz FM signal by 014. A low-pass
f2 = 41.25 MHz at 5 mV Ii Iter removes the carriers and upper con-
version signal components. The 4.5-MHz
NOTES: 1. 17 = 12 mA maximum at V7 = 11 V. FM signal is lurther amplified and filtered
2. V13 = 0.55 Vz ± 0.7 V by 016 and C3. The FM sound output
3. Resistor from term. 6 to term. 7 = 9.09 KH. Crossover steepens and "bow tie" signal is at terminal 3. The gain with
width increases when resistor is decreased in value. Total peak swing decreases respect to a 5-m V sound carrier (tested
slightly. with a 15-mV video carrier) input signal
v· at terminal 5 is 10 to 40 when the resistor
is connected between terminals 6 and 7
is 9.09 kO.
4) AFT Detector and DC Amplifier - Con-
sists of 06 through 012 and related com-
ponents. The detector inputs at terminals
8 and 10 are connected to the external
discriminator transformer and biased
through the transformer at terminal-6
potential. The total current through tran-
sistors 07 and 08 is held constant by the
current-mirror transistors 010, 011, and
012. External filter capacitors connected
to terminals 11 and 12 assure that peak
detection is accomplished. The AFT out-
put voltages are shown in the Electrical
Characteristics chart, and a graphical repre-
NOTES: L1: ACAP,N.122201 11- ACA',N.l4C11D7
sentation is shown in Fig. 4.
1.u.'OkO ......n ......or .. OC L2: RCA ',N. '4133 D TurnlCc.n. , ..... .zo .....
v............ , ....... M.k ... 4)1, T_ .22 Win, D.o .• O.2fi tlypJ
H O.D.• 0.... I'y,.) 5) Voltage Regulator - An active shunt
DC_. OIU. . . . .' . '00 «Min.' QIUnIoIdId)-l40IM6n.1
3.
......
2. TypiQI No ..... DC PoI"",_ Ar,
eo... .......... Tal Polntl.
'-"'.25M",
........... ·[Link](Typ.,
'-46.lIMH1:
1 - . . - - 0.1I1I1IITyp.1
regulator, consisting of 01, 02, Zl, Z2,
and 05, is included to reduce the dynamic
Fig. 2 - rat circuit resistance.
________________________________________________________________ ~1
CA3143E
TV Luminance Processor Features:
• Black-level clamping
The CA3143E is a monolithic silicon inte- the CA31260 chroma processor and the • Linear de controls for brightness,
grated circuit that performs the luminance CA3137E chroma demodulator, will pro- contrast, and peaking
processing functions of amplification; con- vide a luminance/chrominance system hav- • Horizontal and vertical blanking
trast, brightness and peaking control; blank- ing excellent tracking of controls. The • Operates with standard or tapped delay line
ing; and black-level clamping. CA3143E is supplied in a 14-lead dual-
This device, when used in conjunction with in·line plastic package.
CIRCUIT DESCRIPTION
VI3 +30",
Fig. 1 is a block diagram of the CA3143E
indicating the internal functions as well as
external circuitry and signals. The video
input signal with positive-going sync is ap-
VIDEO INPUT
plied to the input of the tapped delay line.
Signals from fixed taps of the delay line
are applied to terminals 1, 2 and 3 of the
CA3143E. In referring to Fig.4, the signal
from the delay line tap A is applied to the
POSITIVE
video input at terminal 1. The signals from
HORIZONTAL
PULSE taps Band C are summed where VA + VB
= Vsum . The signal (Vsum ) is then applied
POSITIVE
VERTICAL to the parallel connection of the peaking
PULSE
input terminals,. 2 and 3. The videO input
910Q
signal is applied to a non-inverting input of
the peaking amplifier while the peaking input
signal (V sum ) is applied to an inverting in-
"V put of the peaking amplifier.
5O.n$-<---~ Low-frequency video components are un-
1.5 Y
attenuated, while high-frequency compon-
ents are attenuated as a function of the
delay-line tap points. The peaking amplifier
is a differential amplifier, so that the output
92CL-27424 is proportional to V1 minus Vsum' At low
Fig. 1 - Functional block diagram. frequencies, the signal at terminals 2 and
3 is unattenuated, and the peaking ampli-
fier produces no output at these frequen-
cies. However, at high frequencies the signal
at terminals 2 and 3 is attenuated thUS, the
peaking amplifier output consists of high·fre-
quency video. The peaking control setting
determines the amplitude of the peaking sig-
nal which is then fed to the video amplifier ,
where it is added to the video input signal
and amplified. The setting of the peaking
control does not substantially affect the dc
quiescent voltage at terminal 4.
The low-impedance video amplifier output
is at terminal 4. The signal is fed through an
external coupling capacitor to terminal 6, the
black-level clamp input. The action of the
black-level clamp is such that it clamps to
the black level rather than to the sync level.
Refer to the circuit diagram in. Fig.3. Con-
sider the situation where no signal is applied
to terminal 12. Terminal 6 is biased through
diode 02. T,he signal at terminal 6 VVill
clamp its most negative excursion (sync
pulse) to the anode voltage of 02. How-
ever, if a positive pulse is applied to termi·
nal 12 during the sync interval, the anode
of 02 is forced to ground due to saturation
NOTE; ATTENUATION AT '0 kHz MUST
BE AT LEAST 66dB GREATER THAN 92CL-Z742,RI of 017. The clamp is thus disabled, and
THE ATTENUATION AT I MHz terminal 6 will clamp to the next lower
t;ig.2 - Test circuit. signal level, the black level.
__----------------------------------------------------------------393
CA3143E
MAXIMUM RATINGS, Absolute-Maximum Values: The clamped video signal at terminal 6 is
DC SUPPL Y CURRENT (Into Terminal 13)*
amplified and inverted at terminal 7. Blank-
59.5 mA
DEVICE DISSIPATION:*
ing is accomplished by applying horizontal
Up to T A = 55°C _
and vertical sync pulses to terminal 9. The
750mW
Above T A = 55°C _ pulses turn ON p-n-p transistor Q6 which
derate linearly 7.9 mW/oC
AMBIENT -TEMPERATURE RANGE:
shorts the base of transistor 015 to the
Operating . terminal 13 supply voltage. The bright-
-40 to +85 0 C
Storage. . . . . . ness control function is accomplished by
-65 to +150°C
LEAD TEMPERATUR E (During soldering): varying the voltage on terminal 8. The gain
At distance 1/16 ± 1132 inch (1.59 ± 0.79 mm) of the inverter stage remains constant, but
from case for 10 5 max. . • . the de reference voltage follows the terminal
8 voltage. The contrast control function is
* Although the CA3143E is rated for maximum by external circuit resistance to 39 rnA for accomplished by varying the voltage of ter-
dissipation of 750 mW, it is recommended a typical voltage at terminal 13 of 11.8 volts. minal 10_ Increasing the voltage on termi-
that the current into terminal 13 be limited
nal 10 lowers the gain of the video ampli-
fier. This reduction in gain does not sub-
ELECTRICAL CHARACTERISTICS at T A = 250 C stantially affect the de quiescent voltage at
terminal 4.
Test Conditions
Bias Switch Numbers U
Characteristic Volts slls2JS3\S41s~s6Is7js8fs9jsl 01 SII LIMITS N
I CA3143E
"(VI Switch Positions T TERMINALS
VI-VA I 2 ,
For Characteristics Measurements Min. Typ. Max_ S
STATIC
Voltage:
At Term. 13 (V131 6.1 2 1 1 2 2 4 1 2 2 1 1 11 11.8 13.2 V 10-400
I "'
Quiescent Voltage
At Term. 4 (V41 6.1 2 1 1 2 2 3 1 2 2 1 1 3.3 4 5.7 V
Quiescent Voltage
At Term. 7 (V71 6.1 2 1 1 2 2 2 1 2 2 1 1 7.1 7.7 8.3 V
92C$-27423
Current into Term.13
Fifi.4 - Tapped delay line.
(Term.13 Connected
to +11 VI (1131 6.1 2 1 1 2 2 3 1 2 2 1 2 10 19 30 mA
DYNAMIC
Wide-Band Gain
(Note 1) 5.8 1 1 1 2 1 2 1 1 1 2 1 6 8.3 11 dB
Contrast Gain
Reduction
(Note 21 5.8 1 1 1 2 1 2 1 1 2 2 1 27 30 - dB
Peaking Gain
(Note 1) 5.8 1 1 2 2 1 2 1 1 1 2 1 15 18.4 22 dB
Peaking
Gain Reduction
(Note 31 5.8 1 1 2 2 1 2 1 1 1 2 1 16 18 - dB
Max. Intermodulation
Distortion:
2V (Note 4) 5.8 1 - 1 1 1 2 - 2 1 2 1 - 20 - %
3V (Note 51 5.8 1 - 1 1 1 2 - 2 1 2 1 - 40 - %
Note 1: Set 50-kHz generator for 100 mVp-p_ Adjust R 1 Peaking Control· (See Fig.21 for
minimum setting. Measure wide-band gain at terminal 7.
MODULATED
Note 2: Set 50-kHz generator for 100 mVp-p. Adjust R 1 for minimum setting. Measure -----L--.l-------I-MHrSIGNAL
contrast gain reduction at terminal 7_
~
Note 3: Set 50-kHz generator for 100 mV-p-p. Adjust R 1 for maximum setting. Measure
peaking gain reduction at terminal 7. 92CS-27422
Note 4: Adjust Rl for minimum setting. With S2 at switch position 1 and 57 at switch
position 3, set 50-kHz generator for 2 Vp-p. Then with 52 at switch position A = Amplitude of 50 kHz signal at deepest trough
2, set 1 MHz generator for 100 mVp-p. Then with S7 at switch position 2, B = Peak amplitude of 50 kH z signal
measure downward modulation of the I-MHz signal due to the 50-kHz signal. Downward Modulation = B-A
B
Note 5: Repeat step 4 except that the 50-kHz generator must be set at 3 VP-P.
_____________________________________________________________________ 395
CA3144G
YI3 +30V
VIDEO INPUT
+!OV 311A R2
.3
"IIH
YI3 ' - - + - - - {
24114
8.5 y
"".a:>4---.. .
1.5Y
.,.a "OY
50110
BRIGHTNESS
12.3 VOLTS CONTROL
REGULATOR
VOLTAGE
,2eN-28101
Fig. 1 - Functional block diagram.
10 leO.
NOTE: "TTENUATION AT 50 kH, MUST
BE AT LEAST H dB GREATER THAN 9lCL-2:8109RI
TH'E ATTENUATION AT I MHz
Fig. 2- Test circuit.
______________________________________________________ ~7
CA3144G
CLAMP INHIBIT INPUT
------------,
I
I
..,
I,SK
07
BUFFER AMP
t- - - - - ---, BR~tH.-~~~I~· a
~---+--~-. I
•• 7
2.4K I
I
012
I
I
I
I I
~ ______ -L_ _ ___ ...1I
CLAMP
•••
, 2,4K
I
I
,.------;0..
I
I
•••
9.6K
011
M- -----------------~-------~
13 SHUNT [Link] , UBSTRATE
a BIAS
AL.L. RESISTANCES ARE IN OHMS
92CL-Zlr06
Fig. 3- Schematic diagram
minals 2 and 3 is attenuated thus, the peaking during the sync interval, the anode of 03 is
amplifier output consists of high·frequency forced to ground due to saturation of 013.
video. The peaking control setting determines The clamp is thus disabled, and terminal 6
the amplitude of the peaking signal which is will clamp to the next lower signal level, the
then fed to the video amplifier, where it is black level.
added to the video input signal and amplified.
The setting of the peaking control does not The clamped video signal at terminal 6 is
substantially affect the de quiescent voltage amplified and inverted at terminal 7. Blanking
at terminal 4. is accomplished by applying horizontal and
vertical sync pulses to terminal B. The pulses
The low·impedance video amplifier output turn ON p-n-p transistor 018 which shorts
is at terminal 4. The signal is fed through an the base of transistor 020 to the terminal 13
external coupling capacitor to terminal 6, supply voltage. The brightness control func-
the black·level clamp input. The action of tion is accomplished by varying the voltage
the black-level clamp is such that it clamps on terminal 9_ The gain of the inverter stage
to the black level rather than to the sync remains constant, but the de reference voltage
level. Refer to the circuit diagram in Fig. 1. follows the terminal 8 voltage. The contrast
Consider the situation where no signal is control function is accomplished by varying
applied to terminal 12. Terminal 6 is biased the voltage of terminal 10. Increasing the
through diode 03_ The signal at terminal 6 voltage on terminal 10 lowers the gain of the
will clamp its most negative excursion (sync video amplifier. This reduction in gain does
pulse) to the anode voltage of 03. However, not substantially affect the dc quiescent
if a positive pulse is applied to terminal 12 voltage at terminal 4.
_____________________________________________________________________ 399
CA3151G
ffi
20 +. -I
I I
~ 10
I
CA31!)IG
il 0
I%
~~
-10
VCHROM ... AT P,3· 400 fI'IVp~p
NOTE; TINT CONTROl.. ADJUSTED
SO THAT WITH A +t
-20 SIGNAL INTO TERM. f.
THE OSCILLATOR AT TERM.
12 AND THE CHROMA AT
TERM. 13 ARE IN PHASE
+1I.6V
'2CS-29237
10. Fig. 2 - "Flesh" correction of oscillator phase angle
as a function of chroma input phase angle.
0.01
I.
56~H
Fl
lB.390 P
39. ~
(;HROMA INPUT I
TERMINAL DIAGRAM
SAT CONTROL 4
OVERLOAO DEl.
24 HORIZ. KEY PULSE INPUT
AL.L RESISTANCE VALUES ARE IN OHMS
TINT AND KILLER FILTER
75pF 82pF"-=-
CAPACITANCE VALUES ARE IN MICROFARADS CONTROL PROCESSOR SECTION 6
UNLESS OTHERWISE INDICATED 100 pF FLESH 8 CHROMA OUTPUT
OVERLOAD
DISABLE
GROUND 1
92CL-29239
17 TINT CONTROL
Fig. 1 - Functional diagram static test circuit, and typical application circuit.
l
16 CARRIER FILTER
15 "FLESH CORRECTOR"
CARRIER OUTPUT
[Link] II 14 "FLESH COARECTOR- AND
OVERLOAD DETECTOR DISABLE
13 DEMODULATOR CHROMA
INPUT
TOP VIEW
Vee
e2 +11.6
0.01
"=' 2.Z3~S~ r-- -63.5 J!s -_'-1
B~ 3.579545 MHz ~:r:CHROMA
XTAL
3.579545 MHz
820' ,.--1. :--4.27 J!5 VBURST
1.2K
~VPEAK(MINl
5.1 K
--j /.-. 5 fl.s
CENTERED KEY PULSE
ON BURST
2.2 K 0.01
52J2
O~
2700'
5.1 K
8.45 V ALL RESISTANCE VALUES ARE IN OHMS
92Cl-29236
Fig. 3 - Dynamic test circuit.
___________________________________________________________________ 401
CA3153G
MAXIMUM RATINGS, Absolute-Maximum Values:
DC SUPPLY VOLTAGE:
Between Terms. 15 and 4 .......................................... 16 V
Between 470 n connected [Link]. 12 and 4 ............................ 35 V
DC SUPPLY CURRENT:
At Term. 15. . . . . . . . . . . . . . . . . . . . . . . . . .. . ................... 20 mA
At Term. 12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 mA
DEVICE DISSIPATION:
UptoTA =+55'C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .750 mW
Above T A = +55' C ............................ Derate linearly at 7.9 mWI' C
AMBIENT TEMPERATURE RANGE:
Operating ................................................... -40 to +85' C
Storage ..................................................... -65 to + 150' C
LEAD TEMPERATURE (During Soldering):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for 10 seconds m~x ..... +265' C
ELECTRICAL CHARACTERISTICS at TA = 25°C
CHARACTERISTIC TEST CONDITIONS LIMITS UNITS
Min_ Max.
Operating Supply See Note 1
Voltage, V 15 12 14.2 V
Supply Current, 1,5 3 15 mA
Shunt Regulator
Voltage, V 12 10.9 13 V
Shunt Regulator V12=10.5V
Current, 1,2 6 20 mA
Tuner AGC High
Voltage, V 10 18.5 21 V
Tuner AGC Low
Voltage, V 10 0.3 1.3 V
AGC Current. 12 Non-Keyed 80 500 /JA
AGC Current (Peak), 12 Keyed Source Current 0.7 3 mA
AGC Current (Peak!. 12 Keyed Sink Current 150 680 /JA
Horizontal Key Input Through 100 kn
connected to Term. 1 25 35 V
Video Output High At Zero Carrier
Voltage, V16 7 10 V
Video Output Low At 30 mV Input
Voltage, V16 0.9 2 V
Sensitivity Voltage, V 16 At 400 /JV Input 0.9 5 V
Noise - 12 mV(RMS)
Chroma 45.75 MHz, 10 mV;
42.17 MHz, 3 mV 0.7 1.6 V (RMS)
AFT Drive 35 85 mV(RMS)
Distortion 50 kHz, 80% Modulated,
Sync TIP Equiv. 30
mV(RMS) - 10 %
Delay Voltage Through 15kn. connected
to Term. 7. See note 2 0 V15 V
Note 1: V15 MIN. should be at least 0.6 V above Terminal 12 potential. Lower voltage may cause some
"white" compression.
Note 2: Zero voltage corresponds to maximum delay at Signal input -= 30 mV (RMS).
__________~----------------------------------------------------@3
CA3153G
THIRD IF -AMPLIFIER STAGE,DETECTOR,
AND VIDEO-AMPLIFIER SYSTEMS
IC16-0311
QI6,17,19,2I,22,25,27,[Link] 031 ARE EMITTER FOLLOWERS
13
I
R36 R45
I
R3'
2,9K 15K I
,~:h6cgF
1.6 K
R53 R55 I
Z2 R43
!12K R46
75K
100
,---
I
75 K
-
021 Z3 r'
R33 I
F
~~F
4K
r----- C7 025 r; Z4 ~ t- I O~
-£ I
031 R56
.00
~ ~
!C8 ["'F I
R32
5K
23pF
~~ 'R49 V
R64
I
I
03~
02~ IK IK
R34
of
J
R50
l,
tt
L--.... I
4K 14 K
C6 20 R41
I--
19pF ,F 11K 1----------.1
J
R51
R37 02. 5K
r--
~I~~~
J
2K R44
"
J
"-';2.
IK
" J lapF 032
f-:(~
J
J 033
04
J
026
I
R3I R'5 05 J R52
270 130 7. K
J
I CI2
R••
100
R42
100
R47
10.
R48
40 J
I
R54
10 K I5PF T
F
I
--------------------~
08 D. R61
G
~A
041 [Link]
I.
r"
R60
"7r 18 K a4' R63
I
60 pF
CIl
R59
1.4K
f
I R62
OK
10 K
NOISE-GATE AND AGe SYSTEMS
a431
.~
1 034
032.33.35, AND 036 ARE EMITTER FOLLOWERS
92CL-)I067
J
Fig. 2 - Schematic diagram for the CA3153G.
038, 036, and 035 to resistor R57 to form charge and discharge current paths at Ter-
the charge current for the external agc filter minal 2 are turned off. Diode D8 provides a
capacitor at Terminal 2. lower-gain agc path for turn-on during chan-
nel acquisition.
A constant·current discharge path for the
capacitor at Terminal 2 is provided by cur·
rent mirror components D7 and 037 during Noise-Gate System (See Fig. 31
the key·pulse duration. Thus the external The circuit components, Cll, R54, 032,
agc filter capacitor is charged or discharged 033, and 043 perform the function of a sta-
during the key-pulse interval only by the dif- tistical system to reduce agc gain during
ference in current between the charge· and "spike" noise. The noise gate turns on for
discharge currents. At the end of the key- large amplitude fast signals and reduces the
pulse duration, C13 is discharged, and the agc loop gain.
---------------------------------------------------------------------~
CA3153G
+"01
~ ------
5 +VS2 12 SHUNT
_RIg" _ _ _ _ _ _ _ _ _ _ _ _ -,
r-------------
I m _
I R27
I
I 740 I
I I
I I
C2
I 1.9pF I
I I
I Vl5
I r--'VII'v-....
R53 1
100 I
I
I
I
I
I~I~~T
16
ell
7'FJ:
R48
40
R3I
270
R43 R38
£~~I R39 11.21< 100
@ ~ _...: _--=--~ =-~ . ___ ~~ _______________________
QI6,17,[Link].27,30 AND 031 ARE EMITTER FOLLOWERS 92CL _ 3106~
-.J
Fig. 5 - Third IF-amplifier stage, detector, and video-ampfifier systems of CA3153G (016 ~Q31)..
____________________________________________________ ~ _______________ 407
CA3159G
6, which drives the outboard diode phase
detector. Second, the negative pulse cuts off
the current through 036, which otherwise
holds 035 in saturation, thus enabling a
current in R41 to turn 034 on and thereby
shift the noise threshold voltage.
Terminal 7 receives a positive flyback pulse
thatsuppliesR41 with the signal to complete
the coincidence gate that alters the noise
threshold when sync and flyback pulses are
in phase. The buffered and clipped flyback
pulse also turns 043 on, which, in con-
junction with an external integrating ca-
pacitor, forms a sawtooth waveform_ This
sawtooth (at flyback rate) is phase compared
with the sync pulse that was separated from
the video input.
The phase detector works against an internal
bias point brought out to terminal 10, and
the phase detector output applied to terminal
11 is slightly positive or negative relative to
terminal 10. This voltage differential with
terminal 10 determines the division of current
between 09 and 010, which are part of the
voltage controlled oscillator. The oscillator
consists of the current source 011, differ-
Fig. 3 - Schematic diagram of the CA3'59G. ential amplifier 012 and 013, and differ-
ential amplifier 09 and 010. The frequency
is determined primarily by a series LC circuit
Circuit Description 022 in cutoff. 029 has an emitter load connected between terminals 13 and 14
provided by an external 1 kn resistor and a (terminals 12 and 13 have resistor loads to
The negative sync video input at terminal 3
series capacitor: when its base is switched the positive supply). If the entire oscillator
is the detected video if. This video signal is
buffered and Vbe compensated by emitter· low, its collector switches high. The resulting current passes through 010 to terminal 13,
followers 028, 027, and 026. The buffered flow of current in 023 overrides the normal the oscillator operates at the frequency at
video signal is applied between the base negative-going pulse in the direct signal path which the phase shift in the LC circuit is
of 021 and a temperature·stable 2·V refer· and holds 021 in saturation. zero. If the current is sent through 09 to
ence. 021 is normally in saturation, and the The video input to terminal 3 also operates terminal 12, however, it must go through an
negative sync pulse imparts a positive swi ng
the sync channel, beginning with 031_ Be- external capacitor between terminals 12 and
to the base of 020. 020 is used as a peak
cause 032 is normally cut off, 031 acts as an 13 and then through the original LC circuit
rectifier driving a capacitor at terminal 1.
The voltage at terminal 1 is the AGC control amplifer with a moderate gain to its collector, and the circuit is tuned differently. Inter-
voltage that sets the if gain such that the sync and a positive sync signal appears at terminal 4. mediate proportions of current division will
pulses drop to just below the 2 V level, driving If the noise pulse is more negative than the produce intermediate oscillator frequencies_
021 out of saturation. noise threshold at the base of 032, the base of The oscillator current output from 012
The above description is for a normal video 030 is pulled down as discussed above. In provides base drive for the 31_5 kHz output
signal; the presence of noise pulses more addition to operating the AGC noise inverter, at terminal 15.
negative than the sync tip level would lower the 030 current passes through 025 to the
the gain to that level. thus disturbing the amplifier load resistor, R35, and cancels the
picture. A gated noise-inversion threshold potentially positive pulse at that point.
is provide at the base of 032 to compensate The positive sync signal at terminal 4 is
for these noise pulses. The threshold is about coupled through an RC network to terminal
1.5 V during trace time, but is reduced to 5 for sync separation_ In essence, the network
about 1 V during coincidence of the sync permits 038 to clamp the positive peaks, so
and flyback pulses. When the video signal the most positive part of the signal is ampli-
is more negative than the noise threshold, fied by 038 while the rest is beyond cutoff.
032 conducts and pulls the base and emitter The separated sync, a negative pulse at the
of 030 low. Without noise, 023 conducts collector of 038, follows two paths_ First,
0_5 mA with its collector·at 7 V, which holds the sync operates an output driver to terminal
__________________________________________________________________ 409
CA3183G
ELECTRICAL CHARACTERISTICS At T A = 25°C. V+ = 5 VDC. V- - 0 VDC; _ Figl. 1 It 2
LIMITS
CHARACTERISTIC TEST CONDITIONS UNITS
Min. Typ. Max.
Supply Current. 1+ Terms. (1+2), Fig. 1 30 60 90 mA
UHF Bandswitch Input Voltage, VBH High level 2.4 - V
VHF Bandswitch Input Voltage, VBl low level - - 0.8 V
UHF Bandswitch Input Current, ISH VBH=20VDC, Fig. 1 - - 0.5 mA
VHF Bandswitch Input Current, IBl VSl =OVDC, Fig. 1 - - -1 mA
UHF Sensitivity level Input fiN = 450 to 950 MHz,
Voltage, VIN(U) fOUT = f1N/256, Fig. 2 - - eo mVRMS
VHF Sensitivity Level Input fiN =90to 275MHz,
Voltage, VIN(V) fOUT = fIN/64, Fig. 2 - - 40 mVRMS
Output Voltage, Vo Terms, 40r 5, Fig. 2 0.65 1 - Vp •p
Output Voltage Rise of Fall
Time, t"tf - 70 - ns
________________________________ ~----------------------------411
CA3188E
Operational Amplifier (See Fig. 2)
Electrical Characteristics at TA = 25°C, V± & 32.5 V, Vas a 18 V, Terms 4 8& 5 grounded
TYPICAL
CHARACTERISTIC TEST CONDITIONS UNITS
VALUES
Input Bias Voltage. V 13 113 = 4 mAo Feedback = 1 Mn 2.5 VDC
Input Bias Voltage, V13 113 = 6 mA, Feedback = 1 Mn 2.6 VDC
Input Bias VoltaQe, V 14 114 = 4 mA, Feedback = 1 Mn 3.3 VDC
Diode Voltage
(term. 14 to term. 13) 114 = 4 mA, Term. 13 = Reference 0.8 VDC
Diode Voltage
(term. 13toterm. 14) 113=4mA, Term. 14= Reference 0.8 VDC
Output Voltage 114 = 4 mA, Resistance between
Low, VOL Terms. 1 and 12 = 10 kn 0.2 VDC
Output Voltage V14 = 0 V, 113 = 4 mA, Resistance
High, VOH between Terms. 1 and 12 = 10 kH 28 VDC
Input Offset Voltage, VIO V13 = 0 V, Term. 1 connected to Term. 14 10 mV
Supply Current, 1+ V4 = 1 V, Feedback (Terms. 1 to 14) = 1 MH 14 mA
Output Sink Current, 10L 114 =4mA, Vl = 32.5 V 25 mA
Output Source Current, 10H 113 = 4 mA, Vl = V14 = OV -15 mA
Input Bias V13 = 0 V, Term. 1
Current, liB (term. 14) connected to Term. 14 0.5 nA
Common·Mode
Rejection Ration, CMRR 65 dB
Power Supply Rejection
Ratio, PSRR 75 dB
Open· Loop Voltage
Gain. AOL 80 dB
Band-Select Switch (See Fig. 3)
Electrical Characteristics at T A = 25°C, V+ = 32.5 V, VBS = 18 V, Terms. 4 & 5 grounded
Terms. 6, 7, 9 = 100 kn to ground
TYPICAL
CHARACTERISTIC TEST CONDITIONS UNITS
VALUES
Logic Inputs "A" & "B"
100 IJ.A
Sink Current
Logic Inputs "A" & "B"
19 = -90 mA, VlO = Vll = 2.4 V -5 IJ.A
Source Current
Output leakage Current,
2 IJ.A
Terms. 6, 7, 9
Output Saturation Voltage:
Term. 9 19 = -90mA, VlO=V11 =2.4 V 0.6 V
Term. 9 19 = -60mA, VlO= Vll = 24 V 0.3 V
Term. 7 17 = -90 mA, VlO=OV, V11 =24 V 0.6 V
Term. 7 17 = -60mA, VlO=O V, Vll = 2.4 V 0.3 V
Term. 6 16 = -90 mA, V10 = 2.4 V, V11 = 0 V 0.6 V
Term. 6 16 = -60mA, VlO = 24 V, V ll =OV 0.3 V
__________________________________________________________________ 413
Preliminary Data CA3168E
2-Digit BCD-to-7-Segment Features:
DecoderIDriver • Separate BCD inputs and segment outputs for
each digit
For Common-Anode LED Displays • Input loading less than 151lA
• 12L logic with buffered inputs and outputs
The RCA·CA3168E is a monolithic integrated Decoding is accomplished with 12L ROM's. • Internal input over range protection circu it
circuit intended for 2-digit display such as The fourteen output terminals are buffered • 5-V supply operation
"numbers" for TV and "CB" channel se- with Darlington pairs driving common-emitter
lection, and other 0-99 numerical or counting output transistors. Each output is capable of • Internal biasing circuits
for consumer or industrial indicator appli- sinking 25 mA for an LED common·anode • Output drive capability of 25 mA per segment
cations. It consists of two independent display device. The supply-voltage range • Open collector outputs drive indicators directly
BCD-to-7-segment decoder/drivers. Two sets (VCC) is intended to be 4.5 V to 6 V. The
of BCD inputs are buffered with p-n-p output voltage (Va) must not exceed 12V,
differential ampl ifier stages internally re- wh ich provides for a wide range of common-
ferenced to 1.7 V. Each of the eight input anode voltage sources. CA3168E
terminals draws less than 15 IlA and is pro- TERMINAL ASSIGNMENT
The CA3168E is supplied in the 24·lead
vided with an internal protection circuit.
dual-in-I ine plastic package.
MAXIMUM RATINGS, Absolute-Maximum Values:
SUPPLY-VOLTAGE, VCC. 6V
INPUT·VOLTAGE (MIN./MAX.) . -0.3IV CC V
INPUT CURRENT (PROTECTION CIRCUIT) ±10mA
OUTPUT VOL TAGE, Vo . 12 V
OUTPUT SEGMENT CURRENT, IOISPLAY 25 mA MSD SEGMENT
OUTPUTS
AMBIENT TEMPERATURE RANGE:
Operating . a to +70:C
Storage -55 to +150 C
POWER DISSJPATION: TOP VIEW
Up to +70 oC. . . . . . . 400 mW
Above +70 C derate linearly at 8.7 mwtc
LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch (1.59 ± 0.79 mm) from case for
10 seconds max.
MSD SEGMENT
OUTPUTS OUTPUT
CA3168E BUFFERS
MSD
ROM I
MSD
ROM2
'''-''''' 1-4 ~
5
ADDRESS ADDRESS rnTT"-....~"l.
DECODER DECODER ~
>
r-"L._.I""'fi§
H.>--j-{&~_...JH~
,....'" 1---' ~
'---+-"----{I GNO
vee
13
VDISPLAY
92C FIll - 3103 .. OND (DISPLAY SUPPLY)
92CS-31033
NOTE: Functional diagram for least significant digit is identical
to functional diagram used for MSD with the exception NOTE: See truth table for test sequence of input/output logic tests and
of Terminal Assignments (see Terminal Assignment dia- Minimum R LOAD = VDISPLAY - VOL For each of the 14 segment
DISPLAY SEGMENT IDENTIFICATION
gram). A separate LSD Bias circuit, and % of the Output
[Link]
Bias Circuit is used for LSD.
drive output terminals. (LED is not used in test circuit)
Fig. 1 - Functional diagram for Most Significant Digit (MSDJ. Fig. 2 - Test circuit.
_____________________________________________________________________ 415
CA3170G
Features:
TV Chroma System • Voitage-controlled oscillator
"G" Suffix Type-Hermetic Gold-CHIP in, • Keyed APC and ACC delllctors
Dual-In-Line Plastic Package • DC hue control
• Shunt regulator
The RCA·CA3170G is a monolithic silicon The CA3170G is a TV Chroma System of
integrated circuit that performs the func· advanced design that incorporates all the fea-
tions of subcarrier regeneration, ACC and tures of the CA3070E but with the added The CA3170G is supplied in the 16-lead
APC detection, and tint control in color tele· advantage of the modified Hue Control Char· dual-in-line plastic package with a hermetic
vision receivers. It is designed to function acteristic. With the CA3170G, the designer Gold·CHIP (G suffix). The chips used in the
compatibly with the CA3121E TV Chroma can provide a front panel hue contrQI that hermetic Gold-CH IP plastic packages are of
Amplifier/Demodulator in a 2·package functions linearly over its entire range, a the sealed-junction type designed to provide
chroma system. particularly desirable consumer feature. protection against the deteriorating effects
of humidity and other surface contaminants
MAXIMUM RATINGS, Absolute·Maximum: without the need for a hermetic package
enclosure. The semiconductor junctions are
sealed by utilizing a silicon nitride passivation
DEVICE DISSIPATION:' layer. A multilayered, highly corrosion-
Up to T A = 55°C, • . • • • . • • . . • • • . • • , •••• , . • . • . , . , •• , •••• , .• , , ••••.•• 750 mW resistant, terminal-connection system of
AboveTA=550C, . . . • • . . • • . , .• , •••• , •••.••••.• ,., ••.••• derate IInearlv 7.9mW/oC unique design is employed.
AMBIENT-TEMPERATURE RANGE:
Operating . . . • . . . . • . . . . . . . . . . • • . • • . , • , •••••• , .• , -40 to +B5°C
Storage . . . . . . . . . . . . . • . . . . . • . • . . • . . • . • . • • , •• , ••.• , •••• -65 to +150oC
CIRCUIT DESCRIPTION
LEAD TEMPERATURE lOuring soldering):
At distance 1/16 ±1/32 Inch 11.59 ±0.79 mm)
· • , ••••••••..•••••. +265 0 C
The CA3170G, is a complete subcarrier re-
from case for 10 s max.
generation system with automatic phase con-
trol applied to the oscillator. An amplified
chroma signal from the CA3121E is applied
v"· 24 V to terminals No. 13 and No. 14, which are
the automatic phase control (APC) and the
automatic chroma control (ACC) inpuu.
APC and ACC detection is keyed by the hor·
izontal pulse which also inhiblu the oscilla-
tor output amplifier during the burst interval.
The ACC syslllm uses a synchronous detec-
OSCILLATOR
tor to develop a correction voltage at the
OUTPUT differential output terminal Nos. 15 & 16.
This control signal is applied to the input
terminal Nos. 1 & 16 of the CA3121E. The
APC system also uses a synchronous detec-
f.-!.-~i}-:<iD;"';;M-<"k, tor. The APC error voltage is inlllrnally
HORIZ
ICEYP\JLSE coupled to the 3.58 MHz oscillator at bal-
IL-~__________________________~__________~ :\~ ance; the phase of the signal at terminal No.
j CA3170G +-________________+~>__----... INPUT
13 is in quadrature with the oscillator.
L ____________ ~ ______ ~
To accomplish phasing requirements, an RC
AlLRESlIU,.nUlUEIARf'''OHM\
phase shift network is used between the
1Jtj~~!~ ~~::~.~S!~:?!C:,~~~R~~:"ACI' ANU VAL ".IE I chroma input and terminal Nos. 13 and 14.
lCOIIGREA1UUEtNP'ICCFAIIAOS Fig. 1 - Functional block diagram of CA3170G.
The feedback loop of the oscillator is from
terminal Nos. 7 and 8 back to No.6. The
same oscillator signal is aVailable at terminal
,. Nos. 7 and 8, but the dc output of the APC
detector controls the relative signal levels at
terminal Nos. 7 or 8. Because the output at
terminal No.8 is shifted in phase compared
to the output at lIIrminal No.7, which is ap-
plied directly to the crystal circuit, control
of the relative amplitudes at terminal Nos. 7
and 8 alters the phase in the feedback loop,
~"~B I ~ thereby changing the frequency of the
crystal oscillator. Balance adjustmenU of de
offseu are provided to establish an initial no-
-.Jr--
'---""=-""."""""'"'1£0 CHROMA GAI~tI~~~OL
• _____ ...J
I signal offset control in the ACC output, and
a no-signal, on-frequency adjustment
through the APC detector-amplifier circuit
which controls the oscillator frequency. The
oscillator output stage is differentially
Fig. 2 - Simplified functional diagram of a two-package TV chroma controlled at terminal Nos. 2 and 3 by the
system utilizing the CA3170G and CA3121E. hue control input to terminal No.1. The hue
__________________________________________________________________ 417
CA3170G
ACC APC SHUNT [Link]
INPUT INPUT [Link] FEEDBACK
AND BIAS [Link]
10 • 7
HORIZONTAL.
KEY [Link]
I~
.31
22.
Q3I
TERMINAL. 9 NO CONNECTION
AL.L. RESISTOR [Link] ARE IN OHMS
Fig. 6 - Schematic diagram of the CA3110G.
TO TERM.6
.,
~ I - -----1
CHIlO" I I
IN~ I
.7 I
I
I
I
I
0.001 I
Hf>I
TILT AO... _
I
I
I
I
I
IL ___ _
92CS-27691111
'"APC
AOJ
Fig. 8 - Static characteristics test circuit
RESISTANCE VALUES ARE IN OHMS
UNLESS OTHERWISE INDICATED, ALL CAPACITANCt
VALUES LESS THAN I ARE IN MICROFARADS,
0.1';, lOR GREATER ARE IN PICOFARADS.
92CL-l!16181t1
Fig. 7 - Outboard circuitry of a typical two-package chroma system for
__________________________________________________________________ 419
color- TV receivers utilizing the CA3121E and CA3170G.
CA3172G
CHROMA
INPUT
>--+--{)0"'--'vV~-oR-Y OUTPUT
REFERENCE
SUBCARAIER 41 >--+-{9)-",--'VV~-oG-Y OUTPUT
~~~~~~0+H-----,
>--r~~-~~-oB-Y OUTPUT
U"lHS01He~.':>f ,"IlICUHI [Link] [Link] ...n ULUfl
lfS~
THAI< I 0 AilE IN .IC~OF"""O\
lOORCRUfERUE,"PI(O, .. R.. OS
Fig. I - Functional diagram of RCA-CA31 72_
FifJ. 2 - Schematic diagram for CA3 I 72.
a-y
OUTPUT
+24V
NOTE;
ALL CAPACITORS GIVEN IN pF
UNLESS OTHERWISE NOTED.
ALL RESISTANCES IN OHMS.
Fig. 3 - Static characteristics test circuit. Fig. 4 - Dynamic characteristics test circuit.
_____________________________________________________________________ 421
CA3189E
ELECTRICAL CHARACTERISTICS, at T A = 25°C, V+ = 12 Volts
TEST CONDITIONS LIMITS
CHARAC· SYMBOL Circuit UNITS
TERISTIC or Min. Typ. Max.
Fig. No.
Static (DC) Characteristics
Quiescent Circuit
Current 111 20 31 40 mA
DC Voltages: "><:6>--+- AUDIO
OUTPUT
Terminal 1 (I F Input) VI 1.2 1.9 2.4 V
Terminal 2 (AC
Return to Input) V2 No signal input, 2,6 1.2 1.9 2.4 V
Non muted
Terminal 3 (DC
Bias to Input) V3 1.2 1.9 2.4 V
Terminal 15
(RF AGC) V 15 7.5 9.5 11 V ALL RESISTANCE VALUES ARE IN OHMS
*1: PRI, -Qo(UNlOADEo)a 75(TUNES WITH 100 pF (el) 201 OF 34e ON
Terminal 10 (DC 7132" DIA fORM
SEC. -Qo(UNLOADEO);;I75 (TUNES WITH 100 pF (e21 201 OF 34e ON
Reference) VlO 5 5.6 6 V 7132" DIA FORM
kQ(PER CENT OF CRITICAL COUPLING) iii 70 %
Dynamic Characteristics (ADJUSTED FOR COIL VOLTAGE lie 1~150 mV
ABOVE VALUES PERMIT PROPER OPERATION OF MUTE (SQUELCH) CIRCUIT
Input Limiting Volt· "E~ TYPE SLUGS,SPACING 4mm
age (-3 dB point) VI (lim) - 12 25 !1V **C=[Link] JLF FOR 50 1-'5 OEEMPHASIS (EUROPE)
: 0,Ot5,..F FOR 75,.., DEEMPHASIS (USA)
AM Rejection VIN = Fig. 2 - Test circuit for CA3189E using a double-
(Term. 6) AMR 0.1 V, 2,6 45 55 - dB tuned detector coil.
Recovered AF AM Mod. fO=10.7
Voltage (Term. 6) = 30% MHz, 325 500 650 mV
VO(AF) DC VOLTAGE SUPPLY V+"2V
AMBIENT TEMPERATURE (TA)-+25·C
~ o SEE TEST CIRCUIT SEE FIG. :5
12
Total Harmonic ~ (RECOVERED AUDIO FROM FULL
OUTPUT (LEFT CO-ORDINATE)
Distortion: * fmod' = 1Il~
~.
-10 10
Single Tuned (Term. 400 Hz, - 0.5 1 %
VIN = 6 Iii n
6) THO 0.1 V !~
C~
-20
~
TUNER AGC DC
VOLTAGE AT
TERMINAL No•• ,
(RIGHT CO-ORDINATE)
-~- -
e a
~4
g
Double Tuned ~~ -30 f - - (PINIOTr:~1 6
- 0.1 - %
2:
(Term. 6) THO Deviation 2
±75 kHz
~~-40 _ .. _--1 ~ 1~~t\l\1
Signal plus Noise to ~ 1""'!t1E..~~o' p..1E..)
Noise Ratio ~ -50
c----t~\·~
-r~~~#1 cJl ~
(Term. 6) S+ N/N 2,6 65 72 - dB -60
'9"
10 100 Ik 10~ IOO~
Deviation Mute INPUT SIGNAL -,.V
Frequency fDEV. fmod. = 0 4,6,7 - ±40 - kHz Fig. 3 - Muting action, tuner AGC, and tuning
meter output as a function of input
R F AGC Threshold V16 2,6 - 1.25 - V signal voltage.
On Channel Step VIN = fDEV. < DC POWER SUPPLY (V+)'12 V
V 12 0.1 V ±40 kHz 6 - 0 - V
AMBIENT TEMPERATURE (TA)-25·C
200 SEE TEST CIRCUIT,.,FIG. 3
fDEV. > 1~
~ 150 5~.Q. ~A
±40 kHz - 5.6 -
... THO characteristics are essentially a function of the phase characteristics of the network connected
between terminals 8, g, and 10.
-50 50 100 "0
CHANGE IN FREQUENCY (6f)-~Hz
Fig. 4 - AFC characteristics (current at Term. 7
as a function of change in frequency).
___________________________________________________________________ 423
CA3189E
...'"
,000000ATUII(
AUDIO
~
DEVIATION MUTE OETECTOR
AND AFC AMPlI.
Fig. 5 - Scho""'tic diagram of the CA31SSE
All RESISTANCE VALUES ARE IN OHMS
*L TUNES WITH 100pF (C) AT 10.7 MHz
OoCUNLOAOED)-7!5 (TOKO No. KACS K586HM OR EQUIVALENT)
*"'C~[Link]".F FOR 5O,.s DEEMPHASIS (EUROPE)
s [Link]!5".F FOR 75".1 DEEMPHASIS (USA)
Fig. 6 - Test circuit for CA3189E using a sing/e-
tuned detector coil.
___________________________________________________________________ 425
CA3221G
TV Chroma Amplifierl Features:
Demodulator • Excellent linearity in de chroma gain-controlled circuit
• Improved filtering resulting in reduced 7_2-MHz output
Provides Complete System for Processing Chroma from the color demodulators
When Used with RCA-CA3070 or CA3170 • Current limiting for short·circuit protection
"G" Suffix Type-Hermetic Gold-CHIP in • Good tolerance to B+ supply variations
Dual-I n- Li ne Plastic Package • Good temperature coefficient stability
• Gold·CHIP for increased reliability
The RCA-CA3221G is a monolithic silicon Gold-CHIP (G suffix). The transistor chips
integrated [Link] amplifier/demodu- used in the hermetic' Gold-CHIP plastic
lator with ACC, saturation control, and killer packages are of the sealed-junction type
control for use in NTSC color TV receivers_ designed to provide protection against the
It is designed to function compatibly with deteriorating effects of humidity and other
the CA3070 or CA3170 in a 2-package surface contaminants without the need for a
chroma system. The CA3221G is functionally hermetic package enclosure. The semicon-
identical to the industry standard CA3121, ductor junctions are sealed by utilizing a
but has a modified saturation control as silicon nitride passivation layer. A multi-
well as a modified color difference matrix. layered, highly corrosion-resistant, terminal-
The CA3221 G is supplied in the 16-lead connection system of unique design is
employed.
dual-in-line plastic package with a hermetic
MAXIMUM RATINGS at TA = 25°C
Supply Voltage " . .30V
Device Dissipation:
Up to T A = 55°C _ . . . . . . lW 1'1 1500
Above T A = 55°C derate linearly 10.5 mW/oC
Operating Temperature Range. . -40 to +85°C ~ 1000
Storage Temperature Range . -65 to +1500 C
lead Temperature (During Soldering) '00
At distance 1/16" ±1/32" 11.59 ±o.79 mm) from ca.e for 10. max.
100 200 soo 400 500 600 100
NTSC CHROMA INPUT SIGNALfTERM.2l-IIIV p_p 9lCS-22687
Fig. 2 - Typical A CC plot for the CA3221 G when
used with the CA3070.
Ace
INPUT
AMB'ENT "T.
I: :' ~'.;,;.' ~~.
:!~~PEC '~~~~~;~~t'\~~ ,
I~
CHROMA
, DE"OCE.
INPUT
i
I
I
I
I
I
I CA322Ki
L ___ _
TO Ace a
APe DEl.
3 ---. f:-
6.N:-
SATURATIOt-l REF. SUB CARRIER
TERMINAL. VOLTAGE-Ydc
,
tICS-501.
ON CA3070 AMPLIFIED CHROMA 92CM-30137
CONTROL INPUT
OR CA3170
Fig. 3 - Saturation control characteristic.
Fig. 1 - Functional block diagram of the CA3221G.
_____________________________________________________________________ 427
CA3221G
KILLER AOJ.
v+
CA3070
I CA~~70
L ___ --1---'0
92CM-30142
Fig. 4 - Simplified functional diagram of a two-package TV chroma
'V_tem utilizing the CA3221G and CA3010 or CA3110.
Fig. 5 - Schematic diagram of CA3221G.
_____________________________________________________________________ 429
CA3221G
TO
TERM.'
I-Y
OUTPUT
KILLER
."
92CM-3013.
NOTE:
2,2·kO LOADS ONLY FOR TEST PURPOSE, 3,5-tlALOADS RECOMMENDED FOR APPLICATIONS.
RESISTANCE VALUeS ARE IN OHMS.
CAPACtTANCE VALUES ARE IN MJCROFARADS UNLESS OTHERWISE INDtCATED.
Fig. 7 - TVpical [Link] tat c;n:u;t for the CA322'G.
_____________________________________________________________________ 431
MOS Field-Effect
Transistors
Technical Data
_ _ _ _ _ _ _ _ _ _ _ _ _ 433
3N128, 3N143
SOUfiCE AND SUBSTRATE GROUNDED
AMBIENT TEMPERATURE ITAJ·2S·C
:'I'E..[Link]~CE 'lOLlS (V6S)· ... 1
+0.5
0.'
-1.5
-2
5 10 15
-2.5
20 ,
I)RAIN·TO·SOUACE VOLTS (VDS) CJATEMTO·SOURCE VOLTS (vGsl GATE-TO-SOURCE VOLTS (VGS '
Fig. 4 .. Drain cuTten' vs. Jrain-to-source voltage Fig. S·Dra;n current vs. gate. to-source voltage (VGS) Fig. 6· Forward transconductance vs. gate 6ios voltage
!COMMON-SOURCE CIRCUIT
SOURCE AND SUBSTRATE GROUNDED
AMBIENT TEMPERATURE ITAI~25·C
FREQUENCY (fl~ ZOO MHz
DRAIN MILLIAMPERES I 10) = 5
IIi.
5 10 IS 20
DRAIN-TO-SOURCE VOLTS (Vosl
DRAIN MILLIAMPERES IIol
D.~,i .'LL"'''A'' '"D'
Fig. 8 ·/nput admittonce vs. drain current Fig. 9· Input admittance ¥s. Jrain·to"source volta,.
F;g. 7. ForwarJ transconductance vs. Jro;n current
III,. IS NEGLIGIBLE AT ntis FRECUENCY
b"
-1.0
o 5 10 15 20
DRAIN-TO-SOURCE \/oLTS (VOS'
ORAiN MILLIAMPERES 110) DRAIN [Link] lID I
Fig. JJ .. Reverse transoJmittance vs. Jra;n"to-source Fig. 12" Forward 'ransadmittance vs. drain current
FIg. 10· Reverse transaJmittance vs. Jro;n current voltage
COMMON M SOURCE: CIRCUIT
... SOURCE MD suaSYRAn GROUNDEO
~ AMalENT TEMPERATURE ITAI·25"
f ;, fREQUEMCT tn -200 MHz
... DRAIII [Link] tIo'·5
t
!ij
1~' boo
'oo
, 5 10 15
ORAIN·TO-SOURCl VOLTS tvos'
20
(VDS' DRAIN [Link] IIDI
F;g. 13-Forward fransoJm;ttance vs. drain-to-source Fig. J4·0utput admittance vs. dra;n current fig. JS·Oufput admittance vs. drain-to-source voltoge
voltage
______~-------------------------------------------------------------435
3N139
SILICON MOS TRANSISTOR N-Channel Depletion Type
e high input resistance
FEATURES
For Audio, Video, and RF AmplHier Applications in RGS 010 14 D typo
Communications, Instrumentation and Control Circuits elow input capacitance
C iss = 3 pF typo
•• Iow feed bKkl capacitance
RCA 3N139 is a silicon, insulated-gate field- Maximum Rotings, Absolute~aximum Values: erss = 0.2 pF typo
effect transistor of the N""Channel depletion type, DRAIN-TO-SOURCE VOLTAGE. VDS' • • +35 max. V • low gate leakage current
utilizing the MOS'" construction. It is a general purpose DRAIN-T()..SUBSTRATE VOLTAGE. VDB +35. -0.3 max. V
transistor especially suited for audio, video, and rf IGSS 00.1 "J. typo
SOURCE-TO-SUBSTRATE
applications, and for wide-band amplifierdesigns. The VOLTAGE. VSB' •.•••••••••••• +35. -0.3 max. V .high drain-to-source voltage: +35 max. V
insulated gate provides a very high input resistance DC GATE~[Link] VOLTAGE. Vas. ±10 max. V
(J014 D. typJ which is relatively insensitive to tempera- PEAK aATE-TO-SOURCE VOLTAGE. Vas ±14 max. V
ture aDdis independent De gate-bias conditions (positive, PEAK VOLTAGE. aATE-T0-ALL OTHER
negative, or zero bias). The 3Nl39 also has a high TERMINALS; VOS. VaD. VOB. non~
repetitive • • • • • • . • • • • • • • • • • • • ±42 max. V
transconductance, a low value of input capacitance DRAIN CURRENT. ID ••••••••••.. 50 max. rnA
(3 pF typJ, and. a very low feedback capacitance
<0.19 pF typJ. TRANSISTOR DISSIPA TION. PT: TERMINAL ARRANGEMENT
At ambient temperatures up to 25°C. . . . . 330 mW
The 3N139 is hermetically sealed in the standard above 250C .........••..•.•.•.. Derate linearly at 2.2 mW/OC
~
4-lead JEDEC TQ-72 package. AMBIENT TEMPERATURE RANGE:
1 - Drain
Storage ••••••••• 0 •• 0 -65 to + 175
0 ••••• °c 0 0
2 - Source
Operating •••• 0 ••••• 0 ..a5 to + 175
• 0 • 0°c • • • •
3 - Insulated Gate
~
LEAD TEMPERATURE (During Soldering):
4 - Bulk (Svbstrate)
At distance not closer than 1132 inch to and Case
seating surface for 10 seconds max••• 265 max. °c
• Metal·Oxlde-Semiconductor
ELECTRICAL CHARACTERISTICS, at TIi. = 25° C Unl... Otherwi.e Specified. Bulk (Substrate) Connected to Source
TEST CONDITIONS
DC DC DC
FREQUENCY DRAIN·TO· GATE·TO· DRAIN LIMITS
CHARACTERISTICS SYMBOLS SOURCE SOURCE CURRENT UNITS
VOLTAGE VOLTAGE
I V.. Va' ID
MHz V V mA Min. Typ. Max.
Draln·to-Source Cutoff Current 'DIOFF} 15 -8 - - 50 .A
Zero-Bias Drain Current* lOSS 15 a 5 15 25 mA
fA = 25°C a ±10 - - 1 nA
Gate Reverse Currant IGSS
TAo = IOOGC 0 ±to - - 100 nA
~ata-to-Source Cutoff Voltage
Small:.Signal. Short-Circuit
VGSIDFF} 15 0.05 -2 -. --6 V
Ravene-Transfer Capacitance C,ss 1 15 5 0.05 0.2 D.• pF
(Drain-to·Gate)
Input Resistance r;s 100 15 5 12 - k{l
DRAIN-TO-SOURCE VOLTS (Vos J
Input Capacitance Ciss 100 15 5 - 3 10 pF
Fig. 1 - Drain Current vs Drain Voltage
Output Resistance 'os 100 15 5 6 - kn
Output Capacitance Cess 100 15 5 - 1.4 - pF
Forward Transconductance 9h 1 kHi! 15 5 5 - mmho
7 FREQUENCY (U-lkHz
I DRAIN-TO-SOURCE VOlTS-15
6 AMBIENT TEMPERATUREITAJ·2S.C".O
.!...
§
~
5
-:yJ:
",cf
.p'V
/'j
,.
~ 4 ~~
-,
GATE-TO-SOURCE VOLlS (vGS 1
GATE-TO-SOURCE VOLTS (VGS J ORAIN MILLIAMPERES (I D J
(1 Fig. 2 - Drain Current vs Gate-to-Source Voltage Fig. 3 - 1 /( Hz forward transconductance vs drain current Fig. 4 - 1 I<Hz forward transconductance vs gate-to-source
va/rage
___________________________________________________________________ 437
3N140, 3N141
,-----,;--1 Q '3N141.
~k81 ~60 ~ L - - - - - - --- - 1 "DiSC ceramic •
MHI~: :
• Tubular ceramic.
All resistors in ohms
: 0
1
(" ~~1:~zT All capacitors in pF
II '
5.6*
INPUT Cl • C2: ~;~~~ai:~.able ail capacitor: E,F. Johnson Type 160-W2
20~.
i C3: 5i~~ 'a~i:O~t~:ee 43~J:~: e~~j~:IPe~1:tor: JFDTypeVAM-
127K
C4: ~'~:i3 ~~ ~:i~~i!~te variable ai, capacitor: Roanwell Type
I
I
I L1: ~b~'~S Sll~~~~~~~t~~a~!!; t~:C~in~~R '!O~080:2~i~e w~~r~~
I length approx. O.65~ Tapped at 1-1/2 turns from Cl endof
L__ _ windinl.
GATE No. Z-TO-SOURCE VOloTSIVGZ5J
l2: Ohmite Z-144 RF choke or equivalent.
L3: J.W. Miller Co. "4580 O.l,..,H RF choke 01 equivalent.
Note: If soD meter is used in place of sweep detector, a low pass
Flg.3 - HF YO VG1S '
filter must be provided to eliminate local oscillator voltage
from load;
FJg.2 • Conversion power gain test circuit
I...ype 3H14J.
~AIH MILLIMPEAES III)! OSCILLATOR INJECTION VOLTAGE "T GATE No.2 (VLo}-VOLTSlr",,1
Fig.4 - HF V$ 'D. Fig.S - GpS v, VG1S (F., 3HI40). Fig.6 - GpS(C) vs VLO (F., 3HI41).
IHR,.
COMMON-SOURCE CIRCUIT
=:;STO:=R~=T (~:!~z::~ INPUT~
..... BlENT TEMPERATUREIT"J-2S·C
OAAIfII-!O-SOURC~ VDt;TSITV~~~'I~ rtEw.: DRAIN-TO-SOURCE'IOLTS lVOS ):13 t
MBENT TEMPERATURE ITAI-ZS'"C
FREQUENCY m-
200 Wltl
~ Ml..LlAWER£SIXO'"'
.. • t:; GATE No.1-VOLTAGE ''tlsl IS "DJUSTEO :: GATE No.Z-TO-SOI..R:E \IOlTS 1"2S'0+4
'1,.+-+ +-r'"" FOR IO *10",,, WHEN VUs-4 V
\ GATE No.Z AT "C-GROUNO POTENTIAL
.>- "
."
o.
I
GATE No 2-TO-SOURCE
VOLTS't'lG2SI-- 1r- .
5
o ..
-2 -I 0 1 -4 -3 -Z -I 0 I Z 3 o S 10 15
GAT[ No. 1- TO-SOURCE VOLTS 1V61S1 GATE No.Z-TO-SOUACE VOLTS IVG2S1 OAAIN-TO-SOURCE VOLTS IVOsl
Fig.7 -10 YO VG1s • Fig.8 - '0 vs VG1S- Fig.9 - Yi5 vs Vas·
COMMON-SOURCE CIRCUIT CQWOH-SO/JRCE CIRCUIT
AMBIENT TEMPERATURE ITA)-2S-C AMBIENT TEMPERATURE ITAI 'ZS"C
FREQUENCY It I >zoo MHI ~ FREQUENCY m > 200 tIIHI
DRAIN MILLIAMPERES 1101> 8
GIoTE No.Z-TO-SOUftCE VOLTS (\1625'>4 i DRAIN MILLIAMPERES IIO'-8
~TE NO.2-TO~_SOURCE VO;!!I\lGzsl>"
~ Or,' lit ~ ~f
Of,
i
ffi
~
~
~ .;". "
7:1"t" tt.
-u
',. ~
-'0
o • ~
-,
0 • '0
2345&78'IOIIIZI1415 ORAIN-TO-SOURCE VOLTS I\lOSI ORAIN-TO-SOURCE VOLTS IVosl
DRA"'-TO-SOURCE VOLTS 1VosI
[Link]. Vas· Fig.1I - YI. v, VOS'
Y05 V5 Fig.J2 - Y'5 Vas· VS
___________________________________________________________________ 439
3N142
Silicon MOS Transistor [Link]'Doplo.... T...
Perlormance Features
• Large dynamic range
For Industrial and Military Applications to 175 MHz • Enhanced [Link] capability for low
cross-modula,jon
[Link] Rotings, Ahsoll,lt.·Mox;mum ~'CJlues at TA '" 25° C • Dual-polarity gate permits positi". and negati"e
The-3N142 is a silicon. insulated-gate field-cffect
swing without degradation of input impedance
transistor of the N--channel depletion type utilizing the • DRAIN·TO-SOURCE
Mo;- construction. • Reduced spurious responses in FM recei"ers
VOLTAGE. V.,s ·20
• Permits use of "acuum-tube biasing techniques
The-3N142 is intended primarily for use as thE' rf .DRAIN·TO-GATE • Excellent thermal stability for critical oscillator
amplifier in FM receivers and general amplifier applica- VOLTAGE, V()f; \- designs
tions at frequencies up to 175 MHz. • GATE-TO-SOURCE
VOLTAGE, VI;S: Deyice Features
The wide dynamic range of the 3N142 reduces ('r088-
modulation effects in AM receivers and .minimizes the Continuous ..... . •.•.• +1 to-8 \' • High input resistance - 1000 megohms
P('lIk II(' ••••. • 15 \'
generation of spurious responses in FM receivers. • Low feedback capacitance - 0.35 pF max.
.DRAIN CURRENT, In ........ 50 mA • Low noise figure - 2.5 dB typo
• High useful power gain -
• ~tal-Oxide..semiconductO!' -TRANSISTOR DISSIPATION, PT:
At ambient \ up to 25'-C , •.... :J:lO mW [Link] - 16 dB min. at 100 MHz
temperatures I above 25 C " " , . Derate lit 2.2mW/"C
Q
• Hermetically sealed TO - 72 metal package
Applicafions
.AMBIENT TEMPERATURE
• RF amplifier, Mixer, and Oscillator in: RANGE: TERMINAL DIAGRAM
~
CB and Mobil. Communication Receivers Storage .. , . " . -65 to +175 'C
Aircraft and Marine Receiver. Operating -6500+175 'C
CATV and MATV Equipmen. .. LEAD TEMPERATURE
~
• Industrial Control Circuits (During Soldering):
• Variable Attenuatars At distances;:: 1/32" from seating
• Current Limiters Burface for 10 seoonds max ... " 265 ·c
• Instrumentation Equip ...... • In tlccordtmce with JEDEC [Link] Dato Format J&-9
• High-Impedance Timing Circuits RDFl1-8 LEAD 1- DRAIN
LEAD 2 - SOURCE
LEAD 3 - INSULATED GATE
ELECTRICAL CHARACTERISTICS, (A. TA - 25° C) LEAD4- BULK (SUBSTRA1E) AND CASE
Measured uilh Substrate ConnC'ctC'tJ 10 Sourcl' LJn/('ss Otht'ru'isf' t;pC'C'i{;C'(i
LIMITS
CHARACTERISTICS SYMBOLS CON OITION S UNITS
Mm. T", Max.
VOS • O. VGS • -8 V, TA - 15' C 0,0001 I nA
VOS -0, VGS··8V, TA-125'C 200 nA
Gate Leakage Cunent IGSS ,vOS' 0, VGS - d, TA - 150 C 0,0001 1 nA
VOS - 0, VGS - d, TA- 1150 C 200 nA
Zem·Blas Drain Current·· lOSS VOS - 15 V, VGS - 0 5 15 25 rnA
Drain'lo-Source Cutoff Currenl 11J{01l\ VOS 10 V, VGS '-8V 50 I'-A
Gate-lo-50uree Culoll Voltage VGS(olO VOS 15 V, 10 50 .. A -0_5 -3 -8 V
Forward Transconductance gls VOS - 15 V, 10 5 rnA, I I kHz 5000 7500 11,000 [Link]
Drain·to-Source Channel ReSistance rO~'nl VOS - 0, VGS . 0, I I kHz 200 [1
Small·Signal Shoft·Circult
. Reverse Transfer Capacttillfcet CISS VOS' 15 V, 10·5 rnA, I· 0,110 I MHz 0.10 0,22 0.35 pF
Small,Slgnal Short·Cnculllnpul Capacitance CISS VOS - 15 [Link] 5 rnA, I - 0.110 I MHz 5,5 7 pF
Input Adrnillane, Vis Common Soulce Configuration - 1 0.155+l3_451 - mmho
I· 100 MHz
Forward Transfer Admittance Vis VOS • 15V -I 7.5-l0.9 I- mmho
Ottput Ad rnillanee V's 10.5 rnA -I 0_21+l0_9 I- mmho
Maximum Available Power Gain ~
Maximum Usable Power Gain MUG dB
(Fixed Neutralization) 17
VOS - 15 V, 10 - 5 rnA, I -100 MHz
17m~ :'~~Ii~:l:':) G", 16 dB
Noise Figure·· NF VOS' 15 V, 10·5 rnA, I -100 MHz 2_5 4 dB
• In accordance with JEDEC Registration Data Format JS-9 RDF-llB l Three·Terminal rvteasurement: Source Returned to Guard Terminal
··See Fie. 1
T1 N1 =6Turns.20TinnadCopperWire;W' 1.0. %" long
00 = 2IE, N1JN2" 4.85
T2 Nl + N4 = 6% Turnst'20 Tinned Copper Wire '4'. 1.0. ~ '6long
,
L ____________ ..J ________ ~e!---..J C,,,
0 0 " ,90N,JN2" 1.9 Nl/N3'" 12.3 N,/N4=8
10 pF Variable Air Capacitor (Hammarlund Mac-10 or Equivalent!
C2" 5 pF Variable Air Capacitor IHammarlund Mac-5 or Equivalent!
g3: ~~~~~F Piston-Tvpe Variable Air Capacitor (Erie S35C or Equivalent)
+l6V
,tcS-170$4
Fig. , - Tut Set Up for '00 MHz Insertion POWfN Gain and
Noise Figure
For characteristics curves, refer to types 3N128 and 3N143 _
______________________________________________________________________ 441
3N153
FEATURES
SILICON INSULATED GATE FIELD·EFFECT TRANSISTOR
N-Channel [Link]~n~~TVIIeI
• excellent thermal stabilit,
• virtually zero inherent offset voltage
RCA 3N153 is a silicon, insulated-gate field-effoct • low lealeage current: 50 pA max.
Maximum Ratings, A~"olut.-lttaKimum Values:
transistor of the N-channel depletion type, utilizing the
MOS" construction. It is intended primarily for critical (Substrate connected 10 source unless otherwise specified) • low "on" resistance - 'DS(on) = 200Q typo
chopper and multiplex applications up to 60 MHz. DRAIN-TO-SOURCE VOLTAGE, VDS ... +20 max. V • high "off' r•• [Link]. - RD5(off) = 10 10 II typo
DRAIN-TO-SUBSTRATE VOLTAGE, VDB. +20, -0.3 max. V
The insulated gate provides a very high value of • low [Link] capacitance-ern = 0.34 pF typo
SOURCE-TO-SUBSTRATE
input resistance (10 10 ohms typ) which is relatively in- VOLTAGE, VSB' . • . . . . . . . . . . . . . +20, -0.3 max. V e low input capacitance-Cin = 6 pF typo
sensitive to temperature and is independent of gate-bias DC GATE-TO-SOURCE VOLTAGE, VGS. is, -8 V
conditions (positive, negative, or zero bias>. The 3N153 PEAK GATE-TO-SOURCE
also features extremely low feedback capacitance VOLTAGE, vGS........... ±14 max. V
<0.34 pF typ) and virtually zero inherent offset voltage. DRAIN CURRENT. 10
(Pulse duration 20 rna, duty factor APPLICA TlONS
This transistor features a Terminal Arrangement in £0.10) ••• • • • • . • • . • • . • • . • . 50 mA
which the gate and source connections are interchanged TRANSISTOR DISSIPATION. PT: • Choppers
to provide maximum isolation between the output (drain) Air:b~e5ttote~~~t~.e~ . . .. . . . . 400 max. mW e Multiplexers
and the input (gate) tenninals. Although this new basing above 25°C •... __ . . . . . derate linearly at. 2.67 mW/oC • Servo Amplifiers
configuration does not appreciably change the measured AMBIENT TEMPERATURE RANGE:
device feedback capacitance, it "Permits the use of • Computer Operational Amplifiers
Storage . . . . • . . . . . . . . . • . . . . . . _ -65 to +175 °c
external inter-tenninal shields to reduce the feedback Operating .•.. , . • . • . . . . . . . . . -65 to +175 °c • Sampling Circuits
due to external capacitances, particularly on printed LEAD TEMPERATURE • Electrometer Amplifiers
circuit boards. This feature makes it possible to mini- (During soldering):
mize feedthrough capacitance. At distance ~ 1/32" to seatmg
surface for 10 seconds max. . , _ . . . .. 265 max. OC
The 3N153 is hermetically sealed in the JEDEC
T0-72 package and features a gate metallization that TERMINAL DIAGRAM
covers the entire source-to-drain channel.
~
• Metal-Oxide-Semiconductor
ELl!CTRICAL CHARACTERISTICS, at TA = 25°C, Un Ie .. Otherwls. SfMclfled. Substrate Connect" to Source.
~
LIMITS
SYMBOLS TEST CONOITIONS Type 3NIS3 UNITS
CHARACTERISTICS
Min. Typ. Max. 1 - Drain
2 - Source
VGS =.S,-iV; Vas =OV; TA = 1SoC 0.1 SO pA
Gate·Leakage Current IGSS 3 - InSOlated Gate
VGS =.S,-8V; Vas =OV; TA = 11SoC I nA 4 - Bulk (Substrate)
and Case
Static Drain-la-Source VGS = OV, VOS = OV 100 300 fl
'OS(on)
"ON" Resistance
Drain-la-Source ROS(oli) VGS = ·8V, Vas = • IV 10 9 10 10 fl
HOFF" Resistance
Drain-to-Source VGS=-8V,VOS=.IV,TA = 1SoC 0.1 I nA
IO(oft)
Culolf Current VGS=-8V,VOS=dV,TA =11SoC 0.1 I ~A
Small·Signal, Short·Circuit, Crss
VGS =·8V:VOS =OV, f = I MHz 0.34 O.S pF
Reverse Transfer CapaCitance Vas =ISV,lo =S rnA, f = I MHz 0.25 0.38 pF
Small~Signal, Short·Circuit, Ciss VGS = -8V, Vas = OV, I = I MHz S 8 pF
Input Capacitance
Small-Signal, Drain-to-Source Vas =OV, VGS =·8V, 1=1 MHz 3 pF
Cds
CapaCitance
Zero-Gale-Bias VGS = OV, Vas =. lSV 10,000 [Link]
gls
Forward Transconductance
~"''''-TO-I..u.C£ VClLTS IVoSI
Oftset Voltage Vo VGS = .S,-8V; Vas = ov O· V teCB-I.'.!!
Fig.l - Drain current VI. Jra/n-to-source yo/tage•
• In measurements of Offset Voltage, thermocouple effects and contact potentials in the measurement setup may cause erronaoU$ readings of
1 microvolt Of more. These errors may be minimized by the use of soldel having a low thermal e,m.f" such as Leeds & NorthrUp No.107-1.0.1,
01 equivalent,
SUBSTRATE CONNECTEO TO SOURCE
DRAIN-TO-SOURCE VOLTS' 10$, ...
AMBIENT TEMPERATURE ITA'·2S·C
ORAIN-TO-SOURCE MILLIVOLTS (VDS' GATE-TO-SOURCE vOLTS (vO$)
Fig.2 - Low-/eyel drain current Fig.3 • Drain-toosouree static resistance
YB. droin-to-source yo/tage.
Ys, gate-to-source yo/tage.
-------------------------------------------------------------------~
3N159
SILICON DUAL INSULATED·GATE FIELD·EFFECT TRANSISTOR N-Cllannel Depletion Type
Fir M_ and Industrial Law·Naisl RF·ARI!Mr PERFORMANCE FEATURES
Applications Up to • MHz • wid. dynamic raftl. pe,mlts la".... [Link] handling
before o .... ,[Link]
The 3N159" is an n-channel silicon, depletion type, • dual-got. permits simplified age circuitry
dual insulated~gate. fie1d~effect transistor utilizing the
• Virtually no age power required
MOS"'. construction. It has exceptional characteristics
for rf - amplifier applications at frequencies up to MaxiMuM Rolin,., [Link] Values: • .reatly reduce. spurious .... pon ••• in FM receiver.
300 MHz. This transistor features B series arrangement ., TA ~ 2S"C • permits use .f vacuum-tube biasing techniques
of two separate chaMels, each channel having an DRAIN-TO-SOURCE VOLTAGE, VDS ..•.•••• 0 to +20 V
• .xcellent thermal stability
independent control gale. GATE-No.I-TO-SOURCE VOLTAGE, VGIS:
Continuous (de) •.••.•.•••..•••.•••• -8 to +1 V • superior [Link] [Link] and greater
Type 3N159 has an exceptionally low..noisefigure, which
Peat ae •.•••••••••.•..•.•••••• -8 to +20 V dynamiC ran,. than bipolar or ..In. I...... field ••Hect
makes this type particularly suitable for critical vhf
GATE No.2-TO-SOURCE VOLTAGE, VG2S : [Link]
applications. When used in a common-sowce CODa
figuration in which gale No.2 is ac grounded, this device Continuous (de) . • • • • • . • • • • • •• -8 to 40% of V DS V
reduces oscillator feedthrough to the anlenna thereby Peat ac •••••.•••.•••••••..•••.. -8 to +20 V DEYICE FEATURES
minimizing oscillator radiation. DRAIN-TO-GATE VOLTAGE:
VDGI 01' V DG2 ••..••••.• , ••••..••••••• +20 V • low to" leak••e cu,rents - -
The 3Nl59 is hermetically sealed in the metal JEDEC 'GI55 & 'G255 = I .A onax.
DRAIN CURRENT. '"
TO-72 package. PUlsed: Pulse dUration ~ 20 ma, • high forward transconductance - -
** Metal-oxide-Semiconductor.
duty factor ~ 0.15 •••.••.••••••••.•.••• SO rnA
TRANSISTOR DISSIPATION, P T :
'f.= 7000 ... mho min.
At ambient } up to 25°C ••• . • • • • • • • • • • • • 400 mW • high unneutraliz" Rf pow.r lain - -
APPLICATIOHS temperature. above 25°C •••.•...•• derate linearly at Gp• = 16.8 min. at 200 MHz
2.67 mW/oC
• RF amplifier in military and industrial communications • low .hf nai •• figure - -
AMBIENT TEMPERATURE RANGE:
equipment NF = 3.S dB max. a' 200 MHo
Storage and Operatinl .•.•••••••.••• -65 to +175 °c
• alrc,.ft, marine and .,.hicular receivers LEAD TEMPERATURE (lhuiQlaoldel'iftc):
At diatanees > 1/32 inch from seating TERMINAL DIAGRAM
• CATV a.d MATY .qui"",••• sur(aee (01' lOaeconda max. • • • • • • • • • • • • • •• 26S °c
~
• telemetry and multiplex [Link]
TA = ~C unl .....h....i ••• [Link]
~
ELECTRICAL CHARACTERISTICS, 01
LIMITS
CHARACTERISTICS SYMBOLS TEST CONDITIONS 3NIS9 UNITS LEAD 1 - DRAIN
Min. Typ. Max. LEAD 2 - GATE No.2
LEAD 3 - GATE No.1
Gate·No.l·to-Source Cutoff Vonage VOS· +16V, '0 • 200 ~A ·2 ·4 V
VGIS(offj VG2S • +4V
LEAD 4 - SOURCE, SUBSTRATE AND CASE
Gate·No.2·to·Source Culoff Vonage VG2S(011) VOS c +16V, 10 • 200 "" ·2 ·4 V
VGlS • 0
VGIS • ·20V, VG2~ • 0 I nA
Vn~ • 0, T • 25 C
Gate·No.I·Leakage Current IGISS VGIS • +IV, VG2~ ·0 I nA
VOS • 0, TA • 25 C
VGIS • ·20V, VG2S ·0 0.2 ~A
VOS ·0, TA ·moc I
I
VG2S • ·20V, VGI~ • 0 I nA I
~---T-l--- 'f------ J
VOS • 0, TA • 25 C
Gate·No.2·Leakage Currenl VG2 s· +1, VOS ·0 I nA
'G2SS VGIS • 0, TA • 25 0 c
VG2S • ·20V, VGlS • 0 0.2 ~A
VOS ·0, TA ·moc
VOO - +I4V, VGlS - 0
K O+---~"""I:~I
Zero·Bias Drain Current lOSS' 5 18 30 mA VAGC,±
VG2S • +4V
Forward Transconductance VOO • +14V, 10 • 10 mA 10,000 18,000 ",mho • Tubularceramic
g,s 7000 .. Di$tceramic:
(Gate·Mo.l·to·Orain) VG2S' +4V. f • I kHz
II Ferrite bead (1/2 used); Indiana General No. H 1142C{A-141) or
Cutoff Forward Transcooductance VOO· +14V, VGIS • -[Link] 100 ",mho FU5H-Horequivalent.
(Gate·No.l·lo·Orain) gfs(off) VG2S • ·2V, f • I kHz t VHF plUII in so:kel J,HrOll C012·[Link] COnt49 (pari No.797H)
Small·Signal, Short-Circuit or equivalent.
VOS· +13V, 10 • 10 mA 3 5.5 7 pF
Input Capacitance' Ciss VG2S • +4V, I • I MHz Ct. C2: 1.5·5pFvariable air capacitor: E. F. Johnson Type 160·102
Small-Signal, Short·Circuit. Reverse Transfer VOS· +[Link] ·10 mA OI'equivalent.
Crss 0.01 0.02 0.03 pF Cr 1-10 pF piston-type variable air capacitor: JFD Type
Capacitance (Orain·lo·Gate NO.1)' VG2S· +4V. f • I MHz
VAM·OlO. Johanson Type 4335, or eqUIvalent.
Small·Signa I; Short-Circuit VOS • +llV, 10 • 10 mA 2.2 pF Cf 0.3-3 pF piston·type variable air capacitor: Roanwelt Type
Cos s
Qutput Capacitance VG2S. +4V, f • I MHz MH·13 01' equivalent.
Maximum Usable Power Gain MUG VOO • +ISV. RS • 270n 16 18 22 dB Ll: 5 turns silver'plated 0.02" thick, 0.07,,·0.08" wide copper
(See Fig.! for Measuremert Circuil) RG • son, f· 200 MHz ribbon. Internal diameter of wiooing = 0.25T~ wioomg
Measured Noise Figure VOO • +15V, RS • 270n length approx. 0.65". Tapped at 1-1 2 turns Irom Cl end
NF 2.5 3.5 dB of winding.
(See Fig.! lor Measurement Circuil) 1·200 MHz, Rc • son
Lr Same as Ll except winding length approx. OJ"; no lap.
* Pulse Test: pulse duration < 20 ms, duty factor < 0.15 •
... Capacitance [Link] Gate N;'l and all other termj;;-als. Fig.l - 200-MHz power "gain and noise-'igure _s'
'0'
• Three-Terminal Measurement with Gate No.2 and Source Returned to Guard Tenrlnal. circuit 'fP. lH159.
For characteristics curves refer to types 3N140, 3N141.
_____________________________________________________________________ 445
3N187
ELECTRICAL CHARACTERISTICS, 01 TA = 250 C unl ... olh ••wise spocili.d COMMON SOURCE CIRCUIT
AMBIENT TEMPERATURE ITAj'2S"C
LIMITS ~ 1.2 12 g
.
FREQUENCY U1.1U)() MHI
CHARACTERISTICS SVMBOL TEST CONDITIONS UNITS DRAIN MILLIAMPERES 110" 10
~
Min. Typ, Max.
3 GATE No 2-TO-SQURCE VOlTS 1V025,0+4
~
VOS . . IS V, 10 = 50 ~A I I
• Gat. No. 1·I.. Soorce Culoff Vol tag. VGIS(off) -0.5 -2 -4 V
VG2S =.4 V ~I Gis 10 '!
~
VOS = .15 V, 10 = 50 ~A -4 V .- ~
.i
• Gal. No. 2·I.. Source Cutoff Vollag. VG2l(oll) -0.5 -2
VGlS = 0 ~
" Gate No. I-Terminal Forward Current IGISSF
VGIS =.1 V TA =250 C - - 50 nA
VG2S = VOS =0 TA = 100 C - - S ~A
• Gate No. I-Terminal Reverse Current
VGlS =·6 V T = 2So C - - 50 nA
IGISSR
VG2S = VOS=O TA-IOQoC - -. S ~A
'0 S 10 15
" Gate NO.2-Terminal Forward Current VG2S = .6 V TA =2So C - - 50 nA ORAIN-TO-SOURCE: VOLTS (VDS'
IG2SSF
VGlS = VOs=O TA" 100" C - - S ~A.
" Gate No. 2-Terminal Reverse Current IG2SSR
. VG2S =-6 V TA = 250 C - - 50 nA Fig. 8. ris VI. VDS
VGlS =VOs=O TA-IOWC - - 5 ~A
VOS = +IS V
" Zero-Bias Drain Current lOS VG2S = .4 V 5 IS 30 rnA
VGIS =0
Forward Transconductance VOS = +IS V, 10 - 10 mA
(Gale No. 1·I.. Drain) lis 7000 12,000 18,000 [Link]
VG2S = +4 V, I = 1kHz
• Small·Signal, ShOfI-CircuitinpulCapaeilaneet Ciss 4.0 6.0 8.5 pF
• Small·Signal, Shorl·Circuil, VOS" +IS V,IO = 10mA
Reverse Transfer Capacitance C'SS VG2S = +4 V, I - I MHz 0.005 0.02 0.03 pF
(Orain-I.. Gate No. 1).
• Small·Signal, ShOft·CircuilOulpulCapaei lane Coss - 2.0 - pF
Power Gain (see Fig. 1) GpS 16 18 22 dB
lMaximum Available Power Gain MAG - 20 - dB
Maximum Usable Power Gain (unneutralized) MUG - 20- - dB
Noise Figure (see Fig. 1) NF - 3.5 4.5 dB
DRAIN-TO-SOURCE VOLTS 1YOS)
" Magnitude of Forward Transadmittance IVlsl VOS = +IS V, 10 = 10 mA - 12,00 - J.'mho
VG2S = +4 V, I =200 MHz Fig. 9. Y•• ••• VOS
• Pltase Angte of Forward TIOnsadmittance (J - -35 - Degrees
Magnitude 01 Reverse Transadmittance IVrsl - 25 - [Link]
Angle 01 Reverse Transadmillanee Its - -25 - Degrees
" Input Resistance 'iss - 1.0 - kfl
" Output Resistance 'oss - 2.8 - kfl
Gale-I.. Source
• Forward Breakdown Voltage:
Gat. No. I VBR1GISSF IGISSF -IG2SSF = 100 ~A 6.5 10 - V
Gal. No.2 v(BR)G2SSF
Gale-I..Source
• Reverse Brealldown Voltage:
Gale No. I IGISSR = IG2SSR '·100 ~A -6.5 -10 - V
'itBRl!>JSSR
Gale No.2 v(BR)G2SSR
.Limlted only by practical desran consuieratlons. OPERATING CONSIDERATIONS
t Capacitance between Gate No.1 and all other lerminals The flexible leads of the 3N 187 are usually soldered to the
• Three·terminal measurement with Gate No.2 and circuit elements. As in the case of any high·frequency IS 10 IS
Source rerurned to Ifound terminal. DRAIN-TO-SOURCE VOLTS IVas)
• In accordance with JEDEC Reelstration Data Format J5-9 RDF"J9A semiconductor device, the tips of soldering irons MUST
be grounded_ Fig. 10- YI• • s. VOS
AM_NT TEMPfRATlItE CTA"25-C -SOURCE CIRCUIT,GATE No.1 INPUT
DRAIN-TO-SOURCE VOLT. (Vos'·" AMBIENT TEMPERATURE (TA"2e-C
"'.
I, DRAIN-TO-SOURCE VOLTS (Vos'eIS
~ GATE No.1-VOLTAGE (vaIS' IS ADJUSTED
FOR 10 -10.. A WHEN Ye2s - 4 V
GATE No.2 AT ~-QROUNO POTENTIAL
~ d'
...
;
I
~
I.
i37.5I.
• i
I• E No.2-TO-SOURCE I ...•
VOLTS ('16 1--1
0
-2 -I 0 I
GATE No. 1- TO-SOURCE 'IIOLTS IYOIS'
-.
0
-3-2-10123
GATE No.2-TO-SOURCE VOLTS (VG2S'
Fig. 6- '0 .s, VGIS Fig. 7-'0 .s. VG2S Fig. 11- Y.. ••• VOS
.........................................................................................................................................................................._447
3N187
-I -I +1
GATE NO. 2-TO-SOURCE VOLTS IVSUI lATE NO.I-TO-IOUICI [Link] I Vels)
FI,. 24· g,. an" 'D ••. VG2S Fi,. 25•• ff.... VGIS
Fig. 26· "'2 ••. VG2S
___________________________________________________________________ 449
3N200
ELECTRICAL CHARACTERISTICS LIMITS
TA " 25°C
III SYMBOLS TEST CONDITIONS UNITS
[Link] otfJerwis. specifieJ Min. Typ. Max. AMBIEHTTEMPERATUAE(T,t,)·Z5OC
MAJ(. POWER GAIN (Gpl). (IdS
O.50~
VOS· -\5 V, 10' SOI"A
Gate No. I-to-Source Cutoff Voltage VGIII;ofn
VG2S =. _4 V
-0.1 -I -3 V ",,, 0.25 ~
~
VOS = -IS V, 10 =SOI"A o ~
Gate No. No-Source Cutoff Voltage VG211;01l) -0.1 -I -3 V
VGIS = 0 ~
-ooug
Gate No_ I-Terminal Forward Currenl VGlS=-IV TA =25°C - - 50 nA
IGISSF
VG2S=VOS'0 TA = 100°C - - 5 /LA -0.5115
Gate No. \-Terminal Reverse Current VGlS=-6V TA = 25°C - - 50 nA
IGISSR VG2S = VOS = 0 TA = loooe - - 5 /LA AUTOMATIC GAIH COtfTROL VOLTS (VAGC)
Gate No.2-Terminal Forward Current IG2SSF
VG2S = -6V TA=25 0 C - - 50 nA Fig. 5- VAGC YS. VG1S
VGIS =VOS =0 TA= 100°C - - 5 /LA
Gate NO.2-Terminal Reverse Current VG2S=-6V TA = 25°C - - 50 nA
IG2SSR VGIS = VOS =0 TA = 100°C - - 5 /LA
AllIIII!MTTE.'!IlATUfI!IT"I- 25"'C
FlEQUEMCYlfI- 4DOIIHa
Zera-Bias Drain Current VOS = +15V, VGIS =0 5.0 rnA
DRAIN IIIILUAMPaES 'Iol • 10
lOS 0.5 12 GATEMO. Z·[Link] YOLT5("G151-.
VG2S = +4V g
Forward Transconductance
gfs f = 1kHz 10,000 15,000 20.001 /L mho
! ~
(Gate No. I-to-Orain)
Small-Signal~ Short-Circuit Input
~
J. ie
Ciss 4.0 6.0 8.5 pF
L .,
Capacitance
Small-Signal, Short-Circuit,
Reverse Transfer Ca~acitance
(Orain-to-Gate-No. I)'
Crss
VOS = +15V
10=IOmA
VG2S = +4V
f = I MHz 0.005 0.02 0.03 pF ~,
i
• I
15
" . ~
~
~
Small-Signal, Short-Circuit Output Coss - 2.0 - pF
Capacitance
6 • 111 12
Power Gain (see Fig. I) GpS 10 12.5 - dB DRAIM·[Link](Vosl
Noise Figure (see Fig. I) NF f =400 MHz - 3.9 6.0 dB
·· Bandwidth
Gate-ta-Source Forward
Breakdown Voltage
BW
IG1SSF =
28 - 38 MHz
Gate No. I V(BR)GISSF
IG2SSF = VG2S =VOS' 0 6.5 - 13 V
Gate No.2 V(BR)G2SSF lOO/LA VGlS = VOS = 0
· Gate-ta-Source Reverse
Breakdown Voltage Gate No. I V(BR)GISSR
fG1SSR =
IG2SSR' VG2S=VOS=0
-6.5 - - 13 V
Gate No.2 lOO/LA
V(BR)G2SSR VG1S = VOS' 0
-In accordance witn JEDEC ,elisl'Mion data fOfm.t t Capacitance between Gale No.1 and all other terminals.
(Js-9RDF.19A.j .Th,""termuI.1 measurement with Gate No.2 and
Sa.. ce I.t,"ned to lUard term",.I.
10 12
[Link]
Fig. 7 - YOS V5. VDS
AIIIIIEHTTEfIIPERATURE{TA"25"C AMBIENTTE,IIPERATURE(TA}=25OC
ClATEMO.2·TO-SOORCEvoLn,vC2SJ'4 rREIlUENCY(I)·400MH.
DRAINMILLIA/IIPERE5UO)·IO
GATEtta. I·TO·SOURCE YQLTS(VGIs!: 0.1 GATE NO. 2-TO·SOURCE VDLTS (VoZs) -.
,.'
AMBIEHTTEMPERATURE{T ... ).2SO(
DR ...... ·[Link](VOS)·IS
-G.2
.
_2
G"TEIOO. 2·TO·WURCE YOLTS(VC2S'
6 8 10
DRA'H-TO-SOLRCEvOLn(vOY
12
[Link]·SOURCEVOLTSIVOS)
F;g. 3 - '0 YS. VG2S Fig. 4 - '0 YS. VOS Fig. 8· Y/s vs. VDS
_____________________________________________________________________ ~1
3N204, 3N205, 3N206
Features:
Silicon Dual-Insulated-Gate • Low Crss - 0.03 pF max.
Field-Effect Transistors • High IVfsl- 14 mmho typo for 3N204 and 3N205
• Integrated gate·protection diodes
With Integrated Gate·Protection Circuits MAXIMUM RATINGS,
For VH F TV Applications Absolute Maximum Values at TA = 2!PC
3N204 - RF Amplifier
* DRAIN·TO·GATE No.1 VOLTAGE 30 V
* DRAIN·TO·GATE No.2 VOLTAGE. . 30 V
3N205 - Mixer * DRAIN·TO·SOURCE VOLTAGE . 25 V
• GATE NO.l·TERMINAL FORWARD CURRENT. 10
3N206 - TV I F Amplifier rnA
• GATE NO.2·TERMINAL FORWARD CURRENT· 10 rnA
The RCA·3N204, 3N205, and 3N206 are • GATE NO.l·TERMINAL REVERSE CURRENT -10 rnA
n·channel silicon, depletion type, dual·insu· * GATE NO.2·TERMINAL REVERSE CURRENT -10 rnA
lated gate, field·effect transistors intended * CONTINUOUS DRAIN CURRENT 50 rnA
for vhf TV applications. Integrated back· * DEVICE DISSIPATION:
Up to T A = 25°C • 360 rnW
to· back diodes protect the gates from ex·
Above T A = 25°C derate linearly 2.4 rnWJDC
cessive input voltages. Up to TC = 25°C 1.2 W
The 3N204 is intended for use in vhf rf Above T C == 25°C derate linearly . 8 mWf'C
amplifiers and delivers linear, low·noise ampli· * AMBIENT TEMPERATURE RANGE:
Operating . . -65 to +175 °c
fication. I ts extremely low feedback capaci·
Storage. . . • . .. ... -65 to +200 °c
tance allows high·gain stable operation with·
out neutralization. The 3N205 is specified for
* LEAD TEMPERATURE (DURING SOLDERING):
At distance 1/16 ± 1/32 inch 11.59 ±0.79 rnrn)
low noise vhf mixer applications. The 3N206 from case for 10 seconds max. . +300 °c
is intended for use in tuned high·frequency
... Forward gate-terminal current is the current into a gate terminal with a forward-gate-to-source voltage applied.
amplifiers such as TV if strips. This voltage is of such polarity that an increase in its magnitude causes the channel resistance to decrease.
• In accordance with JEDEC registration data format (JS-9 RDF-19B)
OPERATING CHARACTERISTICS at TA = 25 0 C
LIMITS
CHARACTERISTIC TEST CONDITIONS UNITS
Min. Typ. Max.
3N204
• Common·Source Spot Noise
Figure, NF - - 3.5 dB
* Small·Signal Common·Source VDD=18 V, VGG=7 V,
Insertion Power Gain, G ps 20 - 28 dB
f = 200 MHz, See Fig.13
* Bandwidth, BW 7 - 12 MHz
* Gain·Control Gate·Supply VOO=18 V, l'>G ps =-30dB,1
Voltage, VGG(GC) f=200 MHz, See Fig. 13 0 - -2 V
* Common·Source Spot Noise
VO=15 V, VG2S = 4 V,
Figure, NF - - 5 dB DRAIN-TO-SOURCE VOlTS (VOS)
f = 450 MHz,lO = 10 rnA,
* Small,Signal Common Source
See Figs. 15 and 16 Fi9.1 - Drain current vs. drain-to-source volts
Insertion Power Gain, G ps 14 - - dB
(pulse-tested with pulse duration ==
3N205 300 IJ.S, duty cycle <;;'2%).
* Small-Signal Conversion
VOO=18 V, fLQ=245 MHz,3
Power Gain, G ps (conv) 17 - 28 dB
fR F=200 MHz, See Fig.17
Bandwidth, BW 4 - 7 MHz
3N206
* Common·Source Spot Noise
Figure, NF - - 4 dB
• Small·Signal Common·Source VOO=24 V, VGG=6 V,
Insertion Power Gain, G ps f=45 MHz, See Fig. 14 25 - 35 dB
Bandwidth, BW 3 - 6 MHz
*
* Gain·Control Gate-Supply VOO=24 V, l'>G ps =-3OdB,2
Voltage, VGG(GC) f=45 MHz, See Fig. 14 -1.6 - 0.6 V
GATE No·' -TO-SOURCE VOLTS (VGIS)
*In accordance with JEDEC registration data format (JS-9 RDF-19B)' 92CS-27948
1. 6G ps is defined as the change in G ps from the value at V GG "" 7V. Fig.2 - Drain current vs. gate-No.l-to-source volts
2. OOps is defined as the change in G ps from the value at VGG = 6V. (pulse-tested with pulse duration == 300 IJ$,
3. Amplitude at input from local oscillator is 3 V RMS.
duty cycle <;;, 2%).
________________________________________________________________ ~3
3N204, 3N205, 3N206
'0
· "
FREQUENCY ItI-MHz
GATE No,2-l0-SOURCE VOLTS IVG2SI
92CS-279:i4
Fig.9 - Ciss .s. VG2S
Fig. 7 - Yos vs. f Fig.8 - Y OS .s. V G2S
VGG
...,
I
I
I
r---'lN'v-~~~-=f-<P--
~....:>.r--l--"?""--"""""~·U
\ 'f
TO 50 Jl
LOAD
FROM 5On~OI,..F
SOURCE 'f II~--<i""' ......r.;"'"'--<t-+-:+J I
I
I 27 I
GATE No.2-TO-SOURCE VOLTS IVG2SI : PFl I
I
Fig.10-CO. . " · VG2S L __ __J
NOTE:
CI. C2, a C3: LEADLESS DISC CERAMIC, 0.001 I'F
C4: ARea 462, 5-80 pF. OR EQUIVALENT
L1: 3 TURNS No. 18 WIRE, 3/16 INCH-DIA. ALUMINUM SLUG
L.2;9 TURNS No. 20 WIRE, 3116 INCH-DIA. ALUMINUM SLUG
uti-uno
Fig. 12 - 200-MHz power gain gain-contro/lIOltag8, and noils-figure test circuit for 3N204*.
l
* In accordance with JEDEC registration data format (JS-9 RDF-19B).
VGG VDD
470 470
GAIN-CONTROL GATE SUPPLY VOLTAGE[VGGu.q-V
92CS-27.57 r--~H --l~P~l
I
I
"..
Fig. 11 - ![Link] .s. VGG(GC) I
8.2
I Mil Mil
I
L2
I 12~
I +-J\201'.2I/MIr"....._4-_~i--=f-<~ ~"":>'<--l--------1\ . 'f~"~11
FROMeO.Q.~f
SOURCE r I I
I
I
I 270.n
I
I I
L __
NOTE:
I---J
CI: L£AOLESS DISC CERAMIC, [Link]"F
C2:LEADLESS DISC CERAMIC, [Link].F
LI:8 TURNS No. 28 WIRE. 5/32 INCH-DIA. FORM, TYPE "J" SLUG
L2:9 TURNS No.28 WIRE, 5/32 [Link], TYPE "J"SLUG
92CM-27959
DRAIN CURRENT 1D:". 9ZCS-279!18
Fig. 14 - -45-MHz power-gain and noise-figure test circuit for 3N206*.
Fig. 13 - Gps ". ID * In accordance with JEDEC registration data format (JS-9 RDF-19B).
________________________________________________________________ ~5
3N204, 3N205, 3N206
FROM!M>Q
SOURCE
NOTE:
FOR TEST FIXTURE. HE PICTORAL. DRAWING IN FIGURE II
CI THRU C4 :SU: FIG""E II. NOTE 0
C5: 0.001 ~F LEAOLESS DISC CAPACITOR
C8 THRUCIO'ALLEN-8RADLEY F!lAU 0.001",' FEED-THROUGH CANCITORS,OR EQUIVALENT
LI • L2: SEE FIGURE 18
Fig. 16 - -46(J..MHz [Link] and noise-figure test circuit for 3N204* •
• In accordance with JEDEC ragistration data format (JS-9 RDF-19BI_
V DD
110 Ito. 45 MHz
2.2 of 1 I- ~
3N200
________ ~T~~~t
11
10
'0
CI C2
91 to
t·OOl",F
NOTE: T1: PRI: 16 TUANS No.30WIRE CLOSE WOUND
C1: ARCO<462, 5-80 pF, or EQUIVALENT ON 114 INCH DIA. FORM, TYPE "J" SLUG
C2: ARC0460, 1.5-16 pF. OR EQUIVALENT sec: 5 TURNS Na.30 WIRE CENTERED
L1: 4TURNSNo.14WIRE.1/4INCH INSIDEDIA. OVER PRIMARY
Fig. 17 - -200 MHz-to45-MHz circuit for conversion power gain for 3N205*.
'" In accordance with JEDEC registration data format IJS-9 RDF-19B).
__ ~ ______________________________________________________________ 457
3N211, 3N212,3N213
ELECTRICAL CHARACTERISTICS, At T A = 25°C (unless otherwise specified)
II .... IIENT TEMP£RATURE (Toll- 25·C
DRA'fI!- TO-SOURCE VOLTAGE 'Vosl-
!C fRIEO~NCY {fl_ t kH~
t~ V tt:t±:ttr:t:!:± tn-::t:
:~_.;..
LIMITS ~ . + 4
CHARACTERISTIC TEST CONDITIONS UNITS ! ~::+ l!t!
MIN. MAX.
* Drain-to-Source Breakdown 10 = 10pA, 3N211 27 - f
i
*
Voltage, V(BR)DS
Gate No.l-to-Source Forward
Breakdown Voltage, V(BR)G1SSFl
VG1S=VG2S= -4V 3N212
3N213
IG1=10mA, VG2S=VDS=0
27
35
6
-
-
-
V
V
r
j
~ 0
C!l
-a~ V
bJitg -: .: ~trp~
u.~ti1·.j:itt;.
-1-1---<-+
. + :.::-~ ~:
.::t[Link];'::::j.;~
......
':: :-;::
~+-T
t:
.... ~
-, o
t •
* Gate No.l-to-Source Reverse
IG1= -10mA. VG2S=VDS=0 -6 - V
I 2 4 3 ~
GATE Ho.2-TO-SOURCE VOlTAGE 'VG2St-V
Breakdown Voltage, V(BR)G1SSRl
Fig. 5-IYfslvs- VG2Sfar3N211and3N212_
* Gate No.2-to-Source Forward
IG2=10mA. VG1S=VDS=0 6 - V
Breakdown Voltage. V (BR)G2SSFl
* Gate No.2-to-Source Reverse
IG2= -10mA, VG1S=VDS=0 -6 - V
Breakdown Voltage, V(BR)G2SSRl
* Gate No.1-Terminal Forward
VG1S=5V, VG2S=VDS=0 - 10 nA
Current,IG1SSF
* Gate No.1-Terminal Reverse VG1S= -5V, TA=25°C - -10 nA
Current, IGl SSR VG2S=VDS=0 TA=150°C - -10 pA
,1:+ :..• :::.I:!±t±
* Gate No.2-Terminal Forward
VG2S=5V. VG1S=VOS=0 - 10 nA oR -:E if::
Current, IG2SSF -I 0 1 2 3
GATE No. 2-TO-SOURCE VOLTAGE (vG2S)-V
* Gate No.2-Terminal Reverse VG2S= -5V, TA=25°C - -10 nA
Current, I G2SSR Fig_ 6 - Iy fsl vs_ V G2S far 3N213.
VG1S=VOS=0 T A=150°C - -10 pA
* Zero-Gate No.1-Voltage VOS=15V. VG1S=O,
6 40 mA
Orain Current. IOS2 VG2S=4V
3N211 -0.5 -5.5
VDS=15V,
* Gate No_l-to-Source Cutoff
VG2S=4V, 3N212 -0_5 -4 V
Voltage. VG1S(off)
ID=20pA 3N213 -0_5 -5_5
3N211 -0.2 -2.5
VDS=15V,
* Gate No_2-to-Source Cutoff
VG1S=0. 3N212 -0.2 --4 V
Voltage, V G2S(off)
ID=20pA 3N213 -0.2 -4
* Small-Signal Common-Source VOS=15V. 3N211 17 40 lATE No.I-TO-SOURCE [Link] (V6ISI-V
Forward Transfer Admittance, VG1S=O, 3N212 17 40 mmho
VG2S=4V, Fig.l-IYfslvs. VGIS f or 3N211,and3N212.
IVfs l3 3N213 35
f=l kHz 15
* Small-Signal Common-Source
VDS=15V. VG2S=4V.
Reverse Transfer Capacitance, 0_005 0.05 pF·
Crss
ID=lmA, f=lMHz
1I ~=II:~io~i~:~:T~:Ti~A~t~:;I: t~
30 FREQUENCY (fl- t kHz
V
*In accordance with JEDEC registration data format (JS-9 RDF-198L
i-! e GATE-Ho.2-TO-SOURCE
VOl.TAGElVo2SI-4V
~ 20
1. All gate breakdown voltages are measured while the device is conducting rated gate current.
This ensures that the gate-voltage-limiting network is functioning properly. i
2.
2. This characteristic must be measured using pulse techniques hW = 300$£5, duty cycle ~ 2%1-
3. This characteristic must be measured with bias voltages applied for less than 5 seconds to
avoic4 "",""fleating. The signal is applied to gate No.1 with gate No.2 at ae ground.
-05'01 0'01
-I.! -I -D.! 0 o.~ t t.!
GATE Ho.I-TO-SOURCE VOLTAGE ("Glsl-v
Fig. 8- IYfsl vs. VG1S far3N213.
________________________________________________________________ ~9
3N211, 3N212, 3N213
Voo
470 470
r--~H
pF
-H-l r~oOi"
I ,.F 1
I 8.2 5.6 390Q I
I Mn Mn
I
I
I
~
5PF
FROM son
SOURCE
I
I
I
L_~
NOTE:
CI: LEADLESS DISC CERAMIC, [Link]'F
C2: LEADLESS DISC CERAMIC. [Link],...F * JEDECREGISTERED DATA - -
LI: 8 TURNS No. 28 WIRE. 5/32 INCH-CIA. FORM, TYPE "J" SLUG JEDEC RELEASE No. 6438.
L2:9 TURNS No. 28 WIRE, 5/32 INCH-CIA. FORM, TYPE "J" SLUG
92CM-26J77
Fig.10-4S MHz power gain and noise figure test circuit for 3N211 and 3N213*.
TEST CIRCUITS (CONT'DI
110 1----1
.n C2Ii 2 I
110
.n
200 MHz
50n
[Link],.F
I'
I L2
L_ __
NOTE 0
L1: 7 TURNS No. 34 WIRE, 114 INCH OIA. ALUMINUM SLUG
L2:5 1/2 TURNS No. 20 WIRE, 1/4 INCH OIA. ALUMINUM SLUG
L3: 7 TURNS No. 24 WIRE, 1/4 INCH OIA. AIR CORE 92CM-26J78
TI: PRI: 25 TURNS No. 30 WIRE CLOSE WOUND ON 1/4 INCH OIA. FORM, TYPE .JM SLUG
SEC: 4 TURNS No. 30 WIRE CENTERED OVER PRIMARY
g~:: ~~~ :;PLEE:~~ES~-~~~F * JEDEC REGISTERED DATA - - JEDEC
C3:0.01I'F LEADlESS OISC RELEASE No. 6438.
Fig.I'-200 MHz-to-45 MHz circuit for conversion power gain for 3N212*_
___________________________________________________________________ 461
40468A,40559A
Device Features:
MOS Silicon Transistors N-Channel Depletion Types
- high 1orw_rd tnlnsconductMce - -
gfs - 7500 /UIIho typo for 40468A
For RF Amplifier and Mixer Applications
Performance Features: -low feedback apllCitance - -
in FM and AM/FM Receivers en. - 0.35 pF mIIX. for 40468A
• reduced spuriow responses in FM tuners
0.38 pF mIIX_ for 40669A
RCA-40468A and 40559A are silicon insulated-gate _ ravena bias on IUbstnne improveslin....ity
field-effed transistors of the n-d18nnel depletion type _ reduced c:ross-modulltion effects in AM recaiven - high useful power gains - -
utilizing the MOS" construction. They are intended neutralized· 17 dB typo
primarily for use 8S the rf amplifier and mixer, respec- unneutl1llized - 14 dB typo
tively. in FM receivers covering the 88 to 108 MHz o hermetically IOOlocI in TO·72 metal pocklllJO
band, but can be used for general amplifier applications [Link] Ratings, Absolule-A./aximuffl Values at T" = 25°C:
at frequencies up to 125 MHz. For circuit design and DRAIN-Tt)-SOURCE VOLTAGE, VOS . . . . . • +20 V
typical performance data refer to RCA Application Note DRAlN-To-GATl-: VOLTAGE. Voe ....... +20 V
AN3535 .. An FM Tuner Using Single-Gate MOS Field- TERMINAL DIAGRAM
GATE-T(}..SOURCE VOLTAGE, Vas:
Effect Transistors as RF Amplifier and Mixer". CONTINUOUS (dc~ . . • . . . . . . . . . + I. -8 V
~
The wide dynamic range of these transistors re- PEAK ftc. . . . • • . . . • . . . . . . • • . . • . . ± 15 V
duces cross-modulation effects in AM receivers and DRAIN CURRENT. 10 . . . • • • . . • . . . . . . 25 mA
TRANSISTOR DISSIPATION:
~
minimizes the generation of spurious responses in
At ambient } up to 2SoC.. .... .. 330 mW
FM receivers.
temperatures above 2SoC • • • • • clerllll." lit 2 2 mW/oC
Operating as a neutralized amplifler at 100 MHz. the AMBIENT TEMPERATURE RANGE:
40468A can provide a power gain of 17 dB (typ.). A Storage. . . • . . . . . . . • . • . . . • . • • . . -65 to + 175°C
LEAD 1 - DRAIN
power gain of 14 dB (typ.) can be realized without Operating . . . . . . • . . . • • . • • . . . . . . -65 to + 175°C
LEAD 2 - SOURCE
neutralization. LEAD TEMPERATURE (During Soldering):
LEAD 3· INSULATED GATE
At distances not closer than 1/32 inch. to
seating surface for 10 seconds maximum. 265 °c LEAD 4 - BULK (SUBSTRATE) AND CASE
* Metal...()xide-Semiconductor.
ELECTRICAL CHARACTERISTICS, at TA = 25a C
With Bulk (Substrate) Connected to Source Unle .. Otherwise Specified
TEST CONDITIONS LIMITS
DC DC
Symbols Frequency Drain·to- Urain RCA-40468A RCA-40559A Units
Characteristics
Source Current RF Amplifier M~er
f viis 10
MHz V mA Min. Typ. Max. Min. Typ. Max.
Drain-la-Source Cutoff Current 10(011) 12 VGS =·8V 100 500 pA
Gate Leakage Currenl 0 VGS =·8V 1. 1 nA
IGSS
0 VGS =+IV 1 1 nA
Zero· Bias Drain Current lOSS 15 VGS =0 5 15 30 5 15 30 mA
Small-Sijp1al, Shorl-Circuit 1 kHz 15 5 7500 pmho
gfs
Forward Transconductance
Small-Signal, Shorl-Circ,it
Reverse-Transfer Capacitance Crss 1 15 5 0.25 0.35 0.25 0.38 pF
(Orain·lo-Gate)
Inp,1 Capacitance Ciss 1 15 5 5.5 5.5 pF
Admittance - RF IMi'" RF Mixer - - -
Inp,1 Admittance Vis 100 MHz 15 5 3 0.155 + j 3.45 0.14 + j 3.38 mmho
Forward Transfer Admittance YI. 100 MHz 15 5 3 7.4 +·0.9 mm 0
Outp,1 Admittance Yos 100z 1 10.7 15 5 3 0.21 + j 0.9 0.076 + j 0.153 mmho
MHz MHz
Forward COIlversion Transconductance gfs(C) 1 kHz 15 3 280tr pmho
Maximum Available Power Gain MAG 100 15 5 26 dB
Maximum Usable Power Gain MUG 100 15 5 - 14 dB
(Unneutralized)
Maximum Usable Power Gain MUG 100 15 5 14 17 dB
(Neutralized)
Maximum Available Cgnversion lin = 100 dB
MAGe 15 3 22
Gain lo,t =10.7
Noise Figure NF 100 15 5 3.5 5 dB
* Bulk (Substrate)-to-Soorce Volts (VBS) :: -3.
For characteristics curves, refer to types 3N128 and 3N143.
____________________ ~ _____________________________________________ 463
40603,40604
PERFORMANCE FEATURES
SILICON DUAL INSULATED·GATE FIELD·EFFECT TRANSISTORS • large dynamic range permits [Link] handling be-
M·Channel Depletion Types fore overload
For FM , aner Applicatiols • dual gates allow product mixing with extremely low
harmonic generation
RCA 40603 and 40604 are ft¥channel silicon, deple- • greatly [Link]." spurious r •• ponses in FM receivers
tion type, dual insulated-gate, field-effect transistor!;
• permits use of vacuum-tub. biasing techniques
utilizing the MOS construction.
These devices have exceptional characteristics for • excellent thermal stobi lity
rf-amplifier (40603) and mixer applications (40604) in
FM tuners and other 'commercial equipment operating • [Link] cross-modulation performance and great.r dy_
at frequencies up to approximately ISO MHz. These trElD- namic range than bipolar and singl.-gat. field •• ffect
sistors feature a series arrangement of two separate MaxiMum Ratings, Absolute-Maximum Values at TA = 2SoC: transistors
channels. each channel baving an independent control DRAIN-TO-SOURCE VOLTAGE, VDS' •.. o to +20 v
gate. For amplifier applications the 40603 with its wide GATE No.l-TO-SOURCE VOLTAGE, VGlS:
dynamic range provides substantially better cross-modu- Continuous (de) . . . . . . . . . . • . . . . . -8 to +1 v DEVICE FEA TURES
lation performance and relative freedom from spurious
Peak ae . . . • • • . . . . . . • . . . . . • . . -8 to +20 V
responses than is obtainable with bipolar or single-gate • extremely low feedback capacitance
GATE No.2-TO-SOURCE VOLTAGE, VG2S: Cr .. = 0.02 pF .yp.
field-effect transistors. The mixing function performed
by the 40604 is unique in that the signal applied to gate Continuous (de) • • . • • • • . . . . . . • • . -8 to 4D"!G of VDS V
No.2 is used to modulate the input-gate (gate No.1) Peak ae . . . • • • • . • • . . . . • • . . • •. -8 to +20 V • high unneutralized RF power gain
transfer characteristic. This technique is superior to DRAIN-TO-GATE VOLTAGE, MUG = 25 dB (typ.) for 40603
conventional "squbre law" mixing. which can only be VDGI or VOO2 . • . . • • • . . . • • • • . . • '20 v
accomplished in the non-linear region of the device trans- DRAIN CURRENT, ID (Pulsed): • low "oi se figure
fer characteristic. ~:t~;a~~:t~O.~52.0.~S: • . • . • • . • • • . 50 mA
HF = 2.5 dB 'yp. for 40603
Because of the low feedback capacitance (0.02 typo TRANSISTOR DISSIPATION, PT:
pF) the 40603 can provide a power gain of 25 dB (typ.) At ambient lup to 25°C. • • . • • • • . 400 mW
at 100 MHz in an unneutralized amplifier circuit. r
temperatw-es above 2S o C . . • . . . . . • derate linearly at
2.67 mW/oC TERMINAL DIAGRAM
The gain of the ~f stage can be controlled by apply- AMBIENT TEMPERATURE RANGE:
~
ing age:: voltage to gate No.2. Virtually no age power is Storage and OperatiDg . • . . • . . . • • . . -65 to +175 °c
required for full gain reduction.
LEAD TEMPERATURE (During soldering): [Link] l_Drai.
The 40603 and 40604 are hermetically sealed in At djstances > 1/32" from seating L.... 2-G.t. No. 2
~
JEDEC TO-72 packages. surface for Urseeonds max • . . . . . • • . L...4 3-Gcrt. No. 1
L...d .. - Source• .s..,... aM C....
ELECTRICAL CHARACTERISTICS, 0' T A = 2S·C
LIMITS
401113 40604
CHARACTERISTICS SYMBOLS TEST CONDITIONS RF AMPLIFIER MIXER UNITS For characteristics curves, refer to type 3N140.
Typ. Max. Typ. Max.
Gale No.l-to..source Cutoff
VGlS(off)
=
Vos +15 V, 10 =200 p,A ·2 ·2
Voltage VG2S =.ft1V
Gate No.2-la-Source Cutoff
VG2S(offl
Vas'" +15 V, 10 =200 p,A ·2 ·2
vonace VGlS '" 0
Gate No.1 Leakage Current 'GISS VGlS'" -20 v, VG2S '" 0, Vas'" 0 "A
Gate No.2 leakage Cunent 'G2SS VG2S '" -20 V, VGIS '" 0, Vas'" 0 "A
Zero-Bias-Voltage Drain Current lOSS VG2S = +4 V, VGIS = 0, Vas'" +13 V 18 18 rnA
Small-Sianal, Short-Circuit
Vas = +13 V, 10 '" 10 mA, f '" 1 MHz
Reverse-Transfer CapaCitance C'SS 0.02 0.03 0.02 0.03 pF
( O,ain·to-Gate-No.l) VG2S = +4 V
Vos = +13 V, 10 = 10 rnA
Input Capacitance Cis5 5.5 5.5 pF
VG2S'" +4 V, f '" 1 MHz
Vos'" +13 V, '0 = 10 rnA 2.1 2.3 pF
Output Capacitance Coss
VG2S '" +4 V, I '" 100 MHz
Vos = +13 V, 10 - 10 rnA
Input Resistance lis 3.5 J.5 kG
VG2S'" T4 V, f::- 100 MHz
Vos:- +13V f := 100 MHz iJ1
Output Resistance 'os '0 - lOrnA
VG2S"'+4V f'" 10.7MHz 20 iJ1
Vos = +13 V, '0 = 10 rnA
Forward Transconductance
", VG2S = +4 V, f'" 1 kHZ'
10,000 2800* /llTlho
Maximum Available Power Gain MAG 26 21 dB
Vos = +13 V. to = 10 rnA
Maximum Uaable Power Gain VG2S" +4 \I
MUG 25" dB
(Unneutralized) f - 100 M!'1z. 'out for 40604
(mixer) " 10.7 MHz
Noise Figure NF 2.5 dB
• conversion tlan$c~~~~tance
"'01 limlte~"--F·"" .Ydesign considerations
______ ~ _____________________________________________________________ 465
40819
Silicon Dual-Insulated-Gate Field-Effect Transistor The back-te-back diode configuration permits the 40819 to
retain the wide input signal dynamic range inherent in the
N~Channel Depletion Type MOSFET. In addition, the low junction capacitance of these
With Integrated Gate-Protection Circuits diodes adds little to the total capacitance shunting the signal
The two-gate arrangement of the 40819 also makes possible gate.
For RF Amplifier Applications up to 250 MHz a desirable reduction in feedback capacitance by operating
in the common-source configuration and ae grounding Gate The 25-volt drain·to·source rating permits the use of higher
No.2. The reduced capacitance allows operation at maxi· voltage power supplies.
RCA·40819 is an n-channel silicon, depletion type, dual in- mum gain without neutralization and reduces local oscillator The 40819 is hermtically sealed in the metal JEDEC TO-72
sulated-gate field-effect transistor (FEn. feedthrough to the antenna - features of special importance package.
The excellent overall performance characteristics of the in rf and if amplifiers.
TERMINAL DIAGRAM
RCA·40819 make it useful for a wide variety of rf-amplifier Special back·to-back diodes are diffused directly into the
applications at frequencies up to 250 MHz. The twa serially- LEAD 1 • DRAIN
MOS pellet and are electrically connected between each
connected channels with independent control gates make insulated gate and the FET's source. The diodes effectively LEAD2·GATENo.2
LEAD 3· GATE No.1
~'
possible a greater dynamic range and lower cross-modula- bypass any voltage transients which exceed approximately
tion than is normally achieved using devices having only a ±10 volts and protect the gates against damage in all normal LEAD 4 • SOURCE,
single control element. handling and usage. SUBSTRATE, AND CASE
ELECTRICAL CHARACTERISTICS, at TA = 250 C unless otherwise specified I 4
LIMITS
CHARACTERISTICS SYMBOLS TEST CONDITIONS UNITS
Min. Typ. Max. Device Features
VOS' +15 V, 10' 200 pA • back-to-back diodes protect each gate against handling 8(fd
Gale-No.l-to·Source Cutoff Voltage VG1SIDff) -2 -4 V in-circuit vMlsiants
VG2S" +4 V
• high forward transconductance: 9fs = 12,000 [Link] (typ.)
VOS" +15 V, 10' ZOO pA • high unneutralized RF power gain: Gps = 18 dB hyp.) at
Gate-No.2-to-Source Cutoff Voltage VG2SIDft) -2 -4
VG1S' 0 200 MHz
• low VHF noiSe figure: 3.5 dB hyp.) at 200 MHz
Gate-No.l-leakatJe Current VG1S" ±6 V 50 nA
IG1SS VOS" 0, VGZS • 0 • low gate leakage currents: IG1SS & 'G2SS = 50 nA at TA = 250 C
• increased drain-to·source voltage rating: VOS =-0.2 to +25 V
VG2S'i6V
Gate-No.2·leakage Current IG2SS 50 nA
VOS· 0, VG1S' 0
VOS"+ 15V Performance Features
Zero-Bias Drain Current lOSS 15 35 mA
VG2S • +4 V, VG IS' a • superior cross-modulation performance and greater
dynamic range than bipolar or· single-gate FET s
VOS" +15 V, 10 " 10 mA
Forward Transconductance (Gate-No.l-to-Drainl 9fs 12,000 JHl1hD • wide dynamic range permits large-signal handling before
VG2S:: +4 V, f :: 1 kHz overload
Small·Signal, Short,Circuit Input Capacitancet pF • virtually no age power required
VOS = +15 V, 10 = 10 rnA • greatly reduces spurious responses in FM receivers
Small-Signal, Short-Circuit,
pF • dual gate permits simplified AGe circuitry
AeverseTransfer Capacitance ern VG2S =+4 V, f '" 1 MHz 0.005 0.02 0.03
(Orain-Io·Gate No.1l'
Small·Signal, Short·Circuit Output Capacitance Coss pF
Power Gain (see Fig. 11 Gps 14 lB dB Applications
Ma)!imum Available Power Gain MAG dB • RF amplifier, mixer. and IF amplifier in military,
20
industrial, and consumer communications equipment
Maximum Usable Power Gain (unneutralizedl MUG 20· dB • aircraft and marine vehicular receivers
VOS" +15 V, 10' 10 mA
Noise Figure hee Fig. 1l NF 3.5 6.0 dB • CATV and MATVequipment
VG2S" +4 V, f" 200 MHz
• . "tetemetry and multiplex equipment
Magnitude of Forward Transadmittance 12,000 JHl1ho
Phase Angle of Forward Transadmittance -35 degrees
Input Resistance kG Absolute Maximum Values, at TA =2~c:
Output Resistance ross 2.B kG Drain-tO-Source Voltage, Vos . -0.2 to +25 V
Gate Terminal Current,
Protective Diode Knee Voltage ldiode (reversel - ±100 JJA - ±10 V IG1S or IG2S . ±100 pA
Orain-to·Gate VOltage,
• limited only by practical design considerations. t Capacitance between Gate No.1 and all other terminals. VOGI or VOG2. +31 V
, Three-terminal measurement with Gate No.2 and Source returned to guard terminal. Drain Current, 10 •. 50 mA
Transistor Dissipation, PT:
#Ferrite bead (41; Pyroferric Co. Q= 40673 At TA up to 2SJC 330 mW
"Carbonyl J" 0.09 in 00; 0.03 .. Disc ceramic.
in 10; 0.063 in thickness. ~ * Tubular ceramic. At T A above 2SJC derate lineerlv 2.2 mWfOC
Ambient Temperature Range:
All resistors in ohms
Operating and Storage . -65 to +175 0c
All capacitors in pF
Lead Temperature tOuring Soldering):
C1: 1.8 - 8.7 pF variable air capacitor: E. F. Johnson At distances 1/32 in from seating
Type 160-104, or equivalel:lt. surface for 10 s max ......... . 265 0c
C2~ 1.5 - 5 pF variable air capacitor: E. F. Johnson Type
, 160-102, or equivalent. Maximum Ratings
I
I C3: 1 - 10 pF piston-type variable air capacitor: JFO Continuous Working Voltage#, at TA = 2!tC:
- ,
I
I
Type VAM-Ol0; Johanson Type 4335, or equivalent.
Z~35 Gate No.1-to-SOurce Voltage, V01S. -6 to +3 V
L------I--:::t...----
I
_~----I---~----..J
OR EQUIV.) I C4: 0.8 - 4.5 pF piston type variable air capacitor: Erie
560·013 or equivalent. Gate No.2-to-Source Voltage, VG2S .. -6 to +6 or V
'lXJ0"" 1000- 1000-
40% of V DS
Ll: 4 turns silver-plated O.02·in thick. 0.075-0.085 in
wide, copper ribbon. Internal diameter of winding = /whictlever value is lessl
0.25 in, winding length appro)(. 0.80 in. Drain-ta-Gate Voltage, VDGl or
VDG2·· +25 v
4-1/2 turns silver-plated 0.02 in thick, 0.085-0.095-
L2:
in wide, 5/16·in, ID Coil = .90 in long.
Continuous Working Voltage Aanng5 must 1:)8 observea tu rnaintam
Fig. 1. 200 MHz power gain and noise figure rest circuit device characteristics. These ratings are based on long-term con-
tinuous voltage operation but may be exceeded for short durations
le.g. testing of device characteristics), provided the absolute Maxi·
For characteristics curves, refer to type 3N187. mum Ratings are not e)(ceeded.
- - - - - -__________________________________________________________ ~7
40820,40821
ELECTRICAL CHARACTERISTICS at T A'" 26G C
LIMITS
CHARACTERISTICS SYMBOLS TEST CONDITIONS 40820 40821 UNITS
Mm Typ Mal<. Mm Typ
Gate No 1 to SOurce Cutoff Voltaqe VGIS(olil Yes" -t16V ,IO"200"A, VG2S" -t4V
M"
.,
Gate No "l to SOllrce ClItOtt Voltage VG2S(0Itl VOS· +1!5V,lo-200"A,V.G1S-0 -, -,
Gate to Source Forward Breakdown Volldoge IG1SSF
GaleNo , V(BR1G1SSF 0
1(l2SSF VG2S VoS
Gate No 2 [Link] 11
V(BRIG2SSF VG,S VoS 0
Gale 10 Source Reverse Breakdown Vollaqe IGISSR
GaleNa 1 VIBRIGISSR 0 11
IG2SSR VG2S VoS
GaleNo "} VIBRlG2SSR IOOIJA
VG,S VoS 0
VG1S 6V 50 oA
Gale No I Term'nal FOlwardC,,,,enT IGISSF Vos VG2S 0
VGIS 4SV 50
VGIS 6V 50 oA
Gale No 1 Termonal Rl!\l!rse CUllen! IG1SSR VOS VG2S 0
VGIS '5V 50
VG2S 6V 50
Gate No 2 Termonal Forward CUllenl IG2SSF VDS VG1S 0
VG2S 4SV 50 oA
VG2S -6\' 50
Gale No 2· Terminal Reverse Curren! IG2SSR VoS VG'S 0
VG2S "V 50
Zero·Blas Drain Currenl 05
Forward Tran!.Conductance
'05 VoS '15V, VGIS
f
O,VG2S
1 kH, 01000
" "mho
IGateNo.I·I~raln) 9f~ '000
Sm~1I SIgnal, Short CIlCUlt Inpu! Capacllance* C'S5 85 ,F
Small Signal, Short Clleu,l, Reverse Tlansfer
Caopaeltance IOraon to Gale No II' C,ss VoS '15V 0005 00' DO' o OIlS 00' 004 ,F
'0 lOrnA
Small SIgnal. Short CorCUlt Output CapaCitance Con VG2S .," ,F
Power Gam (see Fig. 61 Gps dB
Noise Figure (Me Fig. 6) , "lOOMHI dB
Conllerslon Ga.n GpSIC)
, 200/44 MHI dB
• Caopacltance between Gate No , and all other termonals , Three termonal measurement WIth Gale No 2 and Source returned 10 ~ard terminal
, - - - - - - - - - -.7------ - - - - - - - - - - l
1 AGC' -4 TO ti~TERNAL SHIELO.... '"""' Q C4 OUT~UT ;::Fjlrrite bead (4); Pyroferric Co Q'" 40820
, "Carbonyl J" 0.09 in 00; 0.03 1I'Oi!ICceramic.
in 10. 0.063 in thickness. • Tubular ceramic.
All resistors in ohms
All capacitors in pF
~1: i:pe-l:0~1g:. ~~r~~~~a~!~t~apacltor: E. F. Johnson
C2: 1.5 - 5 pF variable air capacitor: E. F. Johnson Type
160·102, or equivalent
C3· 1 - 10 pF piston·type variable air capacitor: JFO
Type VAM·Ol0; Johanson Type 4335, or equivalent.
1:4. 0.8 - 4.5 pF piston type variable air capacitor. Erie
560·013 or equivalent.
Lt· 4 turns silver·plated 0.02·m thick, 0.075·0.085 in
WIde, copper ribbon. Internal diameter of winding ~
025,", winding lenglh approx. 0.80 in.
L2 4·1/2 turns silver·plated 0.02 in Ihick,O.085·0095
in wide, 5/16·in; 10 Coil ~0.90 in. long.
L - - -_ _ _ _ _ _ _ _....._.~5D9 9ZCS-17465
Fig.2 - 200 MHz power gain and noise figure test circuit for type 40820.
Table 1 - V parameters vs. frequency
FREOUENCY (MHz)
CHARACTERISTICS SYMBOL UNITS
50 100 200 250
Y Parameters
Input Conductance gis 0.08 0.33 1.0 1.6 mmho
Input Susceptance bis 1.8 3.6 7.5 9.8 mmho
Magnitude Forward Transadmittance IVil;1 12 12 12 12.3 mmho
Angle of Forward Transadmittance <Yfs -2 -13 -35 -45 degrees
Output Conductance 905 0.10 0.18 0.36 0.42 mmho
Output Susceptance bos 0.5 1.0 2.0 2.6 mmho
Magnitude of Reverse Transadmittance Iv,,1 8 12 ~mho
25 140
Angle of Reverse Transadmittance <Vrs -88 -73 -25 -10 degrees
_____________________________________________________________________ 469
40841
Applications:
Silicon Dual-Insulated Gate Field - Effect Transistor • DC amplifier. • choppers
N·Channel Depletion Type • R F amplifiers • voltage-controlled anenuators
• mixe" • c:onstant-current source
With Integrated Gate-Protection Circuits Device Features: • I F amplifiers • voltage regulator.
General·Purpose Economy Type for Appl ications • back-to-back diodes protlCt gate insulation against damage • video amplifiers • telemetry 81 multiplex
due to static changes frequently encountered during handU", • differential amplifiers • servo amplifiers
from DC to 500 MHz • frequency multiplier, • proximity switches
• hi.... forward transconductance: tfs .. 12,000 Jbnho hvp.)
• phase splitt. .
RCA-40841 is an n-channel silicon, depletion type, dual- • high power gain: Gps = 32 dB (typ.) at 44 MHz • industrial timers - long time delays
insulated gate, field-effect transistor intended for general· • gate leakage currents: IG1SS and IG2SS = 60 nA (mix.) • [Link] tri .... circuits
purpose applications from DC to frequencies up to 500 MHz. atT A' 250C
This MOS/FET provides excellent power gain, linear-circuit • hi.. Input impedance
operation and has a wide dynamic operating range. Its • excellent thermal stability
square-law characteristics result in low cross-modulation
performance over the AGe range. Its dual-gate construction Performance Features:
reduces feedback capacitance by shielding Gate No.1 from TERMINAL DIAGRAMS
• superior cross-moclulation performance and . . ._ dynamic:
the drain, and makes it possible to isolate the local oscillator range than bipolar and junctton-gate FET.
signal from the incoming signal bv applying the two signals
• wide dynamic range [Link]-....I handling before SINGLE-GATE CONFIGURATION
to separate gates. The very low feedback capacitance of this
m
overloading
device eliminates the need for neutralization in circuits using
the dual-gate configuration. Use of the device in the RF • virtually no age power required
input stage of a receiver reduces local oscillator feed-through • .-aatfy reduced spurlous respon_ in AM and FM raceiv.s
to the antenna. The 40841 requires negligible AGe power, .dUlI--gate confi......ion [Link]'1ed AGC circuitry
provides automatic delay when AGe is applied to Gate No. • op..-ates at frequencies to 600 MHz without nMItraIization
2, and exhibits sli9'lt input impedance variations during AGe in circuit. utilizing the dual ....te configuration LEAD 1-0RAIN
~
functioning. The device has exceptionally high input im- LEAOS-2 AND 3-GATE
.operltes up to UHF with low-noi.. perfonnance
pedance, an attribute for timing-circuit design. LEAD 4-S0URCE.
SUBSTRATE AND CASE
Back-to-back diodes are fabricated on the same monolithic
silicon pellet as the MOS/FET to protect the gates against The following dual-gate MOS/F ET types are specified for
damage due to electrostatic charges frequently encountered appltcations requiring premimum-grade performance: 3N200,
during normal handling. These back·to-back diodes also
3N187. 40673. 40819. 40820. 40821. 40822. and 40823.
function as "transient trappers" by limiting in·circuit
transient voltages that exceed ±10 volts_
Detailed information. utilizing RCA dual-gate protected
Maximum ratings and electrical characteristics are included in MOS/FETs in RF applications, is given in the following RCA.
the data for operation of the 40841 as the equivalent of a Application Notes: AN-4431 "RF Applications of the DUAL-GATE CONFIGURATION
single-gate device. For single-gate operation. connect Gate Dual-Gate MOS/FET up to 500 MHz" and AN-401B "Design
No. 1 (Term. 2) to Gate No.2 (Term. 3). as shown in the
~
of Gate-Protected MOS Field-Effect Transistors".
Terminal Diagrams on Page 2. The 40841 MOS/FET is
hermetically sealed in the metal JEDEC TO-72 package.
Maximum Ratings Dual-Gata Singlo-Gate LEAD 1-DRAIN
LEAD 2-GATE No.2
~
Configuration Configuration LEAD 3-GATE No.1
AblOlutfl Maximum Values, at TA =2!PC: LEAD 4-S0URCE
Drain-to-Source Voltage. VOS ... _ ........... _............ . ~.2to+18 -0.210 +18 V SUBSTRATE AND CASE
Gate Terminal Current. IGl S or 'G2S ..... _..... ____ ....... . ±100 ~A
Gate Terminal Current. IGS _.............................. . ±100 ~A
Orain-to-Gate Voltage, VOGl or VOG2 _. __ . _..... _......... . +24 V
Drain-to-Gate Voltage, VOG ................ _..... _ • _..... . +24 V
Drain Current, 10 ..................................... _. 50 50 mA
Transistor Dissipation:
DRAIN-TO-SOURCE [Link])-1
AtTAupto250C ................... _ ......... _ ... _. 330 330 mW AMBIENT TEMPERATURE ITA)-e-c
At T A above 25°C .................... _............. . derate linearly 2.2 mWJOC 10
2
Ambient Temperature Range:
Operating and Storage ....... _ ......... _ ....... _. _. _. _. -65 to +175 -66 to +175 °C
Lead Temperature (During Soldering):
At distances 1132 in from seating surface for 10 s max. ,_. 265 265 °C
Continuous Working Vo/rage#, at TA $: we: 3
Gate No.1-to-Source Voltage. VG1S .................. . -4.5 to +3 V i
Gate No. 2-to-Source Voltage, VG2S ....................... . -4.5 to +4.5 or 40% of VOS V
(wh ichever value is less)
Gate-to-Source Voltage, VGS ............ _ . _ ....... _ ...... . -4.5 to +3 V
Orain-to-Gate Voltage, VOG1 or VDG2 ........ _.... _........ . +20 V
Drain-to-Gate Voltage, VOG .............. _... _........... . +20 V
#Continuous Working Voltage Ratings must be observed to maintain device characterinics. These ratings .re based on long·term continUOUI
voltage ope,atiOfl but may be exceeded for short durations (e.g. testing of device ch.-acteristictl, provided the Absolute Maximum Ratings
are not exceeded.
Fig.l-fO"" VGI$
GATE NO.2-TO-SOURCE [Link](VG2S'-" ~ CO....ON SOURCE CIRCUIT
A..IIENT TEMPERATURE (TA'-U-C
AMalENT TEMPERATURE ITA I- 25'"C ~
10 FR£QUENCY CfI-lkHr
10 GATE NO.I-TO-SOURC£ VOLTS {V6lS'-0 ORAIH-TO-SOURCE VOLTS CVOS)-15
o
GATE NO.2-TO-SOURCE [Link]\/: )-+4
" -0.2
-0.5 -0.4
-0 .•
DRAIN-TO-SOURCE VOlTS ~~)-15
AMBIENT TEMpfRATURECTAI-Z5-C
':.\'tffl
-0.8
.,
-1.0
-1.2
°., -I 0 I 2 3
GATE NO.2-TO-SOURCE [Link] (vGZS)
4 4 • • ~ 12 ~ 16 ., .1
ORAIN-TO-SOURCE [Link] tvos' GATE NO.I-TO-SOURCE [Link] CVOIS)
Flg.2-fO"'. VG2S· Ffg.3-fO'" VOS· Fig.4-gfs"· VGIS·
___________________________________________________________________ 471
40841
SOLID-STATE TIMER FOR INDUSTRIAL APPLICATIONS
Cornetl·Oubilier Electronics- Ty~ MMW or equivalent. TIMING CIRCUIT CHARACTERISTICS 02: VORM'" 60V
R controls duration of time delay. At A'" 60 Mn up to
T A = _,25°C to +SOOC IGT = 2OO~A
5·minute delay (lAC resistor. Type CGH or equivalent)
Accuracy: ±1O% (over temperature) IT'" O.8A
This circuit can also be u58d at supply voltages of 240 V AC
and 24V AC (6OHzl by changing the values of Rl and 03. Repeatability: ±a% (at 2S 0 C) 03: IA= lnA
Reset Time: Less than 150 ms V R = 60V
Fig. 12- Typical timingcin;uir utilizing the 40841 in a single-gate configuration.
___________________________________________________________________ 473
Dimensional Outlines
_ _ _ _ _ _ _ _ _ _ _ _ _ 475
Dimensional Outlines
TO-5STYLEPACKAGES
IT) Suffix (JEDEC MO-002-AL) 8-Lead TO-5 Style
(S) Suffix a-Lead TO-5 Style with
INCHES MILLIMETERS Dual-In-Line Formed Leads (DIL-CAN)
SYMBOL NOTE
MIN MAX. MIN. MAX. I
a 0.200 TP 2 5.88 TP
0.010 0.050 1.27
'1
Al 0.26
A2
oB
0.165
0.016
0.185
0.019 3
4.20
0.407
4.69
0.482
ii~~1:9~~~A
OIA· .185 MAX
.305-.335 14.70)
oBl 0.125 0.160 3.18 4.06
17.750'11: 50 ) .070-.150
oB2 0.016 0.021 3 0.407 0.533 .015-.050 11.78-3.811
.39-1.27)Lf~~~~:J=~-l,
00 0.335 0.370 8.51 9.39
00 1 0.305 0.335 7.75 B.50 •(
Fl 0.020 0.040 0.51 1.01
I 0.028 0.034 0.712 0.863
k 0.029 0.045 4 0.74 1.14
Ll 0.000 0.050 3 0.00 1.27
L2 0.250 0.500 3 6.4 12.7
L3 0.500 0.562 3 12.7 14.27
92CS-19431R2 a 45 TP 45 TP
N 8 6 8
.IOO± .010
Nl 3 5 3 (2.54t·254)
(3 SPACES) .300t.0I0
NOTES 1762 t .254)
NON CUMULATIVE
Refer 10 JEDEC Publication No 95 for Rules for Dimensioning Measure from MOl,.., 410
Axial Lead Product Outlines
92CS-20296R3
Nl IS the quantity of allowable mlssmg leads.
Leads at gauge 'plane Within 0,007" W.17S mm) radium of True
Position ITP)at maximum malenal condition N IS the maXImum quantity of lead poSitions
3. <> B applies between L 1 and L2.~B2 applies between L2 and
0.500" (12.70 mm) from seating plane. Diameter is uncontrolled
in L 1 and beyond 0.500" (12.70 mm)
(T) Suffix (JEDEC MO-OO6-AF) 10-Lead TO-5 Style (V) Suffix
10 Formed Leads Radially
Arranged TO-5 Type
INCHES MILLIMETERS
SYMBOL NOTE
MIN. MAX. MIN. MAX.
a 0.230 TP 2 5.84 TP
0 0 0 0
~1
A> 0.166 0.185 4.1. 4.70
.8 0.016 0.019 3 0.407 0.482
.81 0 0 0 0
.82 0.016 0.021 3 0.407 0.533
00 0.335 0.370 8.51 9.39
00 1 0.305 0.335 7.75 8.50
Fl 0,020 0.040 0.51 1.01
J 0.028 0.034 0.712 0.863
k 0.029 0.045 4 0.74 1,14
l1 0.000 0.050 3 0.00 1.27
L2 0.250 0.500 3 6.4 12.7 92CS-14638 R2
L3 0.500 0.562 3 12.7 14.27
0 360 TP J60TP
N 10 6
-------,-0-
Nl 1 5 1
NOTES,
1. Refer to Rules for Dimensioning Axial Lead Product Out· 4. Measure from Max. 410.
lines. S. Nl is the quantity of allowable missing leads.
2. Leads at gauge plane within 0.007" 10.178 mm~ radius of 6. N is the maximum quantity of lead positions.
True Position ITP) at maximum material condition.
3. 41B applies between L1 and L2. 41B2 applies between L2
and 0.500" (12.70 mm) from seating plane. Diameter is
uncontrolled in Ll and beyond 0.500" (12.70 mm). 92CS-15835
_____________________________________________________________________ 477
Dimensional Outlines
OUAD IN-LINE PACKAGES (Cont'd) Recommended Mounting - Hole
(W) Suffix 16-Lead Staggered
In;
.025(.64IR. 16 15 14
.745-.785
(18.93-19.931
13 12 II
~
10 9
Dimensions and Spacing
MECHAmg~~ ----,--
INDEX
".! .240-.260
1.610-.660)
AREA 1 ~
234 6 7 8
TOP
VIEW
ftCS-ZH"
NOTES:
,. Body width is measured 0.040" 11.02 mml from top surface.
2. Seating plane defined as the junction of the angle with the
narrow portion of the lead.
Dimensions in parentheses are millimeter
equivalentl of the basic inch dimensions.
(0) Suffix 16-Lead
.785
.74e (19.93)J
.02'('64)R~ ~
18.93 Recommended Mounting - Hole
::::::J:: r.~)
" .. 12 " 10 • Dimensions and Spacing
'~:::"~i .k-~--$--$--/~~~~
(i;+~_$_$_}~~ .
12545.7.1
1~
60(1.90) .200 , _ _ _ _ _ _ _ _ _ _ _ _ TOP VIEW
.015 .39 ~ [Link] TERMINAL NO.1
,050 1.27
, t:D-$-$-$-
! !--
.020 ( .51 ) .200 ('.08)
t .15' 3.94
___
1$_$_$-
~ JL~ ~:;(1.65) I
--t
It-<'21~~)
.., ~.030 (.7&)0IA •
J
16 HOLES
I~.~~I
. 200 li~~1 12.541 .035 .89 NOTES: TYP. (IN CIRCUIT BOARD)
MIN. TYP. .020 (.50e) 1. Bodv width is measured 0.040" (1.02 mm) from top surface.
.300 . 014 .356 2. Seating plane defined as the junction of the angle with the
17.62) 91CS -17S35RI
narrow portion of the lead.
TVP 92C$-17580
.Q08-.013 Dimensions in parentheses are millimeter
1203-.3301 equivalents of the basic inch dimensions.
20-Lead Shielded
I'
Recommended Mounting - Hole
Dimensions and Spacing
~
~--~--$--$-$--
.100-.120
12.54-3.041
(2'.~~'
INDEX
NOTCH
T
.200
15.08)
~ ~$--$--$-$
M----------
/
1 d,
---+-'j'--If'-'f'--'f'-
'"
TERMINAL No.1
'" ,h
TQPIJIEW
/ -rtf--! $--cil--$--$-
'><.10 ';F I I ,lOa ~~030(.76) OIA
(3,58 -l r-12.541 18 HOLES
TYP. TYP (IN CIRCUIT BOARDl
92CS-17!!181
NOTES:
1. Body width is measured 0.040" (1.02 mm) from top surface.
2. Seating plane defined as the junction of the angle with the
narrow portion of the lead.
Dimensions in pa-entheses are millimeter
NOTE: TERMINALS II AND 20 ARE OMITTED. equivalents of the basic inch dimensions.
_______________________________________________________________ 479 9ZCS-17!587AI
Dimensional Outlines
DUAL·IN·LlNE AND QUAD-IN·LINE PLASTIC PACKAGES.
(Power Stud a d Heat-8ink Types)
(EM) Suffix (aM) Suffix
16·Lead with Integral Strap Heat Sink 16-Lead Staggered with Integral Strap Heat Sink
END ALIGNMENT OF HEAT SINK
END ALIGNMENT OF HEAT SINK TO CENTER OF PLASTIC BODY
TO CENTER OF PLASTIC BODY
I
TERMINAL r
/ O.537-0.587~ct. L--++---g::8~Ji~b ~~~AkN(2)
INDEX AREA (13.64-14.91) 1.125(28.58) - - - - J io~i~::g,,~,~
I
PLASTIC BODY
(~9'~-5~O~f L
~ I
~
('l;.~.~
.
.
~o.
.125-0.150
15°
J~'~(7'62)TYP'
0.020- 0.050
(0.51-1.27)
TJ 0.100 (2.54) TYP.
La,[Link] (3.18-3.S0
L
. [Link](254)TYP:
.---j I (3.18-3.81)
CENTER OF LEAD
0.008-0.013
10.39-1.52)
Po~I:':?'~2Ef 92CM-2!1649RZ (0.204-0.330)
TO·220-STYLE (VERSA·V) PLASTIC PACKAGE
VERTICAL MOUNT HORIZONTAL MOUNT (M Suffix)
I
!
SYMBOL INCHES MI LLiMETERS SYMBOL INCHES MILLIMETERS
MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX.
A 0.876 0.896 22.25 22.75 A 0.726 0.746 18.44 18.94
B 0.396 0.408 10.06 10.36 B 0.396 0.408 10.06 10.36
C 0.173 0.182 4.395 4.622 C 0.173 0.182 4.395 4.622
0 0.604 0.619 15.35 15.72 0 0.604 0.619 15.35 15.72
E 0.263 0.273 6.681 6.934 E 0.263 0.273 6.681 6.934
F 0.168 0.188 4.268 4.775 F 0.221 0.251 5.614 6.375
G 0.100 0.104 2.540 2.641 G 0.100 0.104 2.540 2.641
H 0.320 0.340 8.128 8.638 H 0.143 0.163 3.633 4.140
J 0.246 0.254 6.249 6.451 J 0.246 0.254 6.249 6.451
K 0.046 0.054 1.169 1.371 K 0.046 0.054 1.169 1.371
L 0.496 0.508 12.60 -12.90 L 0.496 0.508 12.60 12.90
M 0.140 0.150 3.556 3.810 M 0.140 0.150 3.556 3.810
N 5 5 N 5 5
P 0.015 0.020 0.381 0.406 P 0.015 10.020 0.381 I 0.406
Q 0.033 0.040 0.839 1.016 Q 0.033 0.040 0.839 -T 1.016
R 0.129 0.139 3.277 3.530 R 0.129 0.139 3.277 I 3.530
S 0.600 0.630 15.24 16.00
T 0.680 0.710 17.27 18.03
__________________________________________________________________ 481
Application Notes
_ _ _ _ _ _ _ _ _ _ _ _ 483
AN-4431
Because the published Yrs value for the 3N200 is very When receiver sensitivity is an important consideration gain, especiaUy in an RF amplifier intended for the input
small. the circuit Yrs values may differ significantly from the in the design of an RF amplifier, a compromise must be stage of a receiver.
Yrs values shown in Table I and hence. may result in an made in the circuit power gain to achieve a lower noise In addition to the protection afforded in normal
unstable operating condition. It is impossible to provide data factor. A contour plot of noise figure as a function of handling, the diodes also provide in""ircuit protection against
for all possible mounting combinations. therefore, a recom· generator source admittance is shown in Fig. 4. Each contour events such as: static discharge due to contact with the
mended mounting arrangement is shown in Fig. 2. The is a plot of noise figure as a function of the generator source antenna, delay in transmit-receive switching, or connection
source and substrate in the TO·72 package of the 3N200 are conductance and susceptance. Data for the noise figure were of an antenna with an accumulated charge to the receiver.
internally connected to Icad No. 4 and the case. The obtained from a test amplifier designed with very low
source· lead inductance can be reduced. if the case is used as feedback. Even though the area of very Jow·noise figure in Croamodulltion
the source connection. Fig. 2 illustrates a partial component the curves in Fig. 4 cover a broad range of source admittance, Crossmodulation is an important consideration because
layout in which the case is held by a clamp or other fingered impedance·matching for maximum power gain could result in it is an inherent device characteristic where circuit considera-
device. The damp is soldered to a feedthrough capacitor to tions are secondary. Crossmodulation is the transfer of
provide an effective. very·low inductance bypass to RF
signals. This mounting arrangement still permits the use of a
source resistor for DC stability, and enables the case to
proVide isolation between the input and output circuit in
1". . . FREOUENCY(tI-400MHI
NT TEMPE;T\JAE~"C~SE
..! j,
'ACTO'
modulation from an undesired signal on a desired signal
caused by the non-linear characteristics of a device.
Crossmodulation is proportional to the third-order term
of the expansion of the 10 . VGS curve. It is normally
addition to the isolation afforded by the shield. ~125;~~---+~~--~-+~~--+--4--~ specified as the undesired signal voltage required to produce
~ ,f \ a crossmodulation factor of 0.01. The crossmodulation
L:
i ,~
(/':~r-.
\ (( (~. ))
\
II
/
factor is defined as the percent modulation on a desired
carrier by the modulated undesired signal divided by the
percent modulation of the undesired signal.4
Inspection of the 10 . VGIS curve of Fig. 5 offers an
~ i'--l"-..:,"4-/~ V / insight to the possible crossmodulation as a function of
i 2.5 ... gain-reduction performance. When both channels of the
3N200 are fully conducting current, as shown by the VG2S =
4-volt curve, the device approximately follows a square-law
_0•.1,.•.,,-,-_-!o20~_I*,,,,--_L."'--'-I+..,--J,'0"'-_+7.-:-.--+.---!-2.~.-:!0 characteristic. If the ID - VG IS curve was ideal, the
[Link] SOUf'CE SUSCEPTANCE Ibi,)-1IIItItIo
third-order term would be zero; but in practical cases. the
TOP VIE.
" Fig. 4 - Noise factor w. generator source (input) IIdmitt/InCII third-order term and crossmodulation have some low mue•.
(Yis)
AMBIENT TEMPERA1\IRECTA)-U-C
DRAIN-TO-SOUftCE VOLTS IVDSJ-t5
a relatively poor noise figure. As shown in Table 2, the input •
SHIELD conductance (gis) with the case grounded is 2.5 mmho. With
• if . / ~
,""NG~
the reactive portion tuned out, the noise factor at power ,i,
matched conditions is almost I dB higher than the optimum
1,7
--
CAPACITOR C2 CLAMP
noise figure. However. matching to 5.0 mmho results
FEEOTHROUGH
°
CAPACIT"OR C7 in a near optimum noise factor with a loss of only 0.5 dB in
gain. In addition, impedance matching to high conductance
also benefits c:rossmodulation performance, as will be dis-
• if
~'11/ ....
.-.l
circuit
SIDE VIEW
Fig. 2 - Partial component fayout of 400-MHz amplifiBr
cussed in a later section.
Ga.. _ I o n Dlod_
The diodes incorporated into RCA dual-gate MOS
FETs, for pte protection, have been designed to minimize
.- _~#J
~ -I 0 0.4 I
°
The reduction of source-lead inductance provides in GATE No.l-TO-SOURCE VOLTAGEIVGISI-V
addition to grealer stability, a lower input and output RF loading on the input circuits. The smaJl amount of RF
conductance. Table 2 shows the differences in 6. y" parameter loading results in ,only a fraction of a dB loss in power gain
FIg. 5 - Dnlin current (IOJ ~ ,.,. No. '-to-lOUrr::e vo".".
values at 400 MHz when measured with the source con· and a negligible increase in the noise figure. The advantages
of diode protection, greatly outweigh the slight loss in power (VGlsi
neetion made to lead No. 4 (in accordance with. the
published data for the 3N2(0) and when measured with the
case connected directly to the ground plane of the test jig. CHARACTERISTICS SYMBOL FREQUENCY (f) = 400 MHz UNITS
The magnitude of reverse transadmittance is halved with a
significant change in its phase angle. The input conductance Normal ease
is reduced by 30%, and the output conductance is reduced by Connection Grounded
13%. A recalculation of the expressions for MAG, MUG, and
Linvill Criteria (e) shows a significant improvement in gain Maximum Available Power Gain MAG 13.0 15.7 dB
and circuit stability.
While it is difficult to provide accurate information on Maximum Usable Power Gain lunneutralized) MUG 13.B 19.4 dB
the effects of shielding between the input and output
circuits, its effect can be demonstrated when aU other Linvill Stability Factor, C C 0.615 0.335 mmho
feedback components have been reduced to negligible values.
The circuit, shown in Fig. 3 (for component layout see Fig. "y" Parameters
2), was measured both with and without a shield. The
maximum gain, without the shield, averaged 0.8 dB lower Input Conductance 9is 3.6 2.5 mmho
than with the use of the shield.
Input Susceptance bis 11.2 11.7 mmho
M8{J'Iitude of Forward Transadmittance I VIs I 15.5 15.5 mmho
Angle of Forward Transadmittance ills -47.0 ·40.0 degrees
Output Conductance !los 0.8 0.65 mmho
Output Susceptance bas 4.25 4.25 mmho
Magnitude of Reverse Transadmittance I V" I 0.14 0.07 mmho
Angle of Reverse Transadmittance ftrs 14.0 49.0 degrees
Table 2 - ••y •• Parameters at 400 MHz with source connection 10 lead No.4 and with ca.. connected to ground plane
Fig. 3 - 400-MHz ampfifier circuit of_jig
------------------------------------------~-------------------------~
ICAN-8048
Some Applications of a Programmable
Power/Switch Amplifier
by L. R. Campbell and H. A. Wittlinger
The RCA-CA3094 unique monolithic programmable power The CA3094 series of circuits consists of six types that dif· ,----~rrr---- 8.4 V
switch/amplifier Ie consists of a high-gain preamplifier driving fer only in voltage-handling capability and package options, as
a power-output amplifier stage. It can deliver average power 01 shown belOW; other electrical characteristics are identical.
3 watts or peak power of 10 watts to an external load. and
I'1IckageOption. Maximum Voltage Rating
can be operated from either a single or dual power supply.
This Note brieHy describes the characteristics of the CA3094. CA3094S; CA3094T 24 V
and illustrates its use in the following circuit applications: CA3094AS; CAJ094AT 36V
Class A instrumentations and power amplifiers
CA3094BS; CA3094BT 44V
The suffIX "S" indicates circuits packaged in TO-S enclosures
1
OUTPUT
I VOLT
Class A driver-amplifier for complementary power tran· with leads formed to an 8-lead dual·in-line configuration (0.1" FULL
sistors SCALE
Wide-frequency-range power multivibrators
pin spacing). The suffix "T" indicates circuits packaged in 8-
lead TO-S enclosures with straight leads. The generic CA3094 __I
Current· or voltage-controlled oscillators type designation is used throughout this Note.
Cia. A Innrumentatlon Amplifiers Fig,3-Single-supply dif'-'sntisl-brjdge lImplifisr.
Comparators (threshold detectors)
One of the more difficult instrumentation problems fre-
Voltage regulators quently encountered is the conversion of a differential input
,--~""T~~---_+12V
Analog timers (long time delays) signal to a single-ended output signal. Although this conver-
A1arm systems sion can be accomplished in a straightforward design through
the use of classical op-amps, the stringent matching require-
Motor-speed controllers ments of resistor ratios in feedback networks make the can-
Thyristor-firing circuits [Link] particularly difficult from a practical standpOint.
Battery·charger regulator circuits Because the gain of the preamplifier section in the CA3094 >,®~--.YOUT
can be defined as the product of the transconductance
Ground-fault-interrupter circuits and the load resistance (gm Rl). feedback is not needed to THERMO-
COUPLE
Circuit Description obtain predictable open·loop gain performance. Fig. 2 shows
The CA3094 series of devices offers a unique combination the CA3094 in this basic type of circuit.
of circuit flexibility and power-handling capability. Although M ~~VM:ROM
THERMOCOUPLE
these monolithic IC's dissipate only a few microwatts when 100KO PRODUCES
ZERO A~J.
FULL-SCALE
t---'VI/Ir-~ OUTPUT
quiescent, they have a high current-output capability (100 CURRENT
milliamperes average, 300 milliamperes peak) in the active
state. and the premium-grade devices can operate at supply
.,%
100 A
voltages up to 44 volts. 1201(
Fig. I shows a schematic diagram of the CA3094. The por-
tion of the circuit preceding transistors 012 and 013 is the
preamplifier section and is generically similar to that of
the RCA-CA3080 Operational Transconductance Amplifier NO"TES: -30 V
.zcs-zozeo
(OTA).I,2 The CA3094 circuits can be gain-programmed by PRE-AMP. GAIN IAyl. ~m RL _151110- 3) (;5&1 (lOll_ISO Fig,f-5in;fI-SUpply smp/lli.,. "" thllrtnOCOUplfl'ifnfIh.
(OUTPUT AT TERMINAL J I
either digital and/or analog signals applied to a separate
I~I~~I:~::O~~ATION: DIFFERENTIAL INPUT::!I :!:26 mVj "'ass A _ Ampllfi. .
Amplifier-Bias-Current (lAscl terminal (No.5 in Fig. I) to
DEVIATION FROM The CA3094 is attractive for power-amplifier service be·
control circuit sensitivity. Response of the amplifier is es- LlNEARI"TV)
cause the output transistor can control current up to 100
sentially linear as a function uf the current at terminalS. OUTPUT VOLTAGE (EO"AV thditfl' 1180111:26 mVI- 1:4.7 V milliamperes (300 milliamperes peak). the premium devices
This additiunal signal input "purt" provides added fleXibility OU"TPUT CURRENT, IO"~ • 8.35 mA
.The components of the RC network are chosen so that
in many applications. Thus, the uutput of the amplifier is a
10" (9,"RL~~' dlftl
function of input signals applied differentially at terminals :! 2W~C "'2MH•.
and 3 and/ur in a single-ended configuration at terminal 5. The Fig.2-0pen-loop instrultl§ntafion amplifier with [Link]
output portion of the monolithic circuit in the CA3094 cun- input and single·ended output.
sists of a Darlington-connel.:ted transistur pair with al.:cess pro- (CA30948) can operate at supply voltages up to 44 volts, and
The gain of the preamplifier section (to terminal No. I) is
vided to hoth the collectur and emitter terminals to provide the TO-S package can dissipate power up to 1.6 watts when
capability to "sink"' and/ur "source" current. 8m RL = (5 x 10-3 ) (36 x 103~ = 180. The transcon· equipped with a suitable heat sink that limits the case temper-
ductance 8m is a function of the current into terminal No.5,
alUre to 55°C.
IABC, the amplifier-bias<urrent. In this circuit an IABC of
Fig. 5 shows a Class A amplifier cirl.:uit using the C A3094A
260 microamperes results in a 8m of 5 millimhos. The oper-
that is capable of delivering 280 milliwatts to a 350-ohm re·
ating point of the output stage is controlled by the 2-kilohm
sistive load. This circuit has a voltage gain of 60 dB and a
potentiometer. With no differential input signal (ediff = 0),
this potentiometer is adjusted to obtain a quiescent output (.,
10ICQ +I!;y
current 10 of 12 milliamperes. This output current is estab·
lished by the 560-ohm emitter resistor, RE' as follows:
(g",RIJ (ediff)
10'" RE
VOU"T
Under the conditions described, an input swing ediff of 126
millivolts produces a variation in the output current 10 of
±8.3S milliamperes. The nominal quiescent output voltage is
12 milliamperes times 560 ohms or 6.7 volts. This output
level drifts approximately -4 millivolts, or -0.0595 per cent,
for each °c change in temperature. Output drift is caused by
temperature-induced variations in the base-emitter voltage of
the two output transistors, Q12 and 013.
Fig.5-CIsss·A amplifier - 280·mWcapability into II
Fig. 3 shows the CA3094 used in conjunction with a re-
resistiveiDad.
sistive-bridge input network; and Fig. 4 shows a single-supply
J-d8 bandwidth of .. bout 50 kHz. Operation IS stable without
amplifier for thermocouple signals. The RC networks· con- the use of a phase-compensatiun network. Potentiometer R is
nected between termina1s I and 4 in Figs. 3 and 4 provide used tu establish the quiescent operating point for class A
Fig. ,-CA3094 circuit $Chf1(J1lJtic [Link]. compensation to ilssure stable operation. operation.
___________________________________________________________________ 487
ICAN-6048
excess of 10 watts when used in this Iype of circuit. The fre· ,-----.,....-~- +ISV
quency of oscillation fose is determined by the resistor
ratios. as follows:
'TKO
rose = 2RCIn 1(2 R 1/R2) + I]
RARS 8OUTP~
where
RI = RA + RS
47KO
Provisions can easily be made in the circuit of Fig. J I to
vary the multivibrator pulse length while maintaining an es-
sentially constant pulse repetition rate. The circuit shown in
Fig. I:! incorporates a potentiometer Rp for varying the
width of pulses generated by the astable mullivibrator to drive
a Iight-emitting diode (LED).
IJPPER THR£SHOlD = v+
+30V ,-~----'-(l!5Vl
2m. 300lUl
Fig. 15-Current· or voltage-controll6d oscillawr.
H[~.l
OUTPUT
!t2CS-20408
Fig. 12-Astable power mullilfibrator with prolfisions for
varying duty cycle.
Fig. 13 shows a dn:uit incorporating independent controls Ut' SINGLE SUPPLY
(RoN and RoFF) to establish the "on" and "orr' periods of Fig. 18-ConlpllnltoTS (thrnhold detttctor.J - dual- MId singJ...upply
the current supplied to the LED. The network between points ry"".
"A" and "0" is analogous in function to that of the 100-
kilohm resistor R in Fig. I:!. Fig. 19 shows a dual-limit threshold detec.:lor dn.:ui! ill
+30V
AMPLIFIER BIAS which the high-level limit is established by potentiometer R I
Fig. '6-Frequency ss a function of I ABC for C-IDOO pF
lOOK4 Sl04 for circuit in Fig. 15.
471C{& "A- IN914
ate resistor (R) in series with terminalS in Fig. 15 converts the -15 V -W\~'{\r-'V'(Ir---
circuit into a voltage-controlled oscillator. Linearity with re-
spect to either current or voltage control is within I per cent INPUT ~-r-I-""",,,,'-'-'-+@-i
over the middle half of the characteristics. However, variation
in the symmetry of the output pulses as a function of fre-
OUTPUT
quency is an inherent characteristic of the circuit in Fig. 15,
and leads to distortion when this circuit is used to drive the -}--H1GH
DEAD
[Link]
ZONE
phase detector in phase-locked.!oop applications. This type of --LOW
distortion can be eliminated by interposing an appropriate
92CS-20151515 flip-flop between the output of the oscillator and the phase-
Fig. t3-Astable power multivibrator With provisions for locked discriminator circuits.
independent control of LED "on-o"" pttriods.
The C A3094 is also suitable for use in monostable multi-
vibrators, as shown in Fig. 14_ In essence, this circuit is a pulse
counter in which the duration of the output pulses is inde- Fig. 1S-0us,-limit threshold detector.
pendent of trigger-pulse duration. The meter reading is a fune- and the low-level limit is set by potentiometer R2 to actuate
lion of the pulse repetition rate which can be monitored with the (' A3080 [Link] detector.' ,2 A positive output signal is
the speaker. delivered by the C A3094 whenever the input signal exceeds
either the high-limit or the low-limit values established by the
appropriate potentiometer settings. This output voltage is ap·
proximately 12 volts with the circuit shown.
The high current-handling caP'1bility of the e A3094 makes
it useful in Schmitt power-trigger drc.:uits such as that shown
in Fig. 20. In this circuit. a relay coil is switched whenever the
100 •
100 200 300 400
AMPLIFIER BIAS CURRENT (rABel-IlA
500
'ZCS-ZOU4
2.7MQ loon
IZV
....,
Fig. l1-FAlquency 88 II function of I ABC for C-1tJO pF
~n IOOpF for circuit in Fig_ 15. INPUT
,r_=,I4--...J
JM'UT • FULL _ SCALE DEfLECTION _ " PULSESIS!,':C Comparator. IThreshoid Detectors)
Fig. 14-Power tnOnostllble multivibrstor. Comparator circuits are easily implemented with the
CA3094, as shown by the circuits in Fig. 18. The circuit of
Current- or Voitaga-Convolled Oscillaton Fig. 18(a) is arranged for dual-supply operation; the input volt-
Because the transconductance of the CAJ094 varies lin- age exceeds the positive threshold, the output voltage swings
early as a function of the amplifier bias current (IABC) sup- essentially to the negative supply-voltage rail (it is assumed 100KA
plied to terminal 5, the design of a current- or voltage-con- that there is negligible resistive loading on the output ter-
trolled oscillator is straightforward, as shown in Fig. 15. UPPER TRIP POINT-3D ~
minal). An input voltage that exceeds the negative threshold R I+R 2 +R 3
Fig. 16 and 17 show oscillator frequency as a function of value results in a positive voltage output essentially equal to
LOWE" TRIP POINT.'30-0.026'YR::R3
IABC for a current-controlled oscillator for two different the positive supply voltage. The circuit in Fig. 18(b), con-
values of capacitor C in Fig. 15. The addition of an appropri- nected for single-supply operation, functions similarly. Fig.20-PrllCision Schmitt powar-trigger circuit.
___________________________________________________________________ 489
ICAN-6048
Alarm Circuit mined by the proportionaJ bandwidth control to establish the When the temperature is "low", the resistance of the PTC~type
Fig. 25 shows an alarm circuit utilizing two "sensor" error-correction response time. sensor is also low; therefore, tenninal 3 is more positive than
lines. In the "no~alarm" state, the potential at tenninal 2 is terminaJ 2 and an output current from tenninal 6 of the
lower than the potential at terminal 3, and terminal 5 (I ABC) CA3094 drives the triac into conduction. When the tempera-
is driven with sufficient current through resistor R5 to keep ture is "high", the input conditions are reversed and the triac
the output voltage "high". If either "sensor" line is opened, is cut off. Feedback from terminaJ 8 provides hysteresis to the
shorted to ground, or shorted to the other sensor line, the
output goes "low" and activates some type of alarm system ..
The back·tu·back diodes .:onne':led between terminals :! and 3
protect the CA.1094 input terminals against ex.:essive differen·
tial voltages.
it:
RECTIFIED AND FILTERED
EOUT
TO PHASE
COMPARATOR
(al VOLTAGE COMPARATOR
control point to prevent rapid cycling of the system. The
1.5-kilohm resistor between tenninal 8 and the positive supply
limits the triac gate current and develops the voltage for the
hysteresis feedback. The excellent power-supp1y~rejection and
common-mode-rejection ratios of the CA3094 permit accurate
SIGNAL DERIVED FROM
TACHOMETER DRIVEN 8'1'
repeatability of control despite appreciable power-supply rip~
NDTOR8E1NG CONTROLLED pie. The circuit of Fig. 29 is equally suitable for use with
NrC (negative-temperature-coefficient) sensors provided the
positions of the sensor and the associated resistor R are inter-
changed in the circuit. The diodes connected back-to~back
'0
100lU1 across the input terminals of the CA3094 protect the device
against excessive differential input signals.
Thyristor Control from AC·Bridga SenIOr. Fig. 30 shows a
q~C5· 2027&
Fig. 27-Motor IpeIId error detflCtor. line-operated thyristor-firing circuit controlled by a CAJ094
Synchronous Ramp Generator. Fig. 28 shows a schematic that operates from an ac-bridge sensor. This circuit is particu~
"
5101Ctl.
diagram and signal waveforms for a synchronous ramp gener-
ator suitable for use with the motor-controller circuit of
larly suited to certain classes of sensors that cannot be oper-
ated from dc. The CAJ094 is inoperative when the high side of
Fig. 26. Terminal 3 is biased at approximately +2.7 volts the ac line is negative because there is no IABC supply to
(above the negative supply voltage). The input signal EIN at terminal 5. When the sensor bridge is unbalanced so that
terminal 2 is a sample of the half-sinusoi4s (at line frequency) terminal 2 is more positive than terminal 3, the output stage of
Fig.25-Alarm system.
used to power the motor in Fig. 26. A synchronous ramp sig- the CAJ094 is cut off when the ac line swings positive,and the
Motor·Speed Controller System output level at terminal 8 of the CA3094 goes ''[Link]''. Cur-
naJ is produced by using the CA3094 to charge and discharge
Fig. 26 illustrates the use of the CA3094 in a motor·speed rent from the line flows through the lN3193 diode to charge
controller system. Circuitry associated with rectifiers D, and capacitor CI in response to the synchronous toggling of EIN'
the loo-microfarad reservoir capacitor, and also provides cur~
D:! comprises a full·wave rectifier which develops a train of .IOV rent to drive the triac into conduction. oUring the succeeding
half·sinusoid voltage pulses to power the dc motor. The motor negative swing of the ac line, there is sufficient remanent en~
speed depends· on the peak value of the half-sinusoids and the ergy in the reservoir capacitor to maintain conduction in the
period of time (during each half.·cyde) the SCR is conductive. 'IN
triac.
(+)
,., -~y
.~. r\. r\. /"\ BIAS LEVEL AT
~~~_-~__-~_-'!!-..RMINAL NO.3
,.,
~
CI DISCHARGING (RAMP)
CI CHARGING
'OUT
(0) ---------(b)---- 92.C$-20n4
Fill.28-5ynchronous 'limp 1/M.,lItor with input and output
WlIveforms.
92CS-204'l
Fig.30-Line-operated thyristor·firing circuit controlled by
The charging current for C I is supplied by terminal 6. When
ac-bridge sensor.
terminal 2 swings more positive than terminal 3, transistoC!)
012 and Q13 in the CA3094 (Fig. I) lose their base drive and
The SCR conduction, in turn, is controlled by the time dura~ become non-conductive. Under these conditions, C I discharges When the bridge is unbalanced in the opposite direction so
tion of the positive signal supplied to the SCR by the phase linearly through the external diode D3 and the QIO' D6 path that terminal 3 is more positive than terminal 2. the output of
comparator. The magnitude of the positive dc voltage sup~ in the CA3094 to produce the ramp wave. The Eout signal is the C A3094 at terminal 8 is driven sufficiently "low" to
plied to terminal 3 of the phase comparator depends on suppJied to the phase comparator in Fig. 26. "sink" the current supplied through the IN3193 diode so
motor-speed error as detected by a circuit such as that shown that the triac gate cannot be triggered. Resistor Rl supplies
in Fig. 27. This dc voltage is compared to that of a fixed-am- Thyristor Firing Circuits the hysteresis feedback to prevent rapid cycling between turn~
plitude ramp wave generated synchronously with the ac-line~ on and turn-off.
Tamperature Controller. In the temperature control system
voltage frequency. The comparator output at terminal 6 is shown in Fig. 29, the differential input of the CA3094 is con~ Battery~Charger Regulator Circuit
"high" (to trigger the SCR into conduction) during the period nected aclOss a bridge circuit comprised of a PTC (positive. The circuit for a battery-charger regulator circuit using the
when the ramp potential is less than that of the error voltage temperature-coefficient) temperature sensor, two 7S..Jciiohm CAJ094 is shown in Fig. J I. This circuit accurately limits the
on terminal 3. The motor<urrent conduction period is in- resistors, and an aIm containing the temperature set control. peak output voltage to 14 volts, as established by the zener
creased as the error voltage at terminal 3 is increased in the
positive direction. Motor~speed accuracy of ±l per cent is
easily obtained with this system.
1N914
Motor-5peed Error Detector. Fig. 27(a) shows a motor-
speed error detector suitable for use with the circuit of Fig. 26.
A CA3080 operational transconductance amplifier is used as a
voltage comparator. The reference for the comparator is es-
tablished by setting the potentiometer R so that the voltage
at terminal 3 is more positive than that at terminal 2 when the
motor speed is too low. An error voltage E I is derived from a
tachometer driven by the motor. When the motor speed is too
low, the voltage at terminal 2 of the voltage comparator is
less positive than that at terminal 3, and the output voltage at
terminal 6 goes "high". When the motor speed is too high, the
opposite input conditions exist, and the output voltage at ter-
minal6 goes ·~low". Fig. 21(b) also shows these conditions graph.
ically, with a linear transition region between the "high" and
"low" output levels. This linear transition region is known as
"proportional bandwidth". The slope of this region is deter- Fi9.29- Temperature controller. SEC .. lOato
- - - - - - - - - - - - - - - - - - - - - - - - - - - - - -__________________________ ~1
ICAN-6077
An Ie Operational-Transconductance-Amplifier The actual perfonnance of the circuit shown in Fig. 4 is
plotted in Fig. S. Both signaI-to-noise ratio and total
(OTA) With Power Capability hannonic distortion are shown as a function of signal input.
Figs. S(b) and (0) show how the signal-handling capability of
'by L. Kaplan and H. Wittlinger
the circuit is extended through the connection of diodes on
In 1969, RCA introduced the first triple operational.
transconductance-amplifier or OTA. The wide acceptance of
this new circuit concept prompted the development of the
single, highly linear [Link].
the CA3080. Because of its extremely linear transconduct-
ance characteristics with respect to amplifier bias current, the
i
'8 0.4
CA3080 gained wide acceptance as a gain-control block. The t. 0.2
Si~
CA3094 improved on the performance of the CA3080
through the addition of a pair of transistors; these transistors ~i 0
extended the current·carrying capability to 300 milliamperes,
u=: -0.2
peak. This new device. the CA3094. is useful in an extremely
lin
~ -0.4
broad range of circuits in consumer and industrial
applications; this paper describes only a few of the many
consumer applications.
WHAT IS AN OTA?
The OT A, opera tional-transconductance-amplifier, con-
I -~·.b-Lh-L±-...L+-L-k....l:~;-I---';;--'
6V8E-MILLIVOLTS
0.111'1\1 1.011'1\1
INPUT VOLTAGE
100",\1
(a)
cept is as basic as the transistor; once understood, it will Fig. 3- The outpUt-current tranIfer-chanlcttlristic of the 1
broaden the designer's horizons to new boundaries and make
realizable designs that were previously unobtainable. Fig. I
OTA is the ssme .. thar of an idftlized differential
amp/ifitN_ 6
1111 I II
shows an equivalent diagram of ~the OTA. The differential
input circuit is the same as that found on many modern differential amplifier, i.e., a circuit in which differential input , DIODE CUAAENT-O.' ",A
100
~ ~~ 'ABC
operational amplifiers. The remainder of the OTA is to sinale-ended output conversion can be realized. With this ~
composed of current mirrors as shown in Fig. 2. The knowledge of the basics of the OTA, it is possible to explore u 4 1-- -- CA:S080A
SIN RATIO .0 0
geometry of these mirrors is such that the current gain is
unity. Thus, by highly degenerating the current mirrors, the
some of the applications of the device. ~
3 60
i
"';:::
0
~
output current is precisely defined by the differential·input
amplifier. Fig. 3 shows the output-current transfer-character-
DC Gain Control
The methods of providing dc gain-control functions are
, 40
istic of the amplifier. The shape of this characteristic remains numerous. Each has its advantage - simplicity,low cost. high THD
I
level control, low distortion. Many manufacturers who have '0
nothing better to offer propose the use ·of a four-quadrant
multiplier. This is analogous to using an elephant to carry a
0 I--" 0
twig. It may be elegant but it takes a lot to keep it going! 101llV IOO",y
OTA
INPUT VOLTAGE
When operated in the gain-control mode, one input of the
/ standard transconductance multiplier is offset so that only
(b)
1
-Hi! J~fNHL
one half of the differential input is used; thus, one-half of the
1--'~---~---1D--Io"'l-g"'l!e'nl multiplier is being thrown away. 6 -
'R. The orA, while providing excellent linear amplifier
gill- 192' 1 ABC
characteristics. does provide a simple means of gain control. 'r---- I-- - 100
~
lm",holl
Ro
irnttOh"'I'
I",A)
~ " / IABC
C",AI
For this application the OTA may be considered the
realization of the ideal differential amplifier in which the full
differential amplifier gm is converted to a single-ended
.
~
~ 4 -I--
P-~
oa:$.: ~CA:S080
fA.e AOO
IN RATO
60
0
i
!Aac output. Because the differential amplifier is ideal. its gm is 3
tIoUT- I:ABe
~
.....)(
{mAl
'mAl directly proportional to the operating current of the
differential-amplifier; in the OTA the maximum output
, v~
I-'"
I 40
'THO
current is equal to the amplifier bias current IABC. Thus. by
~ IUlfl~11~I~mI:l
Fig. 1- Equivalent diagram of the OTA. varying the amplifier bias current. the amplifier gain may be '"'
varied: A = Gm RL where RL is the output load resistance.
Fig.4 shows the basic confIguration of the OTA dc
A
I 0
10",Y 100",Y 10V
v· gain-control circuit. I INPUT VOLTAGE
As long as the differential input signal to the OT A (0)
remains under SO-millivolts peak-to..peak, the deviation from Fig. 5- Perlormsnce CUfYf!S for the circuits of Figs. 4 and 6.
a linear transfer will remain under 5 percent. Of course. the
total harmonic distortion will be considerably less than this the input as shown in Fig. 6. 2 Fig. 7 shows total system gain
value. Signal excursions beyond this point only result in an as a function of amplifier bias current for several values of
undesired "compressed" output. The reason for this diode current. Fig. 8 shows an oscilloscope photograph of
compression can be seen in the transfer characteristic of the the CA3080 transfer characteristic as applied to the circuit of
differential amplifier in Fig. 3. Also shown in Fig. 3 is a curve Fig. 4. The oscilloscope photograph of Fig. 9 was obtained
depicting the departure from a linear line of this transfer with the circuit shown in Fig. 6. Note the improvement in
characteristic.
'IN
Fig. 2- Current mirrors W, X, Y. and Z used in the OTA.
constant and is independent of supply voltage. Only the
maximum current is modified by the bias current.
TRANSISTORS
The major controlling factor in the OTA is the input FROM CA3046
ARRAV
amplifier bias current lASe; as explained in Fig. I, the total
AGe SYSTEM
output current and gm are controUed by this current. In WITH EXTENDED
INPUT RANGE
addition, the input bias current, input resistance, total supply CON;:'~ ( i ) - - - - - - - - '
current, and output resistance are all proportional to this Fig. 6- A circuit showing how the signa/·handling
amplifier bias current. These factors provide the key to the Fig. 4- Basic configuration of the OTA de fI/Iin-control capabilitv of the circuit of Fig. 4 can be extended
performance of this most flexible device, an idealized circuit. through the connection of diodes on the input.
_________________________________________________________________________________________________________________________________________ 493
ICAN-8077
' ..
_ . - - '990 AT t.4-'X VOL.
En 403 IO-~
En'O!imVAT MIN VOL
En '4mV AT MIN VOL
Fig. 13- A system in which tone controls aTe implicit in the feedback circuit of the
Fig. 12- Block diagnJm of a system using a "'OSSBr"·type tone-control circuit.
power amp/ifier.
C,O ·7
820
.,
.0fo.12 CW
.,
Co . .00
220
0.001 IW
C,
'so-! ·L
lUll
10 4 6 8 10 1 f> a,r;;
.,
FREQUENCY -H,
Fig. 16- The mtMSUrtld responIB of the amp/ifier at extremll1J of tone-control rotation.
1.8 M
[Link]--,---r--,r--,----,------.c-.:::-o
~!
1II
[Link]--+--+-----1f--+---+----IH:-:---l
. ··
o.• f---+--+---'I----1---+--III+..--1
N
Z
N
Z
JUMPER
Fig. 14- A complete POWfH' ampli'i. using the CA3094 and thrwadditional trlmistofS.
~
0.7f--+--+--f--+---+--t1It----l ·i
~
ro.• f--+--+--f--+---+--t1f----l
'20'
'~~:~;~~~~---it, ~ 0.11---+--+--1---+--+--1-11----1
~
~
~ O.4f--+--+--f--+---+--trf--'
Ffl
u
';OO.' '''' "L" ~ o.f--+--+--f--+---+--iHf----l
:=[Link]---+--+--I---+--+--hl----I
07 ~
1''''tl1 _ _ ~
••7 •. ,1---+--+==,".H-Z~='F.:.,.::.~.t~~~I----I
,.
2201(
. ".",~
10 12
POWER OUTPUT - WATTS
Fig. 17- Total harmonic distortion of the amp/ifier with an
Fig. 15- A po_ omp/ifitw _ated from alinglo wpp/y. unrtlfJUlated power supply.
network include. R3, R4, RS. C4. and CS. C6 block. the de when there are tape recorders nearby. The cut limit aids the complete amplifier at the extremes of tone·control rotation.
from the feedback network so that the de gain from input to stability of the amplifier by cutting the loop gain at higher A comparison of Fig. 16 with the L'Omputed curves of
the feedback takeoff point is unity. The residual dc-output- frequencies where phase shifts become significant. Fig. 84 (Appendix B) shows good agreement. The total
In cases in which absolute stability under all load harmonic distortion of the amplifier with an unregulated
RII + RI2 conditions is required. it may be necessary to insert a small
voltage at the speaker terminals is then IABC Rt ~ power supply is shown in Fig. 17; 1M distortion is plotted in
inductor in the output lead to isolate the circuit from Fig. 18. Uum and noise are typically 700 microvolts at the
where Rl is the source resistance. The input bias current is capacitive loads. A 3-microhenry inductor (I ampere) in output. or 83·dB down.
IABC (Vcc - Vbe) parallel with a 22-ohm resistor is adequate. The derivation of
then ~ = -~. The treble network consists of
circuit constants is shown in Appendix B. Curves of control COMPANION RIAA PREAMPLIFIER
R7, R8, R9, RIO, C7, C8, C9, and CIO, Resistors R7 and R9 action versus electrical rotation are also given. Many available preamplifiers are capable of providing the
limit the maximum available cut and boost. respectively. The drive for the power amplifier or Fig. 14. Yet the unique
boost limit is useful in curtailing heating due to finite Performance characteristics of the amplifier its ..ower supply. input
turn-off time in the output units. The limit is also desirable Fig. 16 is a plot of the measured response of the impedance. and gain .- make possible the design of an RIAA
---------------------------------------------------------------------~
ICAN-6077
c,
c,
'0 '0
'0
(ol BASS BOOST AlOWfREO~~
'.
leI TREBLE BOOST (d) TREBLE CUT
ItilBASSCUT
Fig. S1- Four operational-amplifier circuit configurations and the gain expressions for each.
R3 CCW
BASS CONTROL
'"
TREBLE CONTROL
'" Fig. 83- A plot of the response of the circuit of Fig. 14 with /:;;;~ ::too treble tone
Fig. B2- Cut and boost bass and treble controls that have the
characteristics of the circuits of Fig. 81, controls combined at various settings of both controls.
, 91·percent of its total resistance. The amplitude response
of the treble control is, however. never completely "flat";
0 0 a computer was used to generate response curves as
controls were varied.
Fig. B3 is a plot of the response with bass and treble
tone controls combined at various settings of both con-
, • trols. The values shown are the practical ones used in the
actual design. Fig. 84 shows the information of Fig. 83
replotted as a function of electrical rotation. The ideal
50
taper for each control would be the complement of the
IOO-Hz plot for the bass control and the 10·kHz response
, • for the treble control. The mechanical center should
0f-
1000 HZ
t 0 1KHZ l1
occur at the crossover point in each case.
k:;;"'"~
V h¢ f....-- V
V k::::: ~
",0
I. "Applications of the CAJ080 and CA3080A High·
/' Performance Operational Transconductance Ampli-
'I
0 ./
~ '!.\,fI
':/1
0;/
fiers," H. A. Wittlil1ger, RCA Application Note leAN-
6668
2. "A New Wide-band Amplifier Technique," B. Gilbert,
1
/
V IEEE Journal of Solid State Circuits, Vol. SC·3, No.
4, December, 1968.
,/ • 3. "Trackability," James A. Kogar, Audio, December
V 1966
4. RCA Linear Integrated Circuits Manual, RCA Tech·
4 ..
ELECTRICAL ROTATION Of BASS CONTROL
.7 ,.0 .2
ELECTRICAL ROTATIOfli OF TRULE CONTROL
nical Series IC42
*RCA publications available through RCA Solid State
Fig. 84- The information of Fig. 83 plotted as a function of electrical rotation. Division, Box 3200, Somerville, N.J., 08876.
_____________________________________________________________________ 497
ICAN-6157
teristics for various values of RSC are shown in Fig. 4. tor across the output voltage terminals. The addition of a
capacitor will, however, degrade the ability of the system to
react to transient-load conditions. '
,.J
(a) With simplified short-circuit protection
LOAD CURRENT n'LI-IIIA
FREOUENCT tfl-IIHt
Fig. 4- LtHId ,.,u/lltlon chllnlt:tllriltic. for circuit of Fig. 3.
Fif}. 8- Output f'[Link] VI. frequency for c;ff:uit of Fig. 1.
When this circuit is used to provide high output currents at
low output voltages, care must be exercised to avoid 'excessive IbJ
Hiltl-Voltage Regulator
IC dissipation. In the circuit of Fig. 3, this dissipation control (bJ with auxiliary short-circuit protfJCtion
Fig. 9 shows a circuit that uses the CAJ085 as a voltage-
can be accomplished by increasing the primary-to-secondary reference and regulator control device for high-voltage power
Fig. 6- High·current voltage regulatoT using n-p-n pass transistor.
transformer ratio (a reduction in VIror by using a dropping supplies in which the voltages to be regulated are weD above
resistor between the rectifier and the CA3085 regulator. Fig. 5 viously. It should be noted that the degree of short-circuit pro· the input-voltage ratings of the CA308S-series circuits. The ex-
gives data on dissipation limitation (VI-VO ¥s. 10) for CA3085· tection depends un the value of RSCp. i.e., design compromise ternal transistors QI and Q2 reqUire voltage ratings in excess of
series circuits. is required in choosing the value of RSCp to provide the de- the maximum input voltage to be regulated. Series·pass tran-
The short-circuit current is determined as foDows: sired base drive for the 2N5497 while maintaining the desired sistor Q2 is controlled by the collector current of QI, which in
short-drcuit protettion. Fig. 6(b) shows an alternate circuit in turn is controlled by the nonnally regulated current output
VBE 0.7 whkh an addttionallranSIStor (2N5183) and two resistors have supplied by the CA3085. The input voltage for the CA3085
ISC =RSC -RSC amperes (2)
been added as an auxiliary short-circuit protection feature. Re·
sistor R3 is used to establish the desired base drive for the
:!N5497. as described above. Resistor Rlimit now I.:ontrols the
short-circuit output current because, in the event of a short-
dn.:uil. the voltage drop developed across its terminals increases
sufficiently to increase the base drive to the 2N5183 transistor.
This inl.:rease in base drive results in reduced output from the
C AJOHS because collector current flow in the 2NS 183 diverts V,
UNREG
base drive from the Darlington output stage of the CA3085 "'.[Link]
(see Fig. 2) through terminal 7. The load regulation of this cir·
cuit is typically 0.025 per cent with 0 to 3·ampere load-current
variation;lineregulation is typically 0.025 per cent/volt change
in input voltage.
Voltage Regulator with Low VI-VO Difference
In the voltage regulators described in the previous section, it
is necessary to maintain a minimum difference of about 4 volts
F;g. 9- Hiflt·voItlItIfI f1J([Link].
60 ao 100
between the input and output voltages. In some applications
OUTPUT MILLJAMPERES t10l this requirement is prohibitive. The circuit shown in Fig. 7 can regulator at terminal 3 is supplied through dropping resistor R3
deliver an output current in the order of 2 amperes with a and the clamping zener diode DI. The values for resistor RI
VI-VO difference of only one volt. and R2 are determined in accordance with Eq. (I).
Fig. 5- Dissiplltion #[Link] (VI - Vo n. 101 for CA3085If1ri..
h employs a single external p-n-p transistor having its base
c;rcu;u. Negative-Voltage Regulator
and emitter connected to terminals 2 and 3, respectively, of the The CA3085 is used as a negative-supply voltage regulator
CA3085. I.n this circuit, the emitter of the output transistor in the circuit shown in Fig. 10. Transistor Q3 is the series-pass
(Q14 in Fig. 2) in the CA308S is returned to the negative sup-
The line- and load-regulation characteristics for the circuit transistor. It should be noted that the CAJ085 is effectively
ply rail through an external resistor (RSCp) and two series- tonnected across the load-side of the regulated system.
shown in Fig. 3 are approximately 0.05 per cent of the output connected diodes (01, D2). These forward-biased diodes main-
voltage. Diode DJ is used initially in a "circuit-starter" function; tran-
tain Q6 in the CA3085 within linear-mode operation. The sistor Q2 "latches" Dl out of its starter-circuit function so that
the CA3085 can assume its role in controlling the pass-
High-Current Voltage Regulator transistor Q3 by means of Q I.
When regulated voltages at currents greater than 100 milli-
amperes are required, the CAJOS5 can be used in conjunction
with an external n-p-n pass-transistor as shown in the circuits
UNREG REG.
of Fig. 6. In these circuits the output current available from the V, Vo
regulator is increased in accordance with the hFE of the ex-
ternal n-p-n pass-transistor. Output currents up to 8 amperes
can be regulated with these circuits. A Darlington power tran-
sistor can be substituted for the 2N5497 transistor when CUr- REG
rents greater than 8 amperes are to be regulated. Vo
A simplified method of short-circuit protection is used in Fig. 1- Voltage regulator for/ow V I - Vo difference.
connection with the ciicuit of Fig. 6(a). The variable resistor choice of resistors R I and R2 is made in accordance with
RSCp serves two purposes: (I) it can be adjusted to optimize Eq. (I). Adequate frequency compensation for this circuit is
the base drive requirements (hFE) of the particular 2NS497 provided by the [Link]-microfarad capacitor connected between
transistor being used, and (2) in the event of a short-circuit in terminal 7 of the CA3085 and the negative supply rail.
the regulated output voltage the base drive current in the Fig. 8, which shows the output impedance of the circuit of
2NS497 will Increase. thereby Increasing the voltage drop Fig. 7 as a function of frequency, illustrates the excellent Fig. 10- NefIBtive-lIo1ta(/[Link].
aauss RSCp. As this voltage-drop increases the [Link] ripple-rejection characteristics of this circuit at frequencies
proteL'tion system within the CA3085 correspondingly reduces below 1 kHz. Lower output impedances at the higher fre-
the output current available at terminal 8, as dCSI;ribed pre- Operation of the circuit is as follows: current through R3
quencies can be provided by connecting an appropriate capac i-
and Dl provides base drive for QJ, which in turn provides
__________________________________________________________________ 499
ICAN-6157
Vref' the op-amp turns on QI and the cycle is repeated. It A switching-regulator circuit using the CA3085 is shown in
should be apparent that the output voltage oscillates about Fig. 18. The values of Land C (1.5 millihenries and 50 micro-
V,ef with an amplitude determined by RI and R2. Actually, farads, respectively) are commercially available components
the value of Vref varies from being slightly more positive than having values approximately equal to the computed values in
Vref' when 01 is conducting, to being slightly more negative the previous design example.
than Vref' when D I is conducting. The voltage and current
waveforms are shown in Fig. 17(b), (c), and (d).
REG.
Vo Design Example: The following specifications are used in de-
computations for a switching regulator:
VI = 30 V. Vo = 5 [Link] = 500 rnA.
switching frequency'" 20 kHz,
output rippl[Link] 100 mY.
If it is assumed that transistor QI is in steady-state saturated [Link]~F
operation with a low voltage-drop, the current in the inductor 'OY
is given by Eq. 10. as foHows: RUMIT • ~~'~L'MAXI VO' VREF (RI;IR2)
Fig. '6- High..voJtll,. rqullltor incorporllting cummt "snllp-b8ck"
protection. F;g. '8- Typiclll switch;", regullltor cin:uit.
Switching Regulator . Ift l (VI - VO\ (II)
When large input-to-output voltage differences are necessary, It =1: Vdt = -L-I-) Ion Current [Link]
to The CAJ085 series of voltage regulators can be used to pro-
the regulators described above are inefficient because they dis-
vide a constant source or sink current. A reguJated-current sup-
sipate significant power in the series-pass transistor. Under these When transistor QI is off, the current in the inductor
ply capable of delivering up to I ()() milliamperes is shown in
conditions, high-efficiency operation can be achieved by using is given by:
Fig. 19(a). The regulated load current is controlled by RI be-
a switching-type regulator of the generic type shown in
eawe the current flowing through this resistor must establish a
Fig. 17(a). Transistor 01 acts as a keyed switch and operates in (12)
voltage difference between terminals 6 and 4 that is equal to
the internal reference voltage developed between terminals 5
[Link].
and 4. The actual regulated current, reg IL. is the sum of the
quiescent regulator current and the current through RI, i.e.,
(13)
reg IL = (quiescent + IRI
If imax is 1.3 IL, then during ton the current in the inductor
(itJ will be 0.5 A • 1.3 = 0.65 A; therefore. lIiL = 0.15 A
co
Substitution in Eq. 13 yields
tol SELF-OSCILLATING SWITCHING REGULATOR L = (30 - 5), __ 1__ • 2.. = I 4 rnH 0·001
,F
I 0.15 (20.103) 30 .
(14)
Current discharge from the capacitor Cl is given by:
it =C~; (15)
Ay IIio At
Thus.1Iio = C lit . or C = -;;;;- 'oJ
CURRENT REGULATOR
Since ic =iL and 6t = toff. then
C = lIiL toff
Ay
(e) INDUCTOR CURRENT ILl
Substitution for the value of iL from Eq. 13 yields
L VI - Vq\. L. (VO\.
.EGVOE~J"E~
AYo
c= ( Ll") f vtl toff
(16)
AY
=toff + ton. and T =f.
(d) OUTPUT VOLTAGE
The total period T Therefore,
Fig. '7- Swifr:hin, regullltor IIfId IIUDCillttJd WII",fa,."".
toff=t -ton (17)
UNREG
[Link]-lo-_+-~_ _ _ _ _ --.J
HIGHeCURRENT REGULATOR 92CS-21838
either a saturated or cut-off condition to minimize dissipation. For optimum efficiency ton should be Fig. 19- Constllnt cu"ent rquillton.
When transistor QI .is conductive. diode DI is reverse-biased
and current in the inductance LI increases in accordance with
the following relationship:
'" (~~T
vd ",(~\.l VIJf
(18) Fig. 19(b) shows a high-current regulator using the CA3085 in
conjunction with an external n-p-n transistor to regulate cur-
Substitution for ton in Eq. 18 yields rents up to 3 amperes. In this circuit the quiescent regulator
current does not flow through the load and the output current
iL
tl
=4: f Vdt (10)
t
o
ff=!-(~\!.!
f Vt/ f f
(1- VO\
VI")
(19) can be directly programmed by RI. i.e.,
Vref
to
Substitution for toffin Eq. 16 yields RegIL=T!
where V is the voltage across the inductance LI. The current
through the inductance charges the capacitor C I and supplies
current to the load. The output voltage rises until it slightly ex-
C=
(VI-VO>
LI
.!..
f
VO. L
VI f
(I _ vo)
VI
With this regulator currents between I milliampere and 3
ampeIes can be programmed directly. At currents below
ceeds the reference voltage Vref' At this point the op-amp re- 1 milliampere inaccuracies may occur as a result of leakage in
fly
moves base drive to OJ and the unregulated input voltage VI is the external transistor.
"switched off'. The energy stored in the inductor LI now Substitution of numerical values in Eq. 20 produces the
A [Link]·Trlddng Voillge Regulator
causes the voltage at Vx to swing in t~e negative direction and foUowing value for C:
A dual-tracking vohage regulator using a CAJ085 and a
current flows through diode D I. while continuing to supply 30-5 I 5 I
CAJ094A* is shown in Fig. 20. The CAJ094A is baSically an
current into the load RL' As the current in the inductor falls c=~' ~'30' WxJij3' op-amp capable of supplying 100 milliamperes pf output cur-
below the load current, the capacitor CI begins to discharge
and Vodecreases. When Vofalls slightly below the value of 10- 1 63pF rent.
_____________________________________________________________ 501
ICAN-8182
Fig. 2 shows the detailed circuit diagram for the
Features and Applications of integrated-circuit zero-voltage switches. (The diagrams shown
in Figs. I and 2 "are representative of all three RCA
RCA Integrated-Circuit Zero-Voltage Switches zero-voltage switches, i.e., the CA30S8, CA30S9, and CA3079;
(CA3058, CA3059, and CA3079) the shaded areas indicate the circuitry that is not included in
the CA3079.)
The limiter stage of the zero-voltage switch clips the
by A.C.N. Sheng. G.J. Granieri. J. Yellin. and T. McNulty incoming ac line voltage to approximately ±8 volts. This signal
is then applied to the zero-voltage-crosSing detector, which
RCA-CA3058, CA3059 and CA3079 zero·voltage switches (4) Triac Gating Circuit - Provides high-current pulses to genenpes an output pulse each time the line voltage passes
are monolithic in'tegrated circuits designed primarily for use as the gate of the power-controlling thyristor. through zero. The limiter output is also applied to a rectifying
trigger circuits for thyristors in many highly diverse ae In addition, the CA30S8 and CA30S9 provide the following diode and an external capacitor, CF. that comprise the de
power~ontrol and power-switching applications. These important auxiliary functions (shown in Fig. I): power supply. The power supply provides approximately
integraled-circuit switches operate from an ae input voltage of (I) A built-in protection circuit that may be actuated to 6 volts as the Vee supply to the other stages of the
24, 120,208 to 230, or 277 volts at 50,60, or 400 Hz. remove drive from the triac if the sensor opens or shorts. zero-voltage switch. The on-off sensing amplifier is basically a
The CAJOS9 and CA3079 are supplied in a 14·terminal differential comparator. The thyristor gating circuit contains a
dual-in-line plastic package. The CA3058 is supplied in a driver for direct triac triggering. The gating circuit is enabled
14·terminal dual-in-Iine ceramic package. The electrical and when all the inputs are at a ·'high" voltage. i.e., the line voltage
physical characteristics of each type are detailed in RCA Data must be approximately zero volts. the sensing·amplifier output
Bulletin File No. 490. must be "high," the external voltage to terminal J must be a
RCA zero-voltage switches (ZVS) are particularly well logical ·'0", and, for the CA30S8 and CA30S9, the output of
suiled for use as thyristor trigger circuits: These switches the fail-safe circuit must be "high." Under these conditions,
trigger the thyristors at [Link]-voltage points in the the thyristor (triac or SCR) is triggered when the line voltage is
supply-voltage cycle. Consequently, transient load-current essentially zero volts.
surges and radio-frequency interference (RFI) are substantially
Thyristor Triggering Circuits
reduced. In addition, use of the [Link]-voltage switches also
The diodes Dl and D2 in Fig. 2 form a symmetrical clamp
reduces the rate of change of on-stale current (di/dt) in the
that limits the voltages on the chip to ±8 volts~ the diodes 07
thyristor being triggered, an important consideration in the
operation of thyristors. These switches can be adapted for use and 013 form a half-wave rectifier that develops a positive
voltage on the external storage capacitor, CF.
in a variety of control functions by use of an internal
differential comparator to detect the difference between two The output pulses used to trigger the power-switching
externally developed voltages. In addition, the availability of thyristor are actually developed by the zero-crossing detector
numerous terminal connections to internal circuit points and the thyristor gating circuit. The zero-crossing detector
greatly increases circuit flexibility and further expands the AC Input Voltage I nput Series Dissipation Rating consists of diodes D3 through 06. transistor QI. and the
types of ae power-control applications to which these 150/60 or 400 Hzl Resistor fA 5) for AS associated resistors shown in Fig. 2. Transistors QI and Q6
integrated circuits may be adapted. The excellent versatility of through <l9 and the associated resistors comprise the thyristor
VAC kl! W
the zero-voltage switches is demonstrated by the fact that gating circuit and output driver. These circuits generate the
these circuits have been used to provide transient-free 24 2 0.5 output pulses when the at input is at a zero-voltage point so
temperature control in self-cleaning ovens, to control 120 10 2 that RFI is virtually eliminated when the zero-voltage switch
gun-muzzle temperature in low-temperature environments, to 208/230 20 4 and thyristor are used with resistive loads.
provide sequential switching of heating elements in warm-air 277 25 5 The operation of the zero-crossing detector and thyristor
furnaces, to switch traffic signal lights at street intersections, gating circuit can be explained more easily if the on state (i.e.,
and to effect other widely different ac power-control the operating state in which current is being delivered to the
Fig. , - Funcrionlll blocIc diagrllfTls of the zero-volrage switcher thyristo{; gate through terminal 4) is considered as the
functions. CA3068, CA3059, and CA3019.
operating condition of the gating circuit. Other circuit
FUNCTIONAL DESCRIPTION elements in the zero-voltage switch inhibit the gating circuit
RCA zero-voltage switches are multistage circuits that unless certain conditions are met, as explained later.
employ a diode limiter, a zero-crossing (thre~old) detector. an (2) Thyristor firing may be inhibited through the action of In the on state of the thyristor gating circuit, transistors Q8
on-off sensing amplifier (differential comparator), and a an intema¥Iiode gate connected to terminal J. and 09 are conducting. transistor 07 is off, and transistor Q6
Darlington output driver (thyristor gating circuit) to provide (3) High-power dc-comparator operation is provided by is on. Any action that turns on transistor Q7 removes the drive
the basic switching action. The de operating voltages for these overriding the action of .the zero-crossing detector. This from transistor Qs and thereby turns off the thyristor.
stages is provided by an internal power supply that has override is accomplished by connecting terminai 12 to Transistor Q7 may be turned on directly by application of a
sufficient current capability to drive external circuit elements. terminal 7. Gate current to the thyristor is continuous when minimum of ± 1.2 volts at 10 microamperes to the
such as transistors and other integrated circuits. An important terminal 13 is positive with respect to terminal 9. external-inhibit input. terminal I. (If a voltage of more than
feature of the zero-voltage switches is that the output trigger
pulses can be applied directly to the gate of a triac or a silicon
controlled rectifier (SCR). The CA3058 and CA3059 also
feature an interlock (protection) circuit that inhibits the
application of these pulses to the thyrlstor in the event that
the external sensor should be inadvertently opened or shorted.
An external inhibit connection (terminal No. I) is also
available so that an external signal can be used to inhibit the
output drive. This feature is not included in the CA3079;
otherwise, the three integrated-circuit zero-voltage switches are
electrically identical.
Over-all Circuit Operation
Fig. 1 shows the functional interrelation of the zero..yoltage
., ...
switch, the external sensor, the thyristor being triggered. and llNCRUSl:D
GaTEDRIV[
the load elements in an on-off type of ac power-control
system. As shown, each of the zero-voltage switches
incorporates four functional blocks as follows:
I
(I) Umiter-Power Supply - Permits operation directly
I
......
from an ac line.
(2) Differential On/Off Sensing Amplifier - Test. the I
I 4 TMl'ItiSTOIt
condition of external sensors or command signals. Hysteresis
I RCACAlO59
...
or proportional-control capability may easily be implemented L_-'!.~T£.D...£!....~r ______
in this section.
(3) Zero-Crossing Detector - Synchronizes the output
ALL RESISTANCE VALU[S AR[ IN OMIIIIS , ,
INHIBIT I IC'"
NOTE: CIRCUITIIIY,WITHIN SHAD[I) .... E .. S. NOT INCLUDED IN C"lOn
pulses of the circuit at the time when the ac cycle is at a
"'ICoINfEIII .. AL CDNNECTION--DD NOT USE InRIIIIII"L
zero--voltage pOint and thereby eliminates radio-frequency RESTRICTUIM .... [Link] ONLY TOCAlOrll)
inteference (RFI) when used with resistive loads. Fig. 2 - Schmrrftic dhtgr.", of zero-lfOlra,. _wlrdun CA3068. CA3059. MId CA3079.
503
ICAN-6182
more positive than the breakdown voltage of diode 015,
activation of the protection circuit is not possible. For this 120 V MIS. 50-600Hz IItERATIION I
reason, loading the internal supply may cause this circuit to
malfunction. as may selection of the wrong external supply
5 RS"SlCflNHlIJft . ,.
o.
'f~~ '\
voltage. Fig. 7 shows a guide for the proper operation of the > •
I
protection circuit when an external supply is used with a
typical integrated-circuit zero-voltage switch. ~.5r--r-~ ~
~
~ .. ~
~
i ..'r---r---" .\
.,
~
>
~ ,~--t--+---r--t-~r-
~
I 'r-~~-r--t-~---t- 0 I 2 ,
\
.•
EXTERNAL. LOAD CURRENT-mA
• , •
I!I
; Fig. 9 - DC supply voltage as fI function of external load current lor
seversl valutls of dropping resistance RS.
Fig. I I - CA3058 OF CA3059 on-off controller with hystBres;s.
crossing every half-cycle, and an output, for example pulse
No.4, is produced to indicate the zero crossing. During the If a significant amount (greater than ±10%) of controlled
remaining 8.3 milliseconds, however, the differential amplifier hysteresis is required, then the circuit shown in Fig. 12 may be
AMBIENT TEMPERATURE--t
in the zero-voltage switch may change state and inhibit any employed. In this configuration, external transistor 01 can be
further output pulses. The uncertainity region of the used to provide an aUxiliary timed-delay function.
Fig. 1 - Operating T8flions for .built-in protection circuit! of a typical
zero-voltage switch.
differential amplifier, therefore, prevents pulse No.5 from
triggering the triac during the negative excursion of the ac line
voltage.
[-
SPECIAL APPLICATION CONSIDERATIONS
As pointed out previously, the RCA integrated-circuit
zero-voltage switches (CA3058, CA3059, and CA3079) are
1[,,",
! -
exceptionally versatile units that can be adapted for use in a
wide-variety of pewer-control applications. Full advantage of
this versatility can be realized, however, only if the user has a
basic understanding of several fundamental considerations that
apply to certain types of applications of the zero-voltage
switches.
Operating-Power Options
Power to the zero-voltage switch ~ay be derived directly
from the ac line, as shown in Fig. 1, or from an external dc
power supply connected between terminals 2 and 7, as shown Fig. to - Hslf~ycling phtmomtlflon in the zero·voltage switch.
in Fig. 8. When the zero-voltage switch is operated directly
from the ac line, a dropping resistor RS of 5,000 to When a sensor with low sensitivity is used in the circuit, the
Fig. 12 - CA3058 or CA3059 on-off controller with conrrolled
10,000 ohms must be connected in series with terminalS to zero-voltage switch is very likely to operate in the linear mode. hysteresis.
limit the current in the switch circuit. The optimum value for In this mode, the output trigger current may be sufficient to
this resistor is a function of the average current drawn from trigger the triac on the positive-going cycle, but insufficient to For applications that require complete elimination of
the internal de power supply, either by external circuit trigger the device on the negative-going cycle of the triac half-cycling without the addition of hysteresis, the circuit
elements or by the thyristor trigger circuits. as shown in Fig. 9. supply voltage. This effect introduces a half-cycling shown in Fig. 13 may be employed. This circuit uses a
The chart shown in Fig. I indicates the value and dissipation phenomenon. i.e., the triac is turned on during the positive
rating of the resistor Rs for ac line voltages of 24, 120,208 to CA3098E integrated-circuit programmable comparator with a
half-cycle and turned off during the negative half-cycle.
zero-voltage switch. A block diagram of CA3098E is show~ in
230, and 277 volts.
Several techniques may be used to cope with the Fig. 14. Because the CA3098E contains an integral flip-flop,
half-cycling phenomenon. If the user can tolerate some its output will be in either a "0" or "I" state. Consequently
hystersis in the control, then positive feedback can be added the zero-voltage switch cannot operate in the linear mode. and
around the differential amplifier. Fig. II illustrates this spurious half-cycling operation is prevented. When the
technique. The tabular data in the figure lists the signal-input voltage at terminal 8 of the CA3098E is equal to or
recommended values of resistors Rl and R2 for different less than the "low" reference voltage (LR), current flows from
sensor impedances at the control point. the power supply through resistor RI and R2, and a logic "0" is
AlL RESISTANCE
VALUES A.
IN OHMS SENSOR
100,.F
Fig. 8 - Operation of ths zero-voltage switch from an tlxtBrnai de
power supply connected bBtw&en ftJrminals 2 and 7.
...
Half-Cycling Effect
The method by which the zero-voltage switch senses the
zero crossing of the ac power results in a half-cyding
phenomenon at the control point. Fig. to illustrates this
phenomenon. The zero-voltage switch senses the zero-voltage Fig. 13 - Sensitive tflmperature control.
505
ICAN-6182
Circuits that use a sensitive-gate triac to shift the firing both rand 111+ modes, some other types have very poor zero-voltage switch. When a 10,OOO-ohm series resistor is used,
point of the power triac by approximately 90 degrees have sensitivity in the m+ condition. Because the zero-voltage the voltage across the circuit is less than 3 volts and both
been designed. If the primary load is inductive, this phase shift switch supplies positive gate pulses, it may not directly drive sensitivity and output current are significantly reduced. When
corresponds to firing at zero current in the load. However, some higher-current triacs of these other types. a SOOO-ohm series resistor is used, the supply voltage is nearly
changes in the power factor of the load or tolerances of The circuit shown in Fig.20(a) uses the negative-going 5 volts, and operation is approximately normal. For more
components will cause errors in this firing time. voltage at terminal 3 of the zer9-voltage switch to supply a consistent operation, however, a 4000-ohm series resistor is
The circuit shown in Fig. 19 uses a CA3086 negative gate pulse through a capacitor. The curve in recommended.
integrated-circuit transistor array to detect the absence of load Fig.20(b) shows the approximate peak gate current as a Altnougn positive-temperawre-coetTicienl (PTC) sensors
current by sensing the voltage across the triac. The internal function of gate voltage Ve. Pulse width is approximately rated at S kilohms are available, the existing sensors in ovens
zero-crossing detector is disabled by connection of terminal 12 80 microseconds. are usually of a much lower value. The circuit shown in Fig. 22
to terminal 7, and control of the output is made through the is offered to accommodate these inexpensive metal-wound
external inhibit input, terminal 1. The circuit permits an
output only when the voltage at point A exceeds two V SE
drops, or 1.3 volts. When A is positive, transistors 0) and Q4
conduct and reduce the voltage at terminal I below the inhibit
state. When A is negative, transistors QJ and Q2 conduct.
When the voltage at point A is less than ±1.3 volts, neither of
the transistor pairs conducts; terminal I is then pulled positive
by the current in resistor R), and the output in inhibited.
Fig. 22 - Schematic diagram of circuit for use with low-resistance
sensors. A schematic diagram of the RCA CA3080
integrated-circuit operational transconductance amplifier used
in Fig. 22, is shown in Fig. 23. With an amplifier bias current,
IABe, of 100 microamperes, a forward transconductance of
2 milliohms is achieved in this configuration. The CA3080
switches when the voltage at terminal 2 exceeds the voltage at
terminal 3. This action allows the sink current, Is, to flow
from terminal 13 of the zero-voltage switch (the input
impedance to terminal \3 of the zero-voltage switch is
approximately 50 kilohms); gate pulses are no longer applied
to the triac because Q2 of the zero-voltage switch is on. Hence,
if the PTC sensor is cold, I.e., in the low resistance state, the
load is energized. When the temperature of the PTC sensor
increases to the desired temperature, the sensor enters the high
resistance state, the voltage on terminal 2 becomes greater
than that on terminal 3, and the triac switches the load off.
Fig. 19 - Use of the CA3a58 or CA3a59 together with CA3086 for Fig. 20 - Use of the CA3058 or CA3059 to provide negative g8te
pu'ses: (a) schematic diagram; (bl peak gate current (at
switching Inductive 'oads.
terminal 3) as a function of gate voltage.
The circuit shown in Fig. 19 forms a pulse of gate current
and can supply high peak drive to power traics with low Operation with Low-Impedance Sensors
average current drain on the internal supply. The gate pulse Although the zero-voltage switch can operate satisfactorily
will always last just long enough to latch the thyristor so that with a wide range of sensors, sensitivity is reduced when
sensors with impedances greater than 20,000 ohms are used.
there is no probLem With delaymg the pulse to an optimum
Typical sensitivity is one per cent for a SOOO-ohm sensor and
time. As in other circuits of this type, -RFI results if the load is
increases to three per cent for a O.l-megohm sensor.
not suitably inductive because the zero-crossing detector is
disabled and initial turn-on occurs at random. Low-impedance sensors present a different problem. The
sensor bridge is connected across the internal power supply
The gate pulse forms because the voltage at point A when
and causes a current drain. A SOOO-ohm sensor with its
the thyristor is on is less than 1.3 volts: therefore, the output
associated SOOO-ohm series resistor draws less than
of the zero-voltage switch is inhibited, as described above. The
1 milliampere. On the other hand, a 300-ohm sensor draws a
resistor divider Rl and R2 should be selected to assure this
current of 8 to 10 milliampers from the power supply.
condition. When the triac is on, the voltage at point A is
approximately one-third of the instantaneous on-state voltage Fig. 21 shows the 600-ohm load line of a 300-ohm sensor
(VT) of the thyristor. For most RCA thyristors, V'f (max) is redrawn power-supply regulation curve for the
Fig. 23 - Schematic diagram of the CA3080.
less than 2 volts, and the divider shown is a conservative one.
When the load current passes through zero, the triac Further cycling depends on the voltage across the sensor.
com mutates and turn~ off. Because the circuit is still being Hence, very low values of sensor and potentiometer resistance
driven by the line voltage, the current in the load attempts to can be used in conjunction with the zero-voltage switch power
reverse, and voltage increases rapidly across the "turned-off' supply without causing adverse loading effects and impairing
triac. When this voltage exceeds 4 volts, one portion of the system performance.
CA3086 conducts and removes the inhibit signal to permit
Interfacing Techniques
application of gate drive. Turning the triac on causes the Fig. 24 shows a system diagram that illustrates the role of
voltage across it to drop and thus ends the gate pulse. If the the zero-voltage switch and thyristor as an interface between
latching current has not been attained, another gate pulse the logic circuitry and the load. There are several basic
forms, but no discontinuity in the load current occurs. interfacing techniques. Fig. 2S(a) shows the direct input
Provision of Negative Gate Current technique. When the logic output transistor is switched from
Triacs trigger with optimum sensitivity when the polarity of the on state (saturated) to the off state, the load will be
the gate voltage and the voltage at the main terminal 2 are turned on at the next zero-voltage crossing by means of the
similar (1+ and Ir modes). Sensitivity is degraded when the Fig. 21 - Power-supply regulation of the CA3058 or CA3059 with If
interfacing zero-voltage switch and the triac. When the logic
polarities are opposite (r and 111+ modes). Although RCA 3OO·ohm sensor (6O([Link] IOBdJ lor tMO values of sBries output transistor is switched back to the on state,
triacs are designed and specified to have the same sensitivity in resistor. zero-crossing pulses from the zero-voltage switch to the triac
__________________________________________________________________ 507
ICAN-6182
TEMPERATURE CONTROLLERS lag the incoming line voltage. The moton, however. are
Fig. 29 shows a triac used in an oRoOff switched by the triacs at zero current, as shown in [Link]. 34(b).
temperature-controUer confIguration. The triac is turned on at The problem or driving inductive loads [Link] these moton
zero voltage whenever the voltage Vs exceeds the reference by the narrow pulses generated by the zero-voltage switch is
solved by use of Ihe sensitive-gale RCA40S26 Iriac. The high
2."
'OWER
OUTPUT
.."
....E.
OUTPUT
""
POWER
sensitivity of this device (3 milliamperes maximum) and low
latching current (approximately 9 milliamperes) permit
synchronous operation or the temperaturCKontroller circuit.
"""'" P.....
In Fig. 34(0), it is apperenl Ihal, Ihough Ihe gale pulse Vg of
triac Y 1 has elapsed, triac Y2 is switched on by the current
through RL I. The low latching current of the RCA40S26
, , I
triac results in dissipation of only 2 watts in RL I. as opposed
TlME-- to 10 to 20 watts when devices that have high latching
currents are used.
O.!lA
Fig. 3' - Principl,. o( proportional control. 'AG
thermal system and the closed-loop type of control. In the
circuit shown in Fig. 32, the ramp voltage is generated when
the capacitor C 1 charges through resistors Ro and R 1. The
time base or the ramp is determined by resistors R2 and R3.
capacitor C2. and the breakover voltage of the D3202U· diac.
Fig. 29 - CA3058 0' CA3D59 on-off NmpeI'lItu,. controller,
TYOE
voltage V r. The transfer characteristic of this system, shown in
AC IN5195
I·Q-.....~h ,-----=---{) TOptN Z
VCC+6V
Fig. 30(a), indicates significant thermal overshoots and I.
undershoots, a well-known characteristic of such a system. The TO PIN 9
differential or hysteresis of this system. however. can be 1-+iI'l---r~[Link]"r1"1-~OUTPUT
further increased. if desired. by the addition of positive
feedback. O.l,.F
TO PIN 7
I.
20011
~=---~--~----~----~--~
_FORMERLV RCA 45412 COMMOIII
ALL RESISTORS 1/2 WATT PIN CONNECTIONS REFER TO
[Link] OTHERWISE SPECIFIEO RCA CA5058 OR CA305'
DIFFERENTIAL
c:to.,-ce
.FORMERLY RCA40528
Fig. 32 - Ramp ..".,..ror. '0'
When the voltage across C2 reaches approximately 32 volts,
the diac switches and turns on the 2N697S transistor and
IN914 diodes. The capacitor C. then discharges through the
I.} Ib} collector-to-emitter junction of the transistor. This discharge
time is the retrace or tlyback time of the ramp. The circuit
shown can generate ramp times ranging from 0.3 to
Fig. 30 - T,.".,.,. chsractsmUc. of (.) on-off and (bJ pmpottionlll 2.0 seconds through adjustment of R2. For precise
control [Link]. temperature regulation, the time base of the ramp should be
shorter than the thermal time constant or the system, but long Ibl
For precise temperature-control applications, the with respect to the period or the 6O-Hz line voltage. Fig. 33 F;II- 34 - Dual outpUr. o","~nder [Link]'arure conrrollef fa} circuir.
proportional-control technique with synchronous switching is shows a triac connected for the proportional mode. fb} voIrag.1IIId cul'ffltlr .... for",,_
employed. The transfer curve for this type of controller is
shown in Fig. 30(b). In this case, the duty cycle of the power
supplied to the load is varied with the demand for heat
required and the thermal time constant (inertia) of the system.
For example, when the temperature setting is increased in an "K
a. ",
on-off type of controller, full power (100 per cent duty cycle)
is supplied to the system. This effect results in significant
temperature excursions because there is no anticipatory circuit
to reduce the power gradually before the actual set
temperature is achieved. However, in a proportional control
technique, less power is supplied 10 the load (reduced duly
cycle) as the error signal is reduced (sensed temperature
approaches the set temperature).
Before such a system is implemented, a time base is chosen
so that the on-time of the triac is varied within this time base.
The ratio of the on-to-otT time of the triac within this time
interval depends on the thermal time constant of the system
and the selected temperature setting. Fig. 31 illustrates the
principle of proportional control. For this operation, power is
supplied to the load until the ramp voltage reaches a value
greater than the dc control signal supplied to tt,..e opposite side
of the differential amplifier. The triac then remains off for the
remainder of the time-base period. As a result. power is
"proportioned" to the load in a direct relation to the heat
demanded by the system.
For this application, a simple ramp generator can be Fig. 34(a) shows a dual·output temperature controller that Electrlc-Heet Application
realized with a minimum number of active and passive drives two triacs. When the voltage Vs developed across the For electric·heating applications, the RCA·2N5444
components. A ramp having good linearity is not required for temperature-sensing network exceeds the reference voltage 40-ampere triac and the zero-voltage switch constitute an
proportional operation because of the nonlinearity of the VRl, motor No. I turns on. When the voltage across the optimum pair. Such a combination provides synchronous
network drops below the reference voltage VR2, motor No.2 switching and effectively replaces the heavy-duty contacton
• Fonnerly RCA 45412 turns on. Because the motors are inductive, the currents 1M 1 which easily degrade as a result of pitting and wealout from
_______________________________________________________________ 509
ICAN-6182
system. Many types of automatic equipment are not complex
2N5444 " "', enough or large enough to justify the cost of a flexible logic
system. A special circuit, designed only to meet the control
requirements of a particular machine, may prove more
economical. For example, consider the simple machine shown
in Fig. 42; for each revolution of the motor. the belt is
advanced a prescribed distance, and the strip is then punched.
The machine also has variable speed capabiJity.
O.5,.F
200VOC C
Fig. 42 - $tep-tlfld-punch trIIIChin ••
* fOR PftOPORTlOftAL OP(RATIQh OPEN TERMINALS 9,10 IoNQ II "'ltd) CONNECT POSTIVE RAMP VOlTAGE TO lVINIMAL 11
_.SELECTED FOR XGT-6 mA MAXIMUM
_FORMERLY RCA 44003
_FORMERLY RCA 40655 The typical electromechanical control circuit for such a
machine might consist of a mechanical cambank driven by a
Fig. 39 - CA3058 01' CA3059 iflttlgnll-cycltl [Link] controlle, separate variable speed motor. a time delay relay, and a few
rltat features #I prottICtion circuit and no "'1f~I;ng effect. logic and power relays. Assuming use of industrial-grade
controls, the control system could"get quite costly and large.
When the ae line swings negative, capacitor C discharges leg of the ac line is maintained at ground. The comparator. Al Of greater importance is the necessity to eliminate transients
through the triac gate to trigger the triac on the -negative (a CA3130). is powered from a 6.4-volt source of potential generated each time a relay or switch energizes and deenergizes
half-cycle. The diode-resistor~apacitor "slaving network" provided by the zero-voltage·switch (ZVS) circuit ~a CA307:». the solenoid and motor. Fig. 43 shows such transients, which
triggers the triac on negative half-cyc1e to provide only integral The ZVS, in turn, is powered off-line through a senes-droppmg might not affect the operation of this machine, but could
cycles of ae power to the load. resistor R6. Terminal 4 of the ZVS provides trigger-pulses to affect the more sensitive solid-state equipment operating in the
When the temperature being controlled reaches the desired the gate of the load-SWitching triac in response to an appro· area.
value, as determined by the thermistor, then a positive voltage priate control signal at terminal 9. A more desirable system would use triacs and zero-voltage
level appears at terminal 4 df the zero-voltage switch. The SCR switching to incorporate the following advantages:
then starts to conduct at the beginning of the positive input a. Increased reliability and long life inherent in
cycle to shunt the trigger current away from the gate of the solid-state devices as opposed to moving parts and
triac. The triac is then turned off. The cycle repeats when the contacts associated with relays.
SCR is again turned OFF by the zero-voltage switch.
The circuit shown in Fig. 39 is sfmilar to the configuration
in Fig. 38 except that the protection circuit incorporated in
the zero-voltage switch can be used. In this new circuit, the
NTe sensor is connected between terminals 7 and 13, and I~IK ~1-:Y0r®-l
REF.
VOLTAGE
transistor Qo inverts the [Link] at terminal 4 to nullify A[hJUST
the phase reversal introduced by the SCR (Y I)' The internal
power supply of the zero-voltage switch supplies bias current
to transistor 0 0 ,
Of course, the circuit shown in Fig.· 39 can readily be
converted to a true proportional intepak:ycle temperature HYSTERES'S ·R3/R4XII.4V' IK/~.lMII6.4V '12~1ft1/
92CM·29961
controUer simply by connection of a positive-going ramp
Fig. 41 - Thermocouple remperatunlcontrol with Zf1«J·voitllp
voltage to terminal9 (with terminals 10 and 11 open), as .witching.
previously discussed in this Note.
The CA3130 is an ideal choice for the type of comparator Fig. 43 - Transients generated by reiay-contllCt bounce lind non-zero
Thermocouple Temperature Control circuit shown in Fig. 41 because it can "compare"low voltages tum-oH of inductil/fl 10ild.
Fig. 40 shows the CA3080A operating as a pre-amplifier for (such as those generated by a thermocouple) in the proximity
the zero-voltage switch to form a zero-voltage Switching circuit of the negative supply r~il. Adjustment· of potentiometer RI
for use with thermocouple sensors. drives the voltage-divider network R3, R4 so that reference b. Minimized generation of EMI/RFI using zero-voltage
voltages over the range of 0 to 20 millivolts can be applied to Switching techniques in conjunction with thyristors.
noninverting terminal 3 of the comparator. Whenever the c. Elimination of high-voltage transients generated by
voltage developed by the thermocouple at terminal 2 is more relay-contact bounce and contacts breaking inductive
positive than the reference voltage applied at terminal 3, the loadS, as shown in Fig. 42.
comparator output is toggled so as to sink current from ter- d. Compactness of the control system.
minal 9 of the ZVS; gate pulses are then no longer applied to
The entire control system could be on one printed-circuit
the triac. As shown in Fig. 411, the circuit is provided with a
board, and an over-all cost advantage would be achieved ..
control-point "hysteresis" of 1.25 millivolts.~
Fig. 44 is a timing diagram for the proposed solid-state
Nwling of the comparator is performed by means of the
following procedure: Set Rl at the low end of its range and
short the thermocouple output signal appropriately. If the
ALL RESISTORS 1/2 WAlT triac is in the conductive mode under these conditions. adjust
UNLESS OTHERWISE SPECIFIED
UCS-22619 nulling potentiometer R5 to the point at which triac conduc-
Fig. 40 - Thermocoupl. temper"tu,. control with zero·lIOItllge tion is interrupted. On the other hand, if the triac is in the non-
switching.
l:onductive mode under the conditions above. adjust R5 to the
point at which triac conduction commences. The thermo·
Thermocouple Temperature Control with Zero-Voltage load
couple output signal should then be unshorted. and Rl can be
Switching
Fig. 41 shows the circuit diagram of a thermocouple temp- set to the voltage threshold desired for control-circuit operation.
erature control system using zero·voltage load switching. It
should be noted that one terminal of the thermocouple is con· MACHINE CONTROL AND AUTOMATION
nected to one leg of the supply line. Consequently, the thermo- The earlier section on interfacing techniques indicated
couple can be "ground·referenced", provided the appropriate several techniques of controlling ae loads through a logic Fig. 44 - Timing rJillfl'"m tor propo$fK/ $OlId-sttJre mllChine control.
511
ICAN-6182
SYNCHRONOUS LIGHT FLASHER
Fig. 50 shows a simplified version of the
synchronous·switching traffic light flasher shown in Fig. 49. o..,.f 'OK
Z5VDC
2.
....'20
,-
I
VI<
I
120VAC
1i5voc+
GOH'
I OJ,.'
10VOC
ON
Fig. 60 - Synchronous light flasher.
Flash rate is set by use of the curve shown in Fig . .J 6. If a more
*IF Y2' FOR EXAMPLE, IS A "O'AMPERE TRIAC, THEN R, MUST BE DECREASED TO SUPPLY
precise flash rate is required, the ramp generator described
SUfFICIENT lGT fOR Y2
previously may be used. In this circuit, ZVS 1 is the master • FOftMULY RCA 40191
control unit and ZVS2 is slaved to the output of ZVSl
through its inhibit terminal (terminal I). When power is Fig. 5' - Zero'lIOltllgtl switch trIInSient·'rBfI switch controller in which
POweT is supplied to thelOild when the switch ;s tJpM.
applied to lamp No. I, the voltage of terminal 6 on ZVSl is
high and ZVS2 is inhibited by the current in Rx. When lamp
No. I is off, ZVS2 is not inhibited, and triac Y2 can fIre. The
power supplies operate in parallel. The on-of( sensing amplifier
in ZVSa is not used.
TRANSIENT·FREE SWITCH CONTROLLERS
The zero-voltage switch can be used as a simple solid-stat;e
Switching device that permits ac currents to be turned on or
off with a minimum of electrical transients and circuit noise.
The circuit shown in Fig. 51 is connected so that, after the
control terminal 14 is opened, the electronic logic waits until
the power-line voltage reaches a zero crossing before power is
applied to the load ZL. Conversely, when the control terminals
are shorted, the load current continues until it reaches a zero 120VAC
OOH,
crossing. This circuit can switch a load at zero current whether
it is resistive or inductive.
The circuit shown in Fig. 52 is connected to provide the
opposite control logic to that of the circuit shown in Fig: S 1.
That is, when the switch is closed, power is supplied to the
load, and when the switch is opened, power is removed from
the load.
In both configurations, the maximum rms load current that
can be switched depends on the rating of triac Y2. IfY2 is an
RCA·2NS444 triac, an rms current of 40 amperes can be * IfYz , fOA EXAMPLE, IS A 40-AMP[RE TRIAC, AI MUST 8E DECREASEO TO SUPPLY
switched. SUFfiCIENT IGT fOR Yz
• FORMERLY RCA "0691
DIFFERENTIAL COMPARATOR FOR IN~USTRIAL USE Fig. 52 - Zero·voltage switch transient-free switch controller in which
Differential comparators have found widespread use as limit poWflr;s applied to the load when the switch is closed.
detectors which compare two analog input signals and provide
a go/noogo, logic' one" or logic ''zero'' output, depending
upon the relative magnitudes of these signals. Because the
signals are often at very low voltage levels and very accurate
'L
ANY POWER
FACTOA
discrimination is normally required between them. differential
comparators in many cases employ differential amplifiers as a
basic building block. However. in many industrial control
applications. a high-performance differential comparator is not
required. That is, high resolution, fast switching speed. and
similar features are not essential. The zero·voltage switch is
ideally suited for use in such applications. Connection of
terminal 12 to terminal 7 inhibits the zero-voltage threshold
detector of the zero-voltage switch, and the circuit becomes a
differential comparator.
Fig. S3 shows the circuit arrangement for use of the
zero-voltage switch as a differential comparator. In this
application, no external dc supply is required. as is the case .
with most commerCially available integrated-circuit
comparators; of course. the output-current capability of the
zero·voltage switch is reduced because the circuit is operating
in the dc mode. The l()()().ohm resistor Ro. connected
between terminal 4 and the gate of the triac, limits the output
current to approximately 3 milliamperes.
• fCMtMULY IilCA 40191
When the zero-voltage switch is connected in the dc mode,
the drive current for terminal4 can be determined from a FI,. 53 - DifftmlntitJI COTrlplHator wing rhfI CA305B or 00\3059
curve of the external load current as a function of dc voltage in,...tfId-clrcu;t zero·WI',..,. "witch.
_____________________________________________________________________ 513
ICAN·6182
3. Two phases must be turned on for initial starting of the
system. These two phases form a single-phase circuit
which is out of phase with both of its component phases.
The single-phase circuit leads one phase by 30 degrees
and lags the other phase by 30 degrees.
These conditions indicate that in order to maintain a
system in which no appreciable RFI is generated by the
switching action from initial starting through the steady-state
operating condition. the system must first be turned on, by
zero-voltage switching, as a single-phase circuit and then must
revert to synchronous three-phase operation.
Fig. 60 shows a simplified circuit configuration of a
three-phase heater control that employs zero·voltage
syncluonous switching in the steadY4tate operating condition,
with random starting. In this system, the logic command to
turn on the system is given when heat is required, and the
command to turn off the system is given when heat is not
required. Time proportioning heat control is also possible
thrOUgh the use of logic commands.
The three photo-ooupled inputs to the three zero-voltage
switches change state simultaneously in response to a "logic
command". The zero-voltage switches then provide a positive
pulse, approximately 100 microseconds in duration, only at a
zero-voltage crossing relative to their particular phase. A
balanced tluee-phase sensing circuit is set up with the three
zero-voltage switches each connected to a particular phase on
their common side (terminal?) and referenced at their high
side (terminalS), through the current-limiting resistors R4,
RS, and R6. to an established artificial neutral pOint. This
artificial neutral point is electrically equivalent to the
inaccessible neutral point of the wye type of three-wire load
Fig. 67 -"".. Control ci~uit usin, a CA3058 or CA3069 and two and, therefore, is used to establish the desired phase
CA3086 inte(p'[Link],.. relationships. The same artificial neutral point is also used ~o
establish the proper phase relationships for a delta type of
three-wire load. Because only one triac is pulsed on at a time,
the diodes (Dl, D2, and D3) are necessary to trigger the
•• 0
opposite-polarity triac. and. in this way, to assure initial
latching·on of the system. The three resistors (RI, R2, and
R3) are used for current limiting of the gate drive when the
opposite-polarity triac is triggered on by the line voltage.
In critical applications that require suppression of all
generated RFI. the circuit shown in Fig. 61 may be used. In
addition to synchronous steady-state operating conditions, this
circuit also incorporates a zero-voltage starting circuit. The
start-up condition is zero-voltage synchronized to a
single-phase, 2·wire, line-to-line circuit, comprised of phases A
and B. The logic command engage' the linsle-phase .tart-up
zero-voltage .witch and three-pIwe photo...,upled
isoiatonOCl3. OC14. OCIS through the photo-coupled
Fig. 68 - On~ff touch switch.
control circuits. This signal must be electrically isolated In the three-phase circuits described in this section,
from the three·phase power system. photo-optic techniques (i.e., photo-coupled isolators) are used
3. Three separate triac gating signals are required. to provide the electrical isolation of the de logic command
4. For operation with resistive loads, the zero-voltage signal from the ac circuits and the load. The photooCoupled
SWitching technique should be used to minimize any isolaton consist of an infrared light-emitting diode aimed at a
radio-frequency interference (RFI) that may be silicon photo transistor, coupled in a common package. The
generated. light-emitting diode is the input section, and the photo
transistor is the output section. The two components provide a
1 _ aI DC ....... ClrauItry voltage isolation typically of I SOO volts. Other isolation
As expbdnocl earlier WIder Speolol AppIb_ techniques, such as pulse transformers. magnetoresistors, or lal
~ isolation of tho de losic circuitry" from tho ac reed relays, can also be used with some circuit modifications.
line. tho _ . and tho load circuit is often desirable ..... in
Resistive Loads
many sinsle-phase power-oontrol applicationa. In control Fig. S9 illustrates the basic phase relationships of a
circuil1l for pclypbaae power ayatoms. however. this typo of balanced three-phase resistive. load. such as may be used in
.isolation is essential, because the common point of the de logic heater applications, in which the application of load power is
circuitry cannot be referenced to a common line in all phases. Ibl
controned by zero.>Oltaao switchins. The fonowing condillona
are inherent in this typo of application:
• The de tope _ prooIdos the Iow-level olectrk:al _ that
I. The phu.. are 120 degr... aparl;conaequently. all three Fig. 69 - Volt.., phase ";'tionship for a thrH-p/IMe "';8tillll load
dictate. the state of the load. For temperature controls. the de Io8ic phases cannot be switched on simultaneouJly at zero when the BPtJlicarion of IOIHI power is controlled by
circuitry incluc1cs a temperature sensor for feodback. The RCA zero·vol. switching: fal voItllflB .......forms. fbI losd~in:uit
>oltaao.
intepated-clmrit zero-voltap IWitch, when operated. in the de mode
with I08l8 additional circuitry. can Ieplace the de Iosic cltcuitry for 2. A single phase of a wye confrguration type of three-wire =,::~0:'~r[Link],::,,;::,,:~~n::e::'Zditt;:,:.';:
system cannot be turned on. deviation at starr-up and hlrn~ff should be noted.1
temperature controls.
_____________________________________________________________________ 515
ICAN-8182
Fig.. 62 - Triac three-phase control circuit fo, an inductillfl load, [Link].,
thretl-pluJsemoror.
517
ICAN-8222
Considerations in Low-Noise Performance
AMBIENT TEMPERATURE !T"J'25-C
Fig.S shows the schemati<;: diagram of a noise model
useful in a review of the considerations pertinent to opti-
mizing low-noise performance in amplifier operation.
;--
'~-~---~r+---1--+-+++--r--~-H
ENT•
REFERREO
TOHERE~ . ,. 100
FREQUENCY Cf) -
. ,.
Hz
1000
. ..
10,000 • SEE FIG_2
QI-QI CONTAINEO IN
THE C"3095E
Fig. • - H;gIr-inpur-rtn;~tllnctl. low-nol.. smp/ifier cirr:uit.
Fig. 6 - Noise curmnt In lIS II luncrion of frequlH1Cy f forlNlChsuPtlr-betIJ
TOTAL INPUT-REFERREO NOISE ...OLTAGE [Link]' ENTI cascodtNJmpliIi",. trllnsistor psir (a, - 0 3 lind O2 - 0 4 ), is typically about 750 microamperes at a supply voltage of
FOR AMPLIFIER ORIVEN FROM SIGNAL- SOURCE HAVING SOURCE
12 volts, although the current in transistors Q} and Q2 is less
RESISTANCE RS. Entilin VI.,/HiJ '''4I<TRs+!InRsJ2+!EnJ'
signal-to·noise ratio at a particular frequency and source re- than 5 microamperes.
sistance. This adjustment is accomplished by selecting an
operating point for which En is approximately equal to Low-Noise Video Amplifier
Fi,_ 5 - Sourr:.. of nollll in the transisror-6tnplififK stage. J]: In Rs. For example. the optimum operating collector The circuit shown in Fig. 9 illustrates the use of super·beta
currents in the differential-cascade amplifier are about 5 micro- transistors in the input stage of a video amplifier. The circuit is
This model illustrates that consideration must be given to amperes when the amplifier is to be driven from two 300-kilohm capable of delivering 4 volts, peak-to-peak, of output signal with
three major sources of noise: source resistors. For operation from higher source resistances, a typical gain of 33 dB across a bandwidth from dc to 10 MHz
the currents should be proportionately lower, and vice versa. (3-dB point). In this application, each super-beta transistor is
1. Noise contributed by the "thermal-noise" voltage de-
Operating currents in the range from 0.1 to 1.0 milliampere biased fOI operation at about 400 microamperes to achieve
veloped across the signal-source resistance, Rs- The magni-
are recommended when the amplifier is to be operated as a wideband operation. The super-beta transistor characteristics
tude of this voltage in V/.['& is approximately equal to
low-noise video amplifier. At these current levels, the gain- minimize the contributions to noise generated by noise current
J4KTRs for a l-cycle bandwidth, where k is Boltzmann's
bandwidth product (fT) is increased significantly with respect (In) in the input stage. The equivalent input·[Link]-
constant (1.38 x 10-23 jouletK), T is the temperature in
to low collector current operation. frequency characteristics for the entire amplifier circuit are
degrees Kelvin, and Rs is the source resistance in ohms.
shown in Fig. I O. TransistorsQ 1 through Q4 are connected as an
2. The noise voltage, En. resulting from the combined effects
ILLUSTRATIVE CIRCUIT APPLICATIONS emitter-coupled pair of cascade amplifters with a single-ended
of shot noise due to emitter current flow and thermal
noise due to transistor base resistance. These effects add Like other RCA transistor-array IC's, the CA309SE offers load resistor, R3, to drive a discrete transistor Q-PNP. This
combination provides sufficient current gain to drive Q6' the
in rms fashion to give a total En equal to (Eshot 2 + the circuit designer a class of solid-state devices featuring
voltage-gain-stage transistor, with load resistor RS' Resistor
4KTrb'b)~. The shot-noise component, Eshot, is inversely matched electrical and thermal characteristics, compactness,
R7 provides a path for dc and ac feedback around this stage.
proportional to the square root of IEQ, and has a value ease of physical handling, economy, and versatility of use. The
Transistor Q8 is an emitter-follower output stage. The typicaJ
14.2 x 1O- l2 current drain of the amplifier is approximately 8 milliamperes
Eshot; r-;---"""' (V/Hz.)
at a total supply voltage of 10 volts.
~ lEO
In super·beta transistors, the base resistance component of
En tends to dominate, particularly at currents greater than ~oo.~~~~~
10 microamperes. In addition, this component of En has ~
been experimentally found to be inversely related to oper-
atingcurrent. Therefore, the total value of En is inversely re- ~,~'~++~I~~I~~~ ........ COLLECTOR CURRENT (Icl.~,..A
lated to operating current IEQ. For example, the CA3095E ~ 10 ............
has a total t -kHz En of approximately 15 nV I ffz at a
collector current of 5 microamperes and approximately
g :
~
8 nV 11Hz at SO microamperes. ~ 4~-+--+-~+--+--+-~+--+--+-~
3. The noise current, In, resulting from the combined "shot
noise" generated by the flow of base current and the I If
noise generated in the transistor. The magnitude of In is
approximately proportional to JfiB,
where lIB is the base 10
... 100
FREQUENCY Hl-HI
... 1000
. ..
10,000
current. The value of In is typically 0.12 pAl /HZ at f =
t a Hz when the super-beta differential-cascode amplifier Flg.7 - NolH WJIYgtI En". function of ff«lUlll'C'I f for fIIII:h wper-betIJ ..... ·33e
t:lIICfJdtHmplifier trtIMinor ptlir (0,-[Link] Q2-0.,/. BW3dB'IOflltl
in the CA309SE is operating at IEQ = 5 p.A. In decreases ·SEE FIG. 2
to approximately 0.03 pA.[HZat f = I kHz. QI-08 ARE CONTAINED
When each input terminal in a differential amplifier is drive" IN CA30"'
from a source resistance (Rs), the total noise voltage (referred CA309SE is an electronic "building block" which permits the
to the input, see Fig. 5) per unit bandwidth is given by: designer to optimize performance of a particular circuit for FI,. 9 - Video amplifier.
gain, noise, power consumption, bandwidth, and/or other
Eoti (in v//fu); hKTRs+ 2 (InR,)2 +tI!nl specific considerations_ Some typical circuit applications of
I~
the CAJOOSE are described below.
When amplifiers are driven from low source impedances, En is
the predominant factor in noise contributions, whereas the
effect of In predominates ~hen input signals· are supplied
HIllt-In....[Link].. Low-Noi.. Amplifior
1 '0\ r---
The CA309SE contains all the transistors necessary for the
~
from high source impedances. Consequently, since the
CAJ09SE operates with very high beta at very low operating
construction of a low-noise. feedback amplifier harina.a high
input resistance (RIN '" 20 M!'I) and a 3-dB boDdwidth of
1\ --
currents, it has exceptionally low values of In' and is an excel-
about 50 kHz. In the circuit shown in Fig. 8, voltage gain is r-..
lent choice to amplify signals from high source resistances when
provided by a cascade of two stages, the differential-cascode
low amplifier noise contribution is desired. Additionally, the
incidence of "popcorn" (burst) noise 2 is low in the CA309SE,
a characteristic which further enhances its suitability for use in
stage (01.03 - Q2. 04) and the differential slap (07. OS)-
Transistor Q6 is an interstage emitter·follower. The voltage
1\ r--.
ampUfyingsignals supplied from high-impedance sources. Figs. 6 gain of the amplifier (approximately 30 dB with the circuit
and 7 show typical data on In and En characteristics. values shown) is essentially established by the ratio of Rs to
respectively, as a function of frequency, for the super-beta the parallel combination of RS and R6. The RS, C2 IlIItwork..
10 2 4 68102 2 4 68103 2 4681042 4 '[Link]
transistors in the CA309SE. couples feedback around the entire amplifier. Capacitor C4
FREQUENCY (fl-Hr
Because the operating current of the super-beta transistors provides stabilizing compensation. The output-voltage swing
in the CA3095E is adjustable over a wide range, the circuit (Eo) is typically 3 volts. peak-to-peak_ Typical noise-figure FIg. '0 - Equivalent input noise voIrag. .... frequency for thll cirr:uitof
designer can optimize the operating current for maximum data are shown in Fig. 8. Power consumption of the amplifier Fi(J.9.
________________________________________________________________ 519
ICAN-6222
" ".
,0>
I..OW· OIUFTi~~~~A~~~RCONSTANT
Fifl. '6 - Typical w".,..".ta op"llmp IIPPJicllrions:
lal piuoelectric rranaduew IImplifier
(b) low-drlfr. long-tim.-eQnsranr intqrlltor.
Fig. 14 - Op·.mp with unity (JlIin pl'llillTlp/ifier.
Fig. 18 - Tapti play·back preamplifier equalized for
NAB standarch (7.5 inls).
...'" playback standards is shown in Fig. 19. Transistors QI and Q3
are cascode<onnected as the input stage. and transistor Q6 is
108M connected as a common~mitter post·amplifier. Transistor 02
'"
200. and Q4 are non-conductive because the emitter-base junction
in Q2 and the base-collector junction in Q4 are shunted by
'" ....."'"c-,.-,.-(ii}-r
external wiring. Equalization for the RIAA phonograph-
frequency-response characteristics is provided by the RI, CI
network connected in the ac feedback path. DC feedback
stabilization is provided by the path through resistor R2' The
·SEEFIG.2
amplifier has an over-all gain of about 40 dB at I Hz, and can
deliver output voltages in the order of 2S volts. peak-to-peak.
The dynamic range of these circuits is typically about 95 dB
with the gains indicated.
arrangement. Biasing and dc feedback are applied at terminal 7
of the CA309SE through a IO-megohm resistor. The CA748
op-amp drives a 200-microampere meter calibrated in tenns of
the voltages to be measured. A full-scale reading occurs when
the voltage applied to pin 9 is SOO millivolts dc. The entire cir-
cuit is nulled with the SOO-kilohm [Link] potentio-
meter. The total power-supply requirement is only 6 volts with
a supply current of only 300 microamperes; this requirement
can be met with batteries. The input impedance of this simple
• SEE FIG 2:
circuit is approximately 40 megohms on all scales.
Fig. 15 - Op"llmp with high1Jllin prtJIImP/ifiH.
reactance of the ~oupling capacitor C must be much lower than Preamplifier for Tape-Head Sign'"
5 megohms to achieve the high-input-impedance characteristic The exceptional low-noise characteristics of the CA309SE
described above.) The low-drift, long-time-constant integrator make it suitable for preamplifier service in professional-grade
circuit shown in Fig. 16(b) is another excellent application for tape-playback systems. A typical circuit with equalization for
the CA309SE super-beta transistor array. Because exceedingly NAB standards (7.5 in/s) is shown in Fig. 18. Transistors QI
low input bias currents permit the use of a high·value inte- and Q3 are cascode-connected as the input stage, and transistor
grating resistor. R, without introducing substantial error,long- Q6 is connected as a common·emitter post-amplifier. Tran-
time-constant integration can be accomplished. The low input· sistors ~ and Q4 are non-conductive because the emitter-
offset-voltage drift characteristic of the super-beta transistors base junction in 02 and the base-collector junction lit Q4 are 0' Q6AlIlco,n ...tEp'01
THlC.30"E
also contributes to low-error performance. Further reductions shunted by external wiring. Equalization fOY the NAB tape· ·SHf'G2
in error effects, particularly with temperature variation, can be playback, frequency-response characteristics is provided by the
achieved by using a temperature compensated bias-current R I. C 1. C2 network connected in the ac feedback path; DC
source (e.g., RI-R3, Dl). In the circuit of [Link], such an Fig. 19 - PrNmplifier eqlRllizad for RIAA stJlndanh .[Link]
feedback stabilization is provided by the path through resistor to magnetic phonOf/fllPh catridges.
arrangement could be implemented by using Q6 in a diode
R2. The amplifier has an over·all gain of about 37 db at 1 kHz.
connected fashion to serve as DI. With such an arrangement,
and can deliver output voltages in the order of 25 volts, peak-
temperature-compensated bias current is applied to the in-
to-peak. The circuit confIguration of Fig.I8 is preferred to the
verting input terminal. differential-amplifier configuration because it limits the input- ACKNOWLEDGMENT
noise contribution to that of a single transistor (e.g., Q1)' The circuits of Figs. 18 and 19 were designed by LA Kaplan.
High·lnput·I ............. DC-VoI_ Circuit
REFERENCES
The combination of a preamplifier circuit using the
1. "Super-Beta Transistor Array," CA309SE, RCA Data File
CA3095E in conjunction with a CA748 op-amp as deocribed
PreampUfier for Signals from Magnetic-Phonograph Carb'idges No. 591.
above is adaptable to dc-voltmeter circuits requiring high input
impedance, as illustrated by the circ\lit of Fig. 17. An ap- The exceptionaJ low-noise characteristics of the CA3095E 2_ "Measurement of Burst ("Popcorn") Noise in Linear In-
propriate resistor-divider network is provided to develop a dc are also of great use in preamplifier service in equipment used tegrated Circuits," T. J. Robe, RCA Application Note
input signal at terminal 9 of the CA309SE with transistors to reproduce signals from magnetic phonograph cartridges. ·A ICAN-6732.
Q} - Q3 and Q2 - Q4 connected in the differential-cascode typical circuit for this application with equalization for RIAA 3. ''Operational Amplifiers," RCA Data FUe No. 531.
521
ICAN-8247
AFPC 35810lHJ POWER The "on" and "ofP' condition of the transistor 054 is
"
BYPASS FILTER CRYST"'LFILTER SUPPLY
determined by the state of the transistor-pair 011 and 01~'
T* During the "ou" (sampling) interval, a signal from the hori-
zontal rate keyer disables transistor 011 and the collector cur-
rent of the transistor 0 I ~ maintains the transistor 054 in the
"on" condition. During the "ofP' (hold) period, transistors
Oil and 01 ~ change their states and the transistor QS4 is "ofP'.
The bias sample-and-hold circuit, similar in structure to the
above-described circuit, consists of the sampling switch 059
and the transistor-pair 0)7 and 018' This circuit, also acti-
vated by a signal from a .horizontal rate keyer, samples the
quiescent potential of the phase detector. The two signals,
the error and the bias, processed by the sampling circuits, are
stored in filter capacitors, and are applied to opposite terminals
of a differential phase control. The phase control circuit syn-
chronizes the reference carrier produced by the VCO.
Depending on the free-running frequency of the yeO, the
detected signal is in the form of positive or negative going
pulse trains which are then stored in a mter capacitor. The
1'119 1'118
sampling switch has equal drive capabilities for both polari-
12K II< ties of the signal; a requirement of particular importance in the
presence of noise signals. Non-linear operation of the detector
and sampling circuit would produce a rectified dc component
causing an erroneous detuning of the yeo.
TheVCO Loop
The amplification and amplitude limiting of the oscillator
signal takes place in the amplifier-limiter formed by the tran·
Fig, 3- Subcarrier regeneration circuit.
sistor-pair 060 and 020' The output from Q20 is fed to the dc
controlled phase-shifter and returns to the amplifier through a
crystal filter. The amplifier operates in a non-inverting mode,
j --------- Q~ - - - - - - - - - - - - - -+~c- - - - - - - - - - - - CAii2aQ - - - , hence, the total phase shift through the phase-shifter plus cry-
stal filter must be \a multiple of 2 rr radians. The crystal fIlter
I FIAS~~~ROMA (~~~l : is tuned to the subcarrier frequency and the filter band-width
.
I I is determined by a resistor in series with the crystal. The OC
I RI 1'1"00 I controlled phase-shifter has a phase range of approximately
I 300 I
I 1'12 1'15 \
± 4" radians, and a phase change activated by a control signal
I 100 100 I
I I results in a corresponding oscillator frequency change.
I
In the phase-shifter, the oscillator signal available at the col-
lector of 020 is applied to the base of 014 from which it pro-
CHROtolA ceeds along two paths. An integrated capacitor C2 couples
INPUT
this signal from the emitter of 014 to the collector load of
015 and, at this point, the signal is phase-shifted by approxi·
mately "/4 radians. In the second path. the signal arriving at
the collector of 015 passes through a current splitter formed
by the transistor-pair OS6. 015' This signal is reduced to a level
determined by the control voltage at the bases of transistors
056 and 0 I S· At one extreme, transistor 0 ISis OFF and the
\._.~-,--J signal at the collector of 015 arrives through the capacitor C2
rOS£CQNO only. Conversely, with transistor 015 ON, and OS6 OFF, the
CHAR,JpMA
signal arriving through the transistor 015 is phase-oriented so
that the resultant signal has a phase of +3/4 11' radians. The
phase-control is linear throughout most of the control range.
A buffer amplifier is used to supply the CW carrier re-
quired for the demodulators, and the carrier is available at
terminal 8. Internally, the buffer amplifier supplies the two
synchronous detectors. Two R.(' phase-shifters fed from the
buffer amplifier provide the required phase orientation. A low·
pass R14-C3 filter shifts the carrier to the AFPC detector by
-n/4 while a high-pass filter provides a +rr/4 oriented carrier
for the ACC·ki1ler detector.
I
I I AMPLITUDE CONTROL OF THE CHROMINANCE SIGNAL
I I Two cascaded amplifier stages serve to process the chroma
I '"" I signal and several signals are developed to control the gain of
I I each stage.
L __________ ~ _________________ _ ______ J
Fint Chroma Amplifier and ACe Servo Loop
The first chroma amplifier. shown in Fig. 4, is controlled by
the burst responsive ACC-killer detector only. The amplifier
formed by the transistor-pair Q I, 02 is driven singJe-ended by
Fig. 4- The filst chroma amplifier and the ACe servo loop,
the applied composite chroma signal. The amplified output
detector from the switching pulses generated in the sampling sampled signal is stored in the AFPC' filter L"apacitor whkh. from this stage drives differentially the synchronous ACe·
circuits. The sample-and-hold action is accomplished by can· with R~O' determines the til!le constant during this time killer detector. The gain of the first amplifier is a function of
trolling the conduction current in transistor 054 thus alter- interval. During the hold period. transistor OS4 is off and the the dc emitter current supplied by the constant current source
nating the charge path during those intervals. During the tilter time constant is several orders of magnitude larger than 03' This current source is biased to provide a nominal current
sampling interval. transistor 054 conducts and its emitter previously. The discharge of the filter capacitor is reduced and. hence, a nominal gain in the first amplifier stage. The bias
exhibits a relatively low impedance in comparison with the to very small hase bias currents only and little of the stored of the current source is reduced in response to a detected burst
value of the integrated charging resistor R ::!o. The detected or information is lost. signal and the gain of the first stage diminishes correspondingly.
___________________________________________________________________ 523
ICAN-8247
RF BY PASS AFPC FILTER XTAL FILTER CARRIER
OUTPUT
C$!' '$ (7)' ~ '® 8
1----- T:------r---,-----,---,- ---
I
I
I FIRST CHROMA
I AMPLIFIER
I
I
I
I
I
I
I
I R60
I '~
CHROMA
INPUT
SECOND CHROMA
AMPLIFIER
:::1 t wr03-'-O-6-'--+0-70-i~ ~i'" I Lt
~.;~ :l:~.:':, r,: ~
06 I
:
.@
'--v
I: :':
~ ~ I Rir:+-:::~;I~I;;t-o{'""-_+-~+-~:::::ir1141R44 ~R45 I
D~l~ ~~8 I A.. ~'4 I 0 40
~'J+,4't1~~===ti===F=~::::tttr----t~II~]
~66 '-CJO_~2'
•0 r: '- I
-ret" 0.21
I~
-'t
~
II
I
r-l--+---IH-H---',.t
~9
~
II
I
~~~_ _~I_~_~++___~_~~
I :~~
~'7 I
I
~46
R72
FI~~iR
,- _
J '----+---' I 2K I
CHROMA
OUTPUT
~::I=+:t:=:::;-t:t=
ACC"I ,:-:::j ruNER...'. r
J., I- - -.l - -I. - - - -
~
67
I ~,
I
'i6' I
r I R:: I . R49 I I
I
AMP
700 I
I
IREFERENCE
I 18K
I
075 I :.!~
. R62 I
I
C~~~:A f-- ~~... i~7".'o7 I 029 ~ I I ~ I ~7 KEYER ~1-t1""'-Iy'-+'D"'7=7----~+-----I----'1
790022 I ~ I R46,A- J I Z2Z3 ~ I ~R!S31I 2.94K
. .-
CONT:'I
~
R'0 I R61 074 R68 r---",+-R7-.------Hf-----t---t'
OVERLO~ol
DETECTOR I
>'IN\, r.. I 02.
I 'i.L~
I 020027r--f0
28 R48 R51 I 0.0
1
nr=-
I ~I I
700 I
I.!SK
R67 I
~.'KI048 I
!~ 0'8 ~~5 15KI ~~ZI R74
I i ~:~ II K~~~R 1-~47 2K
I 2K I I R55 I ~ IK t-<.---...J ,I
I I ••0 I IR45'K 10KR50 I R52I K I II '.5 KRS4 I
~6;
042 I ;;; R75
I C04 1.2 K I
I I d. FI I 220 IK I o4!
I I I I VOLTAGE REFERENCES !
L
L --.l
- O~RLOAO ~ECTOR_ - _ -
. L......I
--.l - ct-
®..J.... - L... 9- - - -1 - - - _ - - - _ _ - ..J
GROUND (SUBSTRATE) ZENER HORIZONTAL RESISTANCE VALUE ARE IN OHMS.
REFERENCE KEYING INPUT
Fig. 7- Compillre circuit d/afyam mowing dIItlli/s of thll bylng circuit
IIIId int.,,,,,1 bias circuits.
________________________________________________________________ 525
ICAN-6257
linearity improves as the bandwidth increases; however, measuring distortion. The coupling may be varied by either
-
l
~. ,,~
24 recowred audio decreases. A satisractory compromise for moving the coils or by changing the value or the secondary
ti: 23 most FM-receiver applications is reflected in the circuit of load resistor.
I 22 ~---t-~-~-
REIVT
r-- t--- Fig. 9(a). This circuit typically provides 400 millivolts rms of
recovered audio with less than [Link] distortion.
Various circuit values can be used to obtain the same
recovered audio. but the basic conditions of circuit
i f---- --~
Because a double-tuned circuit has better phase linearity <*r
a wider bandwidth, distortion figures ofless than O.I-percent
are attainable with the network used. in the circuit of Fig.
bandwidth and phase linearity must be maintained. The
detector circuit also sets up conditions which are required for
proper operation or the mute circuit. The rf voltage on pin 9
9(b). Proper alignment and coupling adjustment of the must be held at approximately 175 millivolts nns, ±25
.g ·2. 1----- - --- double-tuned circuit are most easily accomp1ished while millivolts. The reason for this requirement is discussed
viewing the resulting S curve. Initial adjustment of the
", subsequently in connection with the mute logic circuit. The
~~ primary tuning sJug to the proper crossover is made with the approximate voltage at pin 9 is determined rrom the
,. .. ~~~
.-..
0 AFt VOiTAGE-pr 7-10 rROSS secondary slug removed. The secondary tuning slug is then equivalent circuit shown in Fig. 10.
~~ -20
-4. -20
• The [Link]-peak voltage on .pin 9 is:
T[MPERATURE-·C
'" 100
I V91"'I V81-;J;
Fig. 1- SuppJv cummt and AFC voItIIgIIM a function of tflmptJI'lIttJnI.
where Rl is the total parallel resistance and V8 is
approximately 300 millivolts, peak-to-peak.
exhibit inductive reactance at their terminals. The nominal
mput impedance of the CA3089E is approximately 9,000 The Q of the tuned circuit between pins 9 and 10 may be
ohms, and it is not recommended that an impedance match affected by the effective Q of the choke between pins 8 and
be attempted. Most commercial receivers use ceramic-filter 9 and the series resistor R31 in the CA3089E. All of the
frequency-selective elements that normally have source above factors should be considered in selecting circuit values.
impedances or 500 ohms or less. When these fdters are Table I lists some typical combinations of component values
properly terminated with loading resistors, the typical source under various conditions.
impedance is rurther decreased to 250 ohms or less. Higher A choke is normally selected to equalize delays in the
levels of source impedance are possible with very careful signal path and in the limiter-quadrature path. It also
circuit layout; however, the maintenance of stability could reduces the ir harmonic content across the quadrature
be diffICult. circuit. In some cases, such as in narrow-band applications, it
may become necessary to use a capacitor as the coupling
The CAJ089E has a rrequency response that is typically
component where large values or inductance with high Q's
flat to 20 MHz; consequently, the device can provide userul
are difftcult to obtain. If a capacitor is used, the phase or the
gain wen
above that frequency. If the device is used at lower ALL RESISTANCE VAlUES ARE IN OHMS
*l TUfES WITH 100 pF ICI AT 10.7 NHE recovered audio and AFC voltage will be reversed, some
rrequencies, the larger-value bypass capacitors required may 00Iu"'1..0"oa))-7$ 16.1. AUTOMATIC MFG. 01V. EX22741 OR EQUIVALENT)
asymmetry of the S curve may result, and the distortion may
not be adequate to bypass tbe higher frequencies. Double
be adversely affected to a small degree.
bypassiDg with lower-value capacitors can overcome such a
ploblenL Another means of allOYiating the problem is 10 As indicated above, the inductance between pins 8 and 9
externally reduce the frequency tesponae by using a smaU I.) tends to equalize delays in the detector signal paths. The
capacitance across the output load of the device. matching of elemen ts of the IC in the balanced detector
~
i "~"
.twmin• ."",oxi"",,. von.,. on
Fig. 10- EquiWlltmt cimuit used to
pin 9 of tM CA3089E in Fifo 9.
circuit results in an AFe output with a very small offset
when referred to the voltage at pin 10. For most
applicatiOns, the inherent offset variation is well within
a) Bottom villW of printlld-circuit board.
tolerances, and does not affect circuit perrormance. ]n some
narrow·band applications, however, the offset becomes more
critical because of the very narrow bandwidth. In such
situations. the combination or normal production variations
of the device and the external circuit components results in
receiver detuning when the AFC loop is closed. This detuning
results in an increased distortion or the recovered audio. This
ALL RESISTANCE VAlUES AfiE IN OHMS
distortion can be corrected with the addition or a variable
*T:PR1.-00IUNlOADEDIIil'SCTUNES WITH 100 pF ten 201 OF 34. ON 7/!2MOIA. f'ORM
SEC.-00(UNlOAOEDI1I75 (TUNES WITH 100 pF IC2) 201 OF 34e 0lIl 7/32" OIA. FORM capacitor from pin 8 to ground to provide phase
kQ(PERCENT OF CR1T1CAL COlIPLiNGIIi TO% compensation. The capacitor can be adjusted to provide zero
(ADJUSTED FOR COIL VOLTAGE Vc;lol5Q rtN
AFC offset with minimum distortion. Generally, the orrset is
ABOVE IJALlJES PERMIT PROPER OPERATION OF MUTE lsaUELCtlI CIRCUIT
"E" T'HIE SLUGS,SPACING 4 ... "" in one direction ror a given set of conditions. The addition of
a fIXed capacitor will minimize variations sufficiently to
bl Components/de -!UP view. (b) satisfy many applications. A value or 5 picorarads is an
effective value for the circuit or Fig. 9(a) with the
"'" 8.-. CA3OB9E Md ourIJoenI ~tJ mountlld on.
pdnred cin:ult boen/..
recommended PC-board layout. Conversely, the ofrset
Fig. 9- (a) Ten c;n;uit for tlHl CA3089E using a sin....tunlld dBtector
.coil, (b) at circuit for ,l1li CA3D89E wing a doublfl-tuned created by using a capacitor between pins 8 and 9, as
.tectorcoil. mentioned earlier, may be compensated by placing an
O"....nt-Det8ctor Ciroui'll inductance between pins 8 and 10.
The quadrature-detector tuned circuit is connected
between pins 9 and 10. The signaJ voltage at pin 8 is adjusted until '8 slight "ripple" is observed moving along the Audio .,d AFC CircuitS
normally coupled to pin 9 throush a choke. The circuit S curve. If the ripple is excessive (enough to distort the S The audio and AFC circuits are very similar, and both
values for the detector network are determined by several curve) the coupling is too tight. If no ripple is observed. the develop the same audio signal at their respective output
ractors, the primary one being distortion at a particular level coupling is too loose. As the ripple moves through the terminals. The audio output voltage on pin 6 is developed
of recovered audio. Distortion is determined by the phase crossover point, it will be observed that the S curve becomes across an internal. nominal. 5.000·ohm resistor ·CR49)
linearity of the quadrature network and is not influenced by more linear near the center frequency. Slight readjustment of connected to the 5.6-volt reference. In addition, the audio
the device unless excessive. recovered audio overdrives the both slugs may be necessary for final alignment. The best signal level can be attenuated by providing' a direct current
audio circuit With a Single tuned network, the phase performance can then be achieved by slight adjustment while into pin 5 without any shift in its dc level. The audio output,
________________________________________________________________ 527
ICAN-8257
455 kHz without the use of external c:ircuilly. The rf-AGC components are necessary_ The CA3089E, operating in distortion at pin 6. This teedback technique resuJts in a very
and mute logic <in:uits do nat develop BUtTlCiont de voItqe conjunction with an inexpensive operationaJ low distortion modulation. The rf output of the CA3089E at
transconductance [Link].4.S provides means of locking the pin 8 is essentially a square wave, and is fed to a
tuned circuit to the incoming frequency. Fig. 17 shows the tuned-amplifier stage to buffer the signal and restore the
block diagram of such a system. The AFC output voltage sine-wave--shaped rf output signal.
developed across the resistor between pins 7 and lOis
amplified by the op-amp and drives a varactor to maintain
the tuned frequency on the incoming--signal frequency.
AcIaw ........ '11
The author thanks Jack Ctaft for his lid and IU_ _ in
mony discussions and Frank Curley for his lid in circuit
construction and collection of data.
Biblio......y
I. "Advances in FM Receiver Design," J. Avin.. IEEE
Transactions on Broadcast and TV Receivers, Aua..
1971.
2. "High-Perfonnance FM Receivers Using High-Gain
Fig. "~[Link], f",quencv-stabiIiZllDon circuit. Integrated-Circuit IFIAmplifiers," T J. Robe, L Kaplan
IEEE Transactions on Broadcast and TV ReceiveR,
Sept. 1966.
Fig. 15-$uggtImHI PC-btwd patt8m and pam layout for the cin:uit
The CA3089E may also be used as the core of an 3. RCA Data Bulletin, File No. 595: CA3096 NPN/PNP
ofFi.,4, ultra-linear PM generator; Fig. J8 shows the circuit. The Transistor Array IC.
carrier is generated by the CA3089E with the introduction of 4. RCA Data Bulletin, Fne No.4 75: CA3080 Operational
to perform their functions, and the meter output signal loses feedback from the output teoninal, pin 8. The carrier is Transconductance Amplifier.
its logarithmic characteristic and exhibits peaks and valleys as modulated by the varactor connected across the tuned circuit S. "Applications of the CA3080 and CA3000A
input signal is increased. Operation of the ff-AGe and mute at the input of the CAJ089E. The varactor is driven by the High-Performance Operational-Transconductance
logic circuits may be enhanced by the addition of a de output of the differential amplifier, AI, using a CAJ028 Amplifiers," H.A: Witt1inger, RCA Application Not..
amplifier and inverter to each circuit. A simple example using IC.6,7 This differential-amplifier stage is driven at one ofits ICAN-6668.
a C A3096E Ie transistor array is shown in Fig. 16. 3 input terminals by the audio modulating signal. Neptive 6. RCA Data Bulletin, File No. 382: CAJ028A,
The CA3089E may be used effectively in narrow-band feedback of the audio signal is provided by driving the other Differential/Cascade Amplifien.
communication receivers. In double-conversion receivers, differential-amplifier input from the recovered aumo output 7. "Application of the RCA CAJ028A and CAJ028B
some of the functions of the CA3089E are negated at a of the CA3089E at pin 6. The detector circuit uses a Integrated Circuit RF Amplifiers in the HF and VHF
455-kHz intermediate frequency. However, if a 1O.7-MHz double-tuned transformer to produce audio with very little Ran!!"s," RCA Application Note ICAN-5337.
intennediate frequencY is used, all of the auxiliarv featwes
+12V
OUTPUT
+12V aOI~F ~
MODULATION
INPUT
'H~·. nl~ ~
IO~F
Fig. '6-Extemlll mute and rl·AGC drilllJ circuits fo, the CA3089E .,V noG.I. EX23656
lIo 54 TtlRNS Mo. 56 WIRE
operating at 455 kHz. External transistors are parts of the
CA3096E n-p-nlp-n-p tran6istorsrrsy.
" TAP AT 5 TURNS
TYPE "[-COftE
may be used, but another set of problems is encountered.
The small deviation signals encountered in narrow-band
systems require the use of high-Q circuits in the quadrature
detector, as indicated in Table I. However, variations in
external-component parameters with temperature changes
may cause the tuned frequency of the detector to drift out
of the if pass band. Normally temperature-compensated
________________________________________________________________ 529
leAN-a3G3
TYPICAL
INTERSTAGE this composite waveform drive the keyed agc amplifier Q27.
BANOPASS CIRCUIT
which in turn drives Q28. Without a video rf signal there is no
video signal output. and Q27 conducts during the keying inter-
vals (the horizontal pulse is connected to terminal 3). As the
detected signal level increases in amplitude and the output
voltage at terminal 19 approaches its typical operational level of
7 volts peak-to-peak, the peak potential at the base of Q27
begins to fall below 0.8 volt. Under these conditions, the keying
current formerly channeled through Q27 is diverted through
diode D4. As the signal level rises even higher, a greater portion
of the Q27 collector current is diverted through 04, and the base
current to Q28 is proportionately increased. A la-microfarad
capacitor is normally connected between terminal and ground
and is, by this connection, put in shunt with Q28. The charge on
this external capacitor is maintained through a bleeder resistor
to V+. As the base current to Q28 increases.Q28 discharges the
capacitor at a rate that is proportional to the base current of
Q28. Integration of the total charge on the capacitor over the
keying interval yields a dc level (agc voltage) that is inversely
proportional to the incoming signal level; i.e., agc voltage
approaches zero as the signal increases.
Any high·performance age-system must have noise-immunity
characteristics in order to avoid the establishment of false agc
levels. AGC voltage developed from random noise can produce
"wash-out", "blank raster" and/or a momentary ·'Ioss of sync" .
The CA3068 is designed with an improved noise-immunity
circuit that essentially removes the keying current during
periods of high noise input. The active devices responsible for
providing protection against this deleterious effect of the im-
pulse noise are the "noise detector", Q29, and the "noise clamp"
Q31 , which is driven by Q30. Impulse noise is channeled through
the high-pass filter network consisting of CIa and R36 to the
detector input Q29. Q29 and C II comprise a conventional peak
detector. The dc level across C II. which is proportional to the
level of impulse noise. turn on Q30 and Q31, thereby clamping
the keying supply voltage (terminal 3) to ground. In actual oper-
ation. the terminal-3 supply has a series resistance that is large
enough to limit the peak current into the zener diode (Z5) to
'OR' approximately 0.8 milliampere. When Q31 conducts, it shunts
KEY PULSE
this current to ground.
The sound-if-channel and PIX-IF-channel signals whose
"carrier" frequencies are 41.25 MHz and 45.75 MHz, respec-
tively, are applied to terminal 12. Q32 functions as a buffer
between the interstage-tuned-circuits associated with ter-
minal 12 and the PIX/sound-channels amplifier .Q33. The inter-
Fig. 2. Detailed block diagram of the CA3068 together with its peripheral tuned circuits. carrier frequency (the difference frequency between the PIX
and sound "carrier" frequencies) is detected by the peak de-
tector Q34 and C12. The resultant 4.5 MHz PM sound·inter-
2~OIl 3 RO PIX'I F VIDEO
:p~~~!~J~Y:~L::R~l carrier signal is fed to transistor Q35. This transistor and Q36
j" :
WIDE BAND AMPLIFIER DETECTOR
INOIs[~UN!TVI form a differential pair that provides an amplified intercarrier
sound·if signal to the base of Q37. A feedback system through
the RC networks in the Darlington emitter-follower output of
-I
" 1 Q37 provides bandpass shaping in the region of 4.5 MHz while
" I maintaining a low dc gain. The low level of de gain is desirable
~ 1
I because the circuit receives its bias in an open-loop manner from
terminal 16. The bandpass of this amplifier system is fairly
1 1
1 1
broad. and even though it is optimized for 4.5 MHz operation.
I there is relatively high output at other intercarrier frequencies,
1 as shown in the curve in Fig. 4.
,I
I
1
1
1
1137 1
710 I
.1
I
1
1
1
1
1
1
---{j)1
1 FREQUENCY IN MHz
1
Rl,,,g 1
1 Fig. 4. Relat;ve sound·carrier output as a function of frequency.
1
TUNERAGc; [Link] 1 The internal zener reference-diode consists of the series diode
10ElAVI
1 arrangement shown connected between terminal 18 and the sub·
Fig. 3. Schematic diagram of the CA3068. strate in Fig. 3. A regulator-circuit configuration showing the
__________________________________________________________________ 531
ICAN-6303
itor connected between terminal 4 and ground. An RC de- which causes more current to flow through the collector circuit, between the tuncr and thc if 'iI:Jgc. Parasitic resonance and
coupling network smooths the agc ripple associated with the so that a positive (or forward) agc potential is generated for the couplings hav~ been mininll:led to maintain a high degree of
charge and discharge of the I O-microfarad capacitor at the hori- bipolar transistor in the tuner. attenuation at frequende~ remote from the if-resonance fre-
zontal-oscillator frequency rate. The age system is normally quency.
keyed from the horizontal-output circuit in the TV system. This The interstage double-tuned bandpass circuit, with a bifilar
keying pulse should be applied to terminal 3. The magnitude of TV RECEIVER PIX-IF CIRCUIT APPLICATIONS T-trap at 41.25 MH:l. is similar to that commonly used in the
the pulse should be sufficient to supply a nominal peak current third stage of color-TV receivers. The sound and ph:ture carriers
value of 0.8 milliampere into terminal 3. The value of the series In this section, the application of the CA3068 integrated arc present lit the input (terminal 12) to the 4.5 MHI. sound-if
resistor Rs associated with terminal 3 may be computed as circuit in a color and a monochrome TV receiver is described_ detector cin:uit. Trapping action removes Ihe41.25 MHz sound
follows: During the conduction period (with keyingapplied~ the The circuits shown were constructed on [Link] copper PC
carrier at terminal 13 to prevent a differt!nce-frequency beat of
constant-voltage components within the integrated circuit boards.
0.92 MHz with the chroma subcarrier at 42,17 MHz. The picture
account for: As previously noted, because of the high gain encountered in
carrier and chroma subcarrier entering terminal 13 are ampli-
PIX-IF design, positive feedback must be avoided if the
fied. detected, and additionally amplified as detected video
amplifier is to remain free of spurious oscillation_ To this end,
Vk = H.2 V signai. If the sound carrier is not attenuated by the 41.25 MHz
the optimization of printed board layout and component place·
(It is assumed that 13:;; O.H mAl trap, the carrier will be detected as a large 4.5 MHz differ-
ment is essential. The pIOper choice of bypassing components
ence-signal in the video output. A 4.5 MHz trap (T5) is included
If the keying·pulse magnitude, Vp ' is 15 V. then: and signal-path layout is necessary to avoid feedback thIOugh
to prevent interference of a residual 4.5 MHz intercarrier signal
ground loops.
IJ=[Link]= 15 Vk (15 XciV in the chroma and luminance circuits.
IF CIRCUIT FOR COLOR TV RECEIVER The chroma peaking circuit compensates for the slope of the
R,; Rs
video response, as shown in Figs. II (a), II (b) and II (c). The
The schematic diagram of an if system for a color-TV re- actual slope and shape of the Video response between 3.08 MHz
Rs = X.s kilohms ceiver is shown in Fig_ 10. A parts list and illustrations showing and 4.08 MHz will vary because of normal component tolerance.
the PC-board component layout (top view) and the actual The chroma-peaking coil, L7. has two cores, one to adjust in-
The sound output is derived from terminal 2 at II level com-
printed circuit (bottom view of board) are shown in Appendix ductance to center the response at 3.58 MHz, and the other to
patible with the input requirements of a TV-sound-if-subsystem
A. Since most current color-TV receivers employ automa- adjust chroma output level and bandwidth. The latter core
IC, such as the RCA CA3065_ There is also a de component of
tic-fine-tuning (AFT) systems, an AFT system using the CA3064 controls circuit Q with little effect on over-all inductance.
approximately 6.7 volts present at terminal 2. Coupling net-
has also been incJuded on the same board; Fig, 10 incJudes the Photographs of the detected sweep-response characteristics
works to subsequent circuits must contain a suitable dc-blocking
AFT circuit. are shown in Fig. 12. The sweep-response of Fig. 12 (0 shows
capacitor. The if-response is determined by the triple-tuned circuit, the interstage alignment from TP3 (of Fig. 10) to terminal 9 of
Small chokes located in the sound and video outputs which consists of three traps: two preceding the IC and an inter- the (' A3068. The sweep-response curves in Figs,,12 (a) through
(terminals 2 and 19) should be self-resonating at the inter- stage double-tuner circuit with one trap. In the [Link] 12 (e) show 60 dB ofagc range from a level of 100 microvolts
mediate frequencies to prevent ifleakage into subsequent stages. circuit, the two bridge-T traps are used to provide attenuation of (Fig. 12 (e» to 100 millivolts (Fig. I::! (a)).
The (' AJ06X if subsystem has an internal zener refer- the adjacent-channel picture carrier (frequency 39.75 MHz) and The alignment procedure for the color-TV PIX-IF system
ence-diode that permits operation of the subsystem with an adjacent-channel sound carrier frequency (47.25 MHz). A using theCA3068, Fig. 10, is given in Appendix A.
external voltage-regulator pass transistor. A suggested circuit
arrangement is shown as part of the over-all if schematic
diagram in Fig_ 5 (b). The voltage-regulator pass-transistor has a
nominal output voltage of 11.2 volts. Bypassing of the V+
supply with reference to the if subsystem is important, and the
suggested arrangement shown in the application circuit (Fig. 10)
should be used. Specifically, terminal 15 should be bypassed to
terminal 17 on the CA3068. Even though terminal 17 is at dc
ground potential, it should not be tied to ground but rather
should be bypassed in the manner shown to avoid mutual im-
pedance coupling within the CA3068.
MONOCHROME TV
The delayed-agc circuits used in the CA3068 were originally
intended to control a MOSFET in the rf-stage of the TV tuner.
This arrangement permits direct application of the delayed-agc
voltage from the CA3068 to the tuner. In monochrome
receivers, however, it is common practice to employ a bipolar
transistor in the rf-stage of the tuner, and a circuit with a "for-
ward"-agc characteristic is required to control the rf-stage. This
characteristic is easily established by means of an inverter net-
work utilizing a p-n-p transistor, as shown in the circuit of Fig. 9_
Fig. 10_ Schematic diagram of a typical application of the CA3068 to a PIX-IF circuit for a color- TV system.
A template of the printed circuit board used to construct this circuit, a diagram of the position of
all components on the board, a block diagram of the location of major components on the board,
and a circuit pa,.ts list are given in Appendix A.
common bridge impedance consisting of parallel-connected Ll I F CIRCUIT FOR MONOCHROME TV RECEIVER
and R2 is used. Adjustment ofLl for best null of the 47.25 MHz
trap assures the desired 60-<lB minimum attenuation, The schematic diagram for a PIX-IF system for a mono-
The triple-tuned circuit provides, at center frequency. a chrome TV system that employs the CAJ068 is shown in
source resistance to the IC of 800 ohms and a voltage gain of Fig. 13. A PC-board component-layout diagram (top view), the
three from the input to pin 6 of the Ie. The first section of the actual printed circuit (bottom view of board), and a circuit parts
triple-tuned circuit consists of L2 and C6. Capacitor C6 is in list are shown in Appendix B. A sound-if system using the
parallel resonance with coil L2 at 44 MHz. The third section of CAJ065 has been included to show the simplicity with which it
Fig. 9. Block diagram of an if system fa,. a monochrome re- the triple-tuned circuit consists of coil lA and capacitor C14. can be used in conjunction with the CAJ068.
ceive,. showing pe,.iphe,.al age circuit. Coupling and voltage-gain from L2 to lA are provided by the The selectivity is provided in two sections, an input
As the input signal level increases, the forward-agc delay voltage second section, coil L3 and capacitors CIO, CII, and C12. The single-tuned circuit with trap, and a double-tuned interstage
is developed at the tuner when the voltage at terminal 7 of the inductive reactance of L3 is made 75 times larger than that of L2 circuit. The resistive pad, RI, R2, and R3 of Fig. 13, is used to
CA3068 decreases. The agc voltage applied to the rf-stage of the to provide a high degree of tuned-circuit isolation for ease of terminate the link-cable and isolate cable effects from the high-Q
tuner (Fig. 9) is derived from the collector of the p-n-p tran- alignment. input circuit. The bridge-T trap-circuit is used to give maximum
sistor. As the delay-agc voltage is generated at terminal 7 of the The circuit provides protection against interference resulting attenuation to the adjacent-channel sound carrier. Precision
CA3068. the base of the p-n-p inverter is driven into conduction, from a strong rf signal which might inadvertently be introduced components (R2, C1, C2) achieve a good null at 47_25 MHz
___________________________________________________________________ 533
ICAN-8303
Alth(IUgh this Application N(llc dcst.:ribcs subsystcm designs Color-Circuit Parts List Monochrome-Circuit Parts List
in TV rel.:civers. Ihe ('AJ06~ IS also applil.:able in AM wmllluni·
t.:ations systems requiring pcrrurmanl.;'c al frequcndeswithin thc Resistors (All values in ohms) Capacitors
Capacitors
range of 10 1070 MHz.
RI 18 CI 3.0pF
CI [Link]~F
[Link] R2 20 C2 3.0pF
C2
5.6pF R3 33 C3 6.8pF
C3
REFERENCES 3.3pF R4 10 C4 3.9pF
C4
C5 [Link]~F
C5 [Link] R5 2.7k
I. RCA l):II:J Bullctin file No ..Nil ~'onccrning Ihl' CA.H)h4 3.3k C6 12~F
C6 300pF R6
C7 [Link]~F
:Jlld CA30h4E, "TV AUloJllatk Fine Tuning Circuit". or the CIO 16pF R7 100
RCA DATABOOK. 1975 Series SSD·20IC. C8 [Link]~F
CII IIpF RS 15k
, RCA Data Bulletin Filc No. 412 cOlll:crnillg the ("A.~0l15. CI2 1.6pF R9 39k C9 6.8pF
CIO [Link]~F
"TV IF Sound SY~lell1", or the RCA DATABOOK, 1975 CI3 [Link]~F RIO 120k
Series SSD-20tC. CI4 47pF RII 4.7k Cli 20pF
3_ RCA Data Bulletin File No. 467 cont.:erning the CA3068. CI5 [Link]~F RI2 10k CI2 15pF
CLl [Link]~F
"Television Video IF System",or the RCA DA1ABOOK. CI6 IO~F RI3 2.2k
1975 Series SSD20 I C. CI7 [Link]~F RI4 4.7k CI4 ISpF
CI5 [Link]~F
CI8 [Link]~F RI5 8.2k
CI6 [Link]~F
CI9 7.5pF RI6 330
CI7 [Link]~F
C20 1.6pF RI7 Ik
APPENDIX A- THE COLOR CIRCUIT CIS 5~F
C21 [Link]~F RI8 330
C22 3.6pF RI9 Ik CI9 4700pF
ALIGNMENT PROCEDURE FOR THE COLOR CIRCUIT C20 68pF
C23 220pF R20 2.7k
C24 [Link]~F R21 Ik C21 12pF
Preliminary Adjustments and Calibration C22 4pF
C25 IIpF R22 330
C26 O.022~F R23 1.2k C23 82pF
I. Adjust delay-age (noise pot) fully cw. C24 0.047~F
C27 680pF R24 Ik
2. Connect supplies as indicated on schematic diagram C25 0.047~F
C28 120pF R25 Ik
(Fig. 10), set bias to zero. C26 [Link]~F
C29 180pF R26 2.2k
3. Set sweep generator to 10 millivolts as indicated on Boonton C27 0.047~F
C30 0.022~F R27 47
91 DA meter with 56-ohm termination.
C31 56pF R28 3.3k
C32 220pF R29 25k
Step '-IF Interstage Alignment
C33 130pF
a. Ground TPI with short clip lead. C34 62pF Inductors RCA Stock No.
b. Connect sweep generator with 56-ohm termination and C35 82pF
IOOO-picofarad decoupling capacitor to TP3. C36 [Link]~F LI 131655
c. Connect oscilloscope to video output. C40 IOOOpF L2 133463
d, Adjust bias for 5-volt peak-to-peak response on oscilloscope. C41 I000pF L3 I.O~H
e. Adjust bottom core ofT4 for minimum at 41.25 MHz. C42 lO00pF lA 12.0~H
r. Adjust L5 and L6 for symmetrical response with PIX and L5 134754'
color markers equal (Fig. 12 (a)): L5 controls markers and 1.6 131465
L6 controls tilt. L7 133546
g, Adjust top and bottom cores of 14 simultaneously. top core L8 130120
for maximum rejection of 41.25 MHz and bottom core to Inductors RCA Stock No. L9 130121
maintain minimum 41.25 MHz,
LI 132159 ·(9 turns No. 23 wire; use 1/2 W resistor to form coil)
Step 2 -I F Overall Alignment L2 132161
1.3 132839
a.
Leave ground clip lead on 1Pt.
lA 132658
b.
Remove sweep input from TP3.
15 137126
c.
Connect TP2 through a l000-picofarad capacitor to TP3.
1.6 132146
Connect sweep generator to input.
d.
TI 132839
Readjust variable bias to maintain S-volts peak-to-peak
e.
T2 132157
response on oscilloscope. Resistors (All values in ohms~
T4 132150
f. Adjust TI for minimum 39.75 MHz.
T5 132135
g. Adjust T2 for minimum 47.25 MHz, RI 18
h. Adjust L2 for equal height of PIX and color markers. R2 27
i. Remove ground-clip lead from 1Pt and IOOO-picofarad R3 91
capacitor from between TP2 and TP3. R4 15k
j. Maintain,5-voits peak-to-peak response on oscilloscope by re- APPENDIX B - THE MONOCHROME CIRCUIT R5 3.3k
adjusting bias. R6 10k
k. Adjust L3 and L4 simultaneously for symmetrical response ALIGNMENT PROCEDURE FOR THE R7 LOk
with PIX and color markers equal: lA controls markers and R8 33k
MONOCHROME-CIRCUIT
L3 controls tilt. R9 51k
Adjust bandpass trimmer, CI2, to place PIX and color mark- Step ,- RIO 270
ers at 40 percent while readjusting L3 and lA (Fig. 12 (b ». I. Connect +20 volts to appropriate points on board.
RII 2.2k
m. Re·adjust Tl for minimum at 39.75 MHz if necessary. RI2 120k
n. Re-adjust T2 for minimum at 49,25 MHz. Then adjust L2 to 2. Connect sweep generator to input
3. Connect dc bias voltage to appropriate point on board. RI3 2.2k
maximize the rejection at 47.25 MHz, RI4 15k
4. Adjust sweep generator for to-millivolt input.
RI5 25k
5. Adjust bias voltage for 5-volt. peak-to-peak output.
AFT Alignment RI6 8.2k
Step 2- RI7 2.2k
a. With oscilloscope on AF1 output, adjust bias for 100voits RI8 3.3k
peak-to-peak response. l. Adjust LT for minimum response at 47,25 MHz. RI9 150
b. Adjust 1.8 for maximum 45.75 MHz. 2. Adjust L2 for maximum at 44.5 MHz. R20 56
c. Adjust L9 for crossover at 45.75 MHz. 3. Adjust L6. L7 for bandpass shown in Fig. 14 (b), The R21 36
d. Re-adjust 1.8 and L9 to obtain symmetry. curve should have 3-MHz bandwidth centered at R22 220
e. Adjust 1.8 to obtain maximum width. 445 MHz. R23 5.6k
__________________________________________________________________ 535
ICAN·6303
1 CA""'I L:J o
2N2102
THE MONOCHROME CIRCUIT o I CA306S1
o
LI
=RIO
DELAY
AGe
________________________________________________________________ 537
leAN-6668
figuration is used to minimize capacitive feed-through shows an oscilloscope photograph of the output of the Once the signal is acquired, variation in the stored-signal
coupling via. the base-collector junction of the p-n-p multiplexer with a 6-Y pop, sine wave signal (22 kHz) applied level during the hold-period is of concern. This variation is
transistor. to one amplifier and the input to the other amplifier primarily a function of the cutoff leakage current of the
Another multiplex system using the OrA's clocked by a grounded. This photograph demonstrates an isolation of at CAJ080A (a maximum limit of 5 nA). the leakage of the
COS/MaS flip-flop is shown in Fig. 6. The high output least 80 dB between channels. storage element, and other extraneous paths. These leakage
voltage capability of the COS/MOS flip-flop permits the currents may be either "positive" or "negative" and,
circuit to be driven directly without the need for p-n-p Sample--and-Hold Circuits consequently, the stored-signal may rise or fall during the
level-shifting transistors. An extension of the multiplex system application is a "hold" interval. The term "tilt .. is used to describe this
A simple RC phase-compensation network is used on the sample-and·hold circuit (Fig. 9), using the strobing character- condition. Fig. II shows the expected pulse "tilt" in
output of the OrA in the circuits shown in Figs. 5 & 6. The istics of the OTA amplifier bias-current (ABC) terminal as a microvolts as a function of time for various values of the
means of control. Fig. 9 shows the basic system using the
values of the RC-network are chosen so that 211~C =::!MHz.
CA3080A as an OTA in a simple voltage-follower configura-
compensation/storage capacitor. The horizontal axis shows
three scales representing leakage currents of 50 nA, 5 nA,
tion with the phase-compensation capacitor selVing the 500 pA.
additional function of sampled-signal storage. The major con-
sideration for the use of this method to "hold" charge is that
neither the charging amplifier nor the signal readout device
significantly alter the charge stored on the capacitor. The
CA3080A is a parttcularly suitable capacitor-charging ampli-
fier because its output resistance is more than 1000 Mn.
under cut-off conditions, and the loading on the storage
capacitor during the hold-mode is minimized. An effective
solution to the read-out requirement involves the use of an
RCA 3N 138 insulated-gate field-effect transistor (MOS/FET)
in the feedback loop. This transistor has a maximum
gate-leakage current of 10 picoamperes; its loading on the THISSC~A~LE
000, FOR
charge "holding" capacitor is negligible. The open-loop
10
0,.
voltage-gain of the system (Fig. 9) is approximately 100 dB if '0"
LEAKAGE
v- --lOY the MOS/FEr is used in the source-follower mode to the I 10 100 10K
10 100 IK lOOK
(NO SUPPLY BYPASSING CA3080A as the input amplifier. The open-loop output 100 IK 101C lOOK 10001(
SHOWN)
impedance ttn) of the 3N 138 is approximately 220 n.
PULSE TlLT- ..V
Fig. 11- Chart showing "tilt" in _mple-and-hold potentials
because its transconductance is about 4,600 ~.mtho at an as a function of hold time with load capacitance a.
operating current of 5 rnA. When the CA3080A drives the a parameter.
3N138 (Fig. 9), the closed loop operational-amplifier output
CLOCK 2ku
impedance characteristic Fig. 12 shows a dual-trace photograph of a triangular
_~:UNPUT Z ::..: Zg (open-loop) signal being "sampled and-held" for approximately 14 ms
8
out - A (open-loop voltage-gain) with a 300 pF storage capacitor. The center trace (expanded
to 20 mV/div) shows the worst-case "tilt" for all the steps
Fig. 6- Schematic diagram of a two-channellinear multi- " ~~~d~ '" 22~ 12", 0.0022 12 shown in the upper trace. The total equivalent leakage
10 current in this case is only 170 pA (I =C~).
plex system using a COSIMOS flip-flop to gate two
OTAs.
This RC-network is connected to the point shown because
the lowest-frequency pole for the system is usually found at
this point. Fig. 7 shows an oscilloscope photograph of the
multiplex circuit functioning with two input signals. Fig. 8
SAMPLE OVli TOP TRACE"SAMPLED SIGNAL I Y/DIV a 2Dmll~IDIV
HOLO -I~\I CENTER TRACE WORSE CASE TILT ZOmY/DIV &
Y-:-15V 20m5e~/DIV
Fig.9- Schematic diagram of OTA in a sample-and-hold
circuit. Fig. 12- Oscilloscope photo of "triangular·voltage" being
sampled by circuit of Fig. 9.
Fig. 10 shows a "sampled" triangular signal. The lower
TOP TRACE:MULTlPLEXEO OUTPUT IV/DIY a
IOOI'HC/DlY
trace in the photograph is the sampling signal. When this Fig. 13 is an oscilloscope photograph of a ramp voltage
BOTTOM TRACE:TlME EXPANSION OF SWITCHING signal goes negative, the CAJ080A is cutoff and the signal is being sampled by the "sample-and-hold" circuit of Fig. 9.
BETWEEN INPUTS 2V/DIV 80
5,..sec I OIY "held" on the storage capacitor. as shown by the plateaus on The input signal and sampled-output signal are superimposed.
Fig. 7- Voltage waveforms for circuit of Fig. 6,. top trace: the triangular wave-fonn. The center trace is a time The lower trace shows the sampling signal. Data sliown in
multiplexed output· lower trace: time expansion of expansion of the top-most transition (in the upper trace) Fig. 13 were recorded with supply voltages of ± lOY and the
switching between inputs. with a time scale of 2 [Link]/div. series input resistor at terminalS was 22 kil.
6 ZO..,..c/DIV
TOP TRAC[:SAMPLED SIINAL IV/DIY
TOP TRACE'I V/DN a IOO,."c/OIV -OUTPUT CENTER TRACE'~~~~R~I02N'::c~R SIGNAL TOP TAACE'JNPUT AND OUTPUT SUPERJMPOS£O
BOTTOM TRACE: VOLTAGE EXPANSION OF OUTPUT IY/DIV a 2,l<.5ec/OIV
BOTTOM TRACE: SAMPLING SIGNAL 20V/DIY 6
ImY/DIV a 100I'MC/OIY ISOLATION 20~'tc/DIY BOTTOM TRACE SAMPLING SIGNAL 20V/01V a
IS IN EXCESS OF 80 db 2JLuc/OIV
Fig. 8- Voltage waveforms for circuit of Fig. 6,. top trace: Fig. 10- Waveforms for circuit of Fig. 9,- top trace: sampled
output· lower trace: voltage expansion of output· signal: center trBc9: top portion of upper signal: Fig. 13- Oscilloscope photo of "ramp·voltage" being
isolation in excess of 80 dB. lower trace: sampling signal. sampled by circuit of Fig. 9.
__________________________________________________________________ 539
leAN-eee8
the dn:uit of Fig. 20 as an emitter-follower to drive the p-n-p
transistor. variations due to base-emitter characteristics are
considerably redu..:ed due to the ..:omplemenlary nature of
the n-p-n base-emiller jun..:tions. Moreuver. Ihe temperature
..:oeflidents of the two base-emitter jun..:tions tend to cancel
one another. Fig. ~I shows a l'onfiguralion using one
transistor in the RCA type (' A.'O I MA n-p-n transistor-array as
TOP TRACE;MODULATlQN FREQUENCY INPUT
=201lOlTS P-PII50f/oSlC/DIV
CENTER TRACE AMPLITUDE MODULATE OUTPUT
500",WDIV II 5O,.SlC/OIV
Fig. 24- OTA analog multiplier drilling an op-amp that
BOTTOM TII:[Link]:PANOED OUTPUT TO SHOW operates as a current-to-volrage converter.
DEPTH OF MODULATION 20",VlOIV
II 50f/oSlC/DIV
Fig. 25 shows a schematic diagram of the basic multiplier
with the adjustments set-up to give the multiplier an
accuracy of approximately ±7 percent "full-scale". There are
only three adjustments: I) one is on the output, to
Fig. 21- Amplitude modulator using OTA controlled by
p-n·p and n-p-n transistors.
TO P TR A CE: MODUL ATiON FREQUENCY INPUT
20 YOL T5 II 50,.5ec/DIV
BOTTOM TRACE· AMPLITUDE MODULATED OUTPUT
500mV/DIV II 50-",!It!~/OIV
an input entitter-follower. with the three remaining tran-
sistors of the transistor·array connected as a current·source
for the emitter - followers. The IOO·kQ potentiometer
shown in these schematics is used to null the effects of
amplil1er input offset voltage. This potentiometer is adjusted
to set the output voltage symmetrically about zero. Figs. 22a
and 22b show osdlJoscope photographs of the output
Fig. 25- Schematic diagram of analog multiplier using OTA.
voltages obtained when the circuit of Fig. 19 is used as a
modulator for both sinusoidal and triangular modulating
Signals. This method of modulation permits a range compensate for slight variations in the current-transfer ratio
exceeding 1000: I in the gain, and thus provides modulation of the current-mirrors (which would otherwise result in a
of the carrier input in excess of 99%. The photo in Fig. 22c symmetrical output abuut some current level other than
shows the excellent isolation achieved in this modulator zero); 2) the adjustment of the 20..ld1 potentiometer
TOP TRACE:GATEO OUTPUT IV/OW AND 50,..sec/OIIl
during the "8ated-ofr' condition. BOTTOM TRACE: VOl. TAGE EXPANSION OF ABOVE establishes the gm of the system equal to the value of the
SIGNAI..-SHOWING NO RESIDUAL fixed resistor shunting the system when the V-input is zero;
ImV/DIV AND 50l'sec/OlV-AT
Four-Quadrant Multipliers LEAST 80 db OF ISOLATION 3) compensates for error due to input offset voltage.
fq;IOOIiHa Procedure for adjustment of the circuit:
A single (' A3080A is especially suited for many
low-frequency, low-power four-quadrant multiplier applica- I. a) Sel the I MQ output-current balancing poten-
tions. TIle basic multiplier circuit of Fig. 23 is particularly tiometer to the center of its range
useful for waveform generatiun. doubly balanced modula- Fig. 22- aJ Oscilloscope photo of amplitude modulator b) Ground the X- and Y- inputs
tion, and other signal processing applicatiOns, in portable circuit of Fig. 15 with Rm =40H2, V+ = to v and c) Adjust the 100 kH potentiometer until a [Link]-V
equipment, where low-power consumption is essential and v- == ·10 V. Top trace: modulation frequency input reading is obtained at the output.
accuracy requirements are moderate. The multiplier config- ~ 2(} V pop; center trace: amplitude modulated 2. a) Ground the V-input and apply a signal to the X-
uration is basically an extension of the previously discussed output 5()()..mV/div.; lower trace: expanded output input thmugh a low source-impedance generator.
gain-controlled configuration (Fig. 19). to show depth of modulation, 20 mVldill.; b) (It is essential that a low impedance source be
To obtain a four-quadrant multiplier, the first term of triangular modulation; top trace: modulation fre- used; this minimizes any change in the gm
the modulation equation (which represents the fixed carrier) quency input.:::=. 20 v,. lower trace: amplitude balance or zero·point due to the 50-t'A V-input
must be reduced to zero. This term is reduced to zero by the modulated output 500 mVldill.; c) square wave bias current).
placement of a feedback resistor (R) between the output and modulation, top trace: gated output 1 Vldill.;lower b) Adjust the 2O-kU potentiometer in series with
the inverting input terminal of the C A3080A. with the value trace: expanded scale, showing no residual (1 V-input until a reading of zero-V is obtained at
of the feedback resistor (R) equal to 118m' The output mVldiv) and at least 80 dB of isolation at fq == 100 the output. This adjustment establishes the gm of
current is 10 = 8m (-Vx) because the input is applied to the kHz_ the CA3080A at the proper level to cancel the
output signal. The output current is diverted
inverting terminal of the OTA. The output current due to the
through the 510-kn resistor.
resistor (R) is 1[: Hence, the two signals cancel when R = 3. a) Ground the X-input and apply a signal to the
I/g m . The current for this configuration is: V-input through a low source-impedance gener-
ator.
lo=-19_2~vm. andVm=Vy b) Adjust the I-MO: resistor for an output voltage of
zero-V.
The output signal for these configurations is a "current" There will be some interaction among the adjustments and
which is best terminated by a short-circuit. This condition the procedure should be repeated to optimize the circuit
can be satisfied by making the load resistance for the performance.
multiplier output very small. Alternatively, the output can be Fig. 26 shows the schematic of an analog multiplier
applied to a current-to-voltage converter shown in Fig. 24. circuit with a 2N4037 p-n-p transistor replacing the V-input
In Fig. 23. the current ··cancellation" in the resistor R is ··current" resistor. The advantage of this system is the higher
a direct function of the OTA differential amplifier linearity. input resistance resulting from the current-gain of the p-n-p
In the following example, the signal excursion is limited to
',o---v."v---' transistor. The addition of another emitter-follower pre-
±IO mV to preserve this linearity. Greater signal-excursions ceding the p-n-p transistor (shown in Fig. 21) will further
on the input terminal will result in a Significant departure increase the current gain while markedly reducing the effect
from linear operation (which may be entirely satisfactory in Fig. 23- Basic four quadrant analog multiplier using an of the Vbe temperature-dependent characteristic and the
many applications). OTA. offset voltage of the two base-emitter junctions.
____________________________________________________________________ 541
ICAN-6668
20Jl18c/DIV
TOP TRACE FLIP-FLOP OUTPUT 15VOLTS/OIV)
CENTER TRACE "ONE-SHOT" OUTPUT (5 VOLTS/OIV)
BOTTOM TRACE· PULSE AT THE COLLECTOR OF
THE 21'04031 TRANSISTOR
(O I VOLTS/OIV) Fig. 31- Schematic diagram showing OrA driving COS/MOS
Inverter/Amplifier (open-loop mode). For greater
current output the two remaining amplifiers of the
CD4007A may be connected in parallel with the Fig. 34- Schematic diagram showing OTA driving two-stage
single stage shown. Open-loop gain ~ 130 dB. COS/MOS Inverter/Amplifier (unity gain closed-
loop mode).
(a)
TOP TRACE· COLLECTOR OF PNP TRANSISTOR
(05'01/01'01)'
CENTER [Link])CEO OUTPUT WITH ONE
CHANNEL INPUT GROUNO(O 5V/DIV)
LOWER TRACE DECODED OUTPUT (O 5'01/01'01)
TIME ALL SCALES 5 mnc / 01'01
.rep TRACE INP;)T 5V/OIV-IOD,...sec/DIV
BOTTOM H".~CE ouTPUT SAME SCALE
------~
Fig. 32- Schematic diagram showing OTA driving COS/MOS
Inverter/Amplifier (unity-gain closed-loop mode).
For greater cu"ent output. the two remaining (b)
...
--~
amplifiers of the CD4001A may be connected in
parallel with the single stage shown.
; t·
amplifiers in the C04007 A are connected as shown in Fig.
33, the open-loop slew-rate remains at 65 V/[Link]. A slew-rate
TIME EXPANSION TO 500Jlste/DtV
of about I V/JJsec is maintained with this circuit connected
in the unity-gain voltage-follower mode, as shown in Fig. 34.
Fig. 35 contains oscilloscope photos of input-output wave-
Fig. 30- (a) Waveforms showing timing of flip-flop. delav-
forms under small-signal and large-Signal conditions for the TOP TRACE II\IPUT-5QmV/DIV-I,...sec/DIV
"one-shot" and the strobing pulse to the sample- BOTTOM TRACE OUTPuT-SAME SCALE
circuits of Figs. 32 and 34. These photos illustrate the
and-hold circuit (Fig. 28): top trace: flip-flop
inherent stability of the OTA and COS/MOS circuits
output (5 V/div); center trace: "one-shot" output
uperating in concert. (oJ
(5 V/div); lower trace: pulse at collector of 2N4031
transistor (0.1 V/div); b) Waveforms showing the
decoding operation from the decoder keying pulse
(top traces) to the recovered "decoded" sampled
output (lower traces). 1) top trace: collector of
2N4031; center trace: multiplexed output with one
channel input grounded; lower trace: decoded
output; 2) Expanded scale of (1).
a constant-currcnt transistor. Phase compensation is applied
TOP TRACE INPUT-5v/DIV-IOO,...sec/DIV
at the interface of the (' A30RO and the 3N 138 MOS/FET BOTTOM TRACE OUTPUT -SAME SCALE
shuwn in i-=ig. 9.
Another variation of this gcneric form ()f amplifier
utilizes the RCA ('04007 A (COS/MOS) "inverter" as an (d)
ampliticr driven by the CA30XO. Each. of the three
"inverter"/amplificrs in the CD4oo7A has a typical voltage
gain of 30 dB. The gain of a single COS/MOS "inverter"/
amplifier coupled with the 100 dB gain of the C A30S0yicrds
a lotal ftHward-gain of about 130 dB. Usc of a two-stage
Fig. 33- Schematic diagram showing OTA driving two-stage
COS/MOS Inverter/Amplifier (open-/FP mode).
-t-
COS/MOS amplifier configuration will increase the total gain..:::: 160 dB.
open-loop gain of the system to about 160 dB
.'v----"
(100,000,000). Figs_ 31 through 34 show examples of these
configurations. Each COS/MOS "inverter"/amplifier can sink Precision Multistable Circuits
or source a current of 6 rnA (typ.). In figs. 33 and 34, two The micropower capabilities of the CA3080, when TOP TRACE II\IPuT-50mVfDIV -I,...see/DIV
BOnOM TRACE OUTPUT -SAME SCALE
COS/MOS "inverter"/amplifiers have been connected in combined with the characteristics of the C04OO7 A COS/
parallel to provide additional output current. MOS "inverter"/amplifiers. are ideally suited for use in
connection with precision multistable circuits. In the circuits Fig. 35- a) Waveforms for circuit of Fig. 32 with large signal
The open-loop slew-rate of the circuit in Fig. 31 is of Figs. 31, 32, 33, and 34, for example, power-supply input; b) Waveforms for circuit of Fig. 32 with
approximately 65 V/JJsec. When compensated for the unity- current drawn by the COS/MOS "inverter"/amplifier ap- small signal input; c) Waveforms for circuit of Fig.
gain voltage-follower mode, the sJew-rate is about 1 V/[Link] proaches zero as the output voltage swings either positive or 34 with large signal input; d) Waveforms for circuit
(shown in Fig. 32). Even when the three "inverter"/ negative, while the CA3080 current-drain remains constant. of Fig. 34 with small signal input.
__________________________________________________________________ 543
ICAN-888S
shows this equation plotted as a function of beta. It is Conclusions
significant that the current transfer ratio (12/1,) is improved The Operational Transconductance Amplifier (OT A) is a
by the (12 term, and reduces the significance of the 2 (1 + 2 unique device with characteristics particularly suited to
term in the denominator. applications in multiplexing. amplitude modulation. analog
multiplications, gain control, switching circuitry, multivibra-
tors, comparators, and a broad spectrum of micropower
" " circuitry. 1l,e (A3080 is ideal for use in conjunction with
(OS/MOS (Complementary-Symmetry MOS) IC's being
operated in the linear mode.
SCALE HORIZONTAL=2WaV
VERllCAL = ImA /DIV
STEPS=lmA/DIV Acknowledgements
The author is indebted to C. F. Wheatly for many helpful
Fig. F- Photo showing remits of Fig. E. discussions. Valued contributions in circuit evaluation were
made by A. J. Visioli Jr. and J. H. Klinger.
Fig. G shows the current·division within the "mirror" References
assuming a "unit" (l) of current in transistors (Q2 and 03. I RCA's Linear Integrated Circuits Manual, Basic Circuits.
Section.
~
The resulting current-transfer ratio 12/11 = f32+ i
26+ Fig. C Fig. G- Current flow analys;s of Fig. E. Rr A published data for r A3060 File No. 404
545
ICAN-6728
provides enough gain to bring the in- minals 10 and 11, perform peak or en- +10
put signal level to an amplitude suit- velope detection. As shown in Fig. 1,
0
able for fm detection, but not so high
as to cause PC layout or coupling
this frequency-sensitive network con-
sists of a parallel LC network in -10
V~ It
problems, Fig. 2. series with a 6.8-pF capacitor. The
REFEREN\CED TO RECOVERED AUOIDAT TERM 9
signal voltage (from Q30) is appiied -20
t-- VOLTAGE CONTROL AT MAX .• fO"4.!S MHz,fm-400Hz
4' ·!25 kHz
80 across the entire network connected to -30
terminal 10. The portion of the signal
10
(TYPICAL!. ! i\ from Q30 that is across the external -40
.i
60
! 6.8-pF capacitor is applied to terminal
-50
l\~M REJEC~IJN
~o 11, and the resulting difference in these [\. SI'G~AL-TO-NOI5E RATIO 16f-O I
:?
r signals provides the basic S curve used -60
- 40
~ 30
~
in the recovery of the audio signal from
the fm signal.
01
4 ", 4
I
88 tO • •• 100
liI RF INPUT LEVEL AT TERMS. 14.15-mv
~ 20 An advantage of the differential
peak detector is that it requires the Fig. 3 - Recovered audio and signal-to-noise ratio
alignment of only one single-tuned
.. .. ..
10 as functions 01 rf input level.
coil. This coil (L in Fig. 1) can be
0
, • , 4 , 4 aligned by anyone of the following
001 oI I
10 methods (with an input terminated in
FREQUENCY('",)-MHz
92CS-31101 50 ohms, fa = 4.5 MHz, 1m = 400 Hz, "The volume is controlled when the
Fig. 2· Voltage gain of if amplifier as a function L::.f = ± 25 kHz, and a voltage at ter- bias levels of the differential ampli-
fiers are changed by a current flow·
of frequency. minal 15 (V15) '" 100 mV rms):
ing through an external fixed resistor
between terminals 12 and 16. The
As shown in Fig. 4, the if amplifier 1 . Tune L for maximum recovered amount of current flowing through
consists of four stages of differential audio. To minimize thermal ef- this external resistor (which deter-
amplifiers, 015-016, 019-020, 023- fects on alignment, the volume mines the level of recovered audio) is
024, and 027-028, using resistors control should be adjusted so
R13, R16, R19, and R24 as constant- controlled by the position of the
that the maximum recovered
variable resistance (volume control)
current SinKS; each stage is fOllowed audio level at the load is
relative to ground. The voltage refer-
by emitter followers, 017, 021, and limited to a low power level
(approximately 0.1 watt or ence at terminal 16 is established by
025. Because the differential am- internal . zener diode Z2, approxi-
plifier functions as a limiter, am less).
mately 6 volts. The maximum level of
signals are eliminated and the signal 2. Tune L for maximum recovered recovered audio, therefore, occurs
into 030 consists of constant-am- audio and fine tune for when no currents other than the
plitude, frequency-modulated square minimum distortion. base currents for 034 and 039 are
waves. These square waves are being drawn from the zener diode
shaped into approximate sine waves 3. With no rf input Signal, note through the external resistor. When
by 030 and its associated RC net- the dc voltage at terminal 9. the volume control is adjusted for the
works to assure proper operation of Then apply a 4.5-MHz cw minimum level of recovered audio,
tlie fmdetector. The signal output signal and adjust the detector the current drawn from terminal 16
from R31 into the base of 041 and to coil L until the dc voltage at should be limited to less than 1
terminal 10 Is a constant-amplitude terminal 9 is the same as the milliampere.
fm sine wave. value noted.
This method of contrOlling the re-
After aligning the differential peak covered audio has a very predictable
FM Detector detector coil, align the input trans- volume-control taper, which can be
former by reducing the fm input modified to suit the designer's prefer-
The fm sine wave at terminal 10 signal level until the recovered audio ence by changing the external com-
constitutes the input signal to the dif- level drops approximately 3 dB. Then ponent values. In addition, it allows
ferential peak detector stage. The ex- tune the input transformer for a max- for either a one- or two-wire volume
tracted signal contains the audio In- imum recovered audio level while the control. The one-wire volume control
formation. The detector section is input level of the if amplifier-limiter is (Fig. 4, alternate volume-control cir-
formed by the differential amplifier below its limiting point. Fig. 3 shows cuit) requires only one wire from the
configuration comprising transistors the recovered audio, am rejection, printed circuit board to the external
031, 032, 035, 036, 040, and 041. and signal·to-noise ratio for the volume control, but requires that
Transistors 031 and 041 are emitter CA3134 as a function of rf input level. the value of the variable resistor be
followers that operate at approx- large (approximately 500 kilohms)
imately 0.3 rnA and provide high and that the resistor have an audio
impedance at each input of the Volume Control and taper to assure an acceptable
detector (terminals 10 and 11). Tran- Electronic Attenuator change of audio output level with a
sistors 032 and 040, which operate linear change (rotation) of the
at approximately 10 microamperes, Control of the audio Signal volume-control. The two-wire volume
along with the 15-picofarad capaci- detected by the differential peak control allows the use of a volume
tors C3 and C4 and the external fre- detector is accomplished by differen- control having a lower value of
quency-sensitive network on ter- tial amplifiers 033-034 and 038-039. resistance and a linear taper.
________________________________________________________________ 547
ICAN-8728
UNATTENUATED
v'
8 AUDIO OUTPU1
__ .l-__-l-______~i=:j:::==='---4--L--_\-l-@AUDIO OUTPUT
9 FROM ELECTRONIC
ATTENUATOR
16j VOLUME CONTROLS
FOR ELECTRONIC
J-4-----t.--®12 ATTENUATOR
~[Link]
-= I @ ~gNNECTION
I
'"
AUDIO PfJWER AMPLIFIER WITH CURRENT liMITING
_ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ---l
Fig. 4 - Schematic diagram of CA3134.
nents, especially costly electrolytic 073. The limiting drive is determined ceeds 150 ·C, tlie thermal-sensing
capacitors. The input impedance (at by the feedback from R53, R54, and portion of the CA3134 begins to shut
terminal 7) is typically 100 kilohms 069 to Q72, and R55, R56, and 071 to down the power amplifier by remov-
(R59). Fig. 5 shows the frequency 073. When the peak output current ing the bias from the power amplifier
response of the audio power ampli- exceeds approximately 0.8 ampere, driver stages. The temperature at
fier and Fig. 6 its efficiency. Both cur- the voltage developed across the which the thermal shutdown circuitry
rent limiting and thermal shutdown emitters of 072 and 073 will cause is activated is determined by the
protection are provided. Current 069 and 071, respectively, to con- relative areas of 09, 066, and 018
limiting is accomplished by limiting duct, thereby limiting the drive to the and those of 049,011,012, and 013.
the. drive to the output transistors output transistors 074, 075. When 049 conducts, transistors 079,
from the driver transistors 072 and When the chip temperature ex- 068, and 076 are in turn biased into
_____________________________________________________________________ 549
ICAN-6728
Acknowledgment and Audio Output Systems," conductive epoxy to allow the
File No. 1097. excess to be forced through
The author is indebted to both Jack 2. Method of attaching heat sinks the hole when the heat sink is
Craft for many helpful discussions similar to the type provided fitted over the stud. Stress ap-
and Wayne Austin for his sugges- with the CA3134GM or GQM to plied to the stud should be
tions in the preparation of this Note. the CA3134G. First apply a limited to less than 3 in-Ibs
The contributions of H. Chinery in the non-conductive epoxy (Uniset (approximately 0.35 newton-
electrical characterization of the structural adhesive or equiva- meter), 15 Ibs (approximately
CA3134 and Ralph Thompson in the lent) to the top side of the plas- 65 newtons) of tenSion, and
mechanical characterization of the tic package. Then apply a con- 100 Ibs (approximately 445
stud package are acknowledged. ductive epoxy (Dupont 5504A newtons) of compression.
or equivalent) in the hole of the
References heat sink and around the stud
projecting from the plastic
1. RCA Solid State Data Sheet for package. To assure good ther-
CA3134 types, "TV Sound IF mal conduction, use sufficient
___________________________________________________________________ 551
ICAN-8732
"
CO,
'N27O
GO'IIO-GO
IIIO'C4TOR
LATel1
CIRCUiT
".
NOTIES: O,-OS-RCA·cAJO.:S
ALL RfSlSTORS IN OHMS
ALL caPAC'TORS IN ."RMARADS
UNLESS OTHIER.'SIEHOTlEO
Fig. 2b- Complete IChematic diagnlm for burst noise [Link]
currents consistent with the gain-bandwidth requirements of The background noise peaks depend on the source Thus, at a room temperature of 29()OK.
the particular application. termination Rs, the wide band IJf noise fJgUre of the Dur,
In the test for burst noise. the source resistance (Rs) seen and the test system bandwidth. A good estimate of the
by the input terminals of the OUT. is a key test parameter. normal background noise--peak levels can be computed from
Burst noise causes effects which are equivalent to a spurious the defmition of noise factor and an empirically determined
For example, a 100 kO resistor preceding a system with a
current·source at the device input and. therefore, burst-noise noise-crest factor of approximately 6: 1. The crest-factor is
bandwidth of I kHz will genarate a noise-volt... of
current generates an equivalent input noise-voltage in the ratio of the maximum peak-noise voltage to the RMS
proportion to the magnitude of the source resistance through noise voltage. The noise factor is defined as the ratio of the
which it flows. Accordingly. to increase the sensitivity of the total noise power at the amplifier output to the output-noise
test system, it is desirable to use the highest source resistance power due to the source resistors alone. In terms of the RMS
consistent with the input offset-current of the OUT. For noise voltages at the input terminals of the amplifier this is
example, an Op-Amp which has 0.1 p.A input offset current equivalent to: Both inputs of an Op-Amp are usually terminated in Rs.
could realistically be tested with source·resistance in the hence it is necessary to combine the effects of both resistors
order of lOOKfl (10 mV input offset), whereas a I Mfl to determine the effective ENRs at the input of the DUT.
Noise Factor (F) = E2input noise total = (ENTi); (I) Because the noise voltages from these two resistors are
source-resistance (100 mV input offset) could cause excessive
E2noise source resist (ENRS) uncorrelated their voltages must be added vectoraUy rather
offset in the output. For 741 type Op-Amps a lOOkfl
than algebraically.
resistance is recommended.
Burst·noise generation in amplifiers is usually more ENTi is the total input noise-voltage. i.e., the sum of noise
prnnounoec1 at lower temperatures (particularly below O"C). generated in the source termination resistance and noise
generated by the DUT.
Consequently. consideration must be given to the tempera- ENRs (effcctive) =J(ENRsI)l + (ENRs:z)2 (4)
ture of the DUT in relation to the temperature range under
ENRs is that part of ENTi due to Rs alone.
which the [Link] is expected to perform in a particular
because ENRsI = ENRsl' when Rsl = Rs2
operation.
A test parameter of importance is the time duration of Therefore, ENTi = (.JF) (ENRs)' (2)
observation. Because the frequency of bunt-noise occurrence ENRs (effective = (...tZJ (ENIW
is frequently less than once every few seconds, the minimum
ENRs can be computed by using the well mown expression and for I kHz bandwidth at 2900K
test period should be in the range of from 1S to 30 seconds.
for "white-noisen generated across the terminals of a resistor
(R): ENRs (effective) = (V2) (1.28 pV) = 1.81 pVRMS.
.....[Link]
A test system built to accommodate the test philosophy (3) Ifin this example, the DUT has a wideband I/fn_ fl8Ure of
outlined above has the ability to reject or pass a OUT on the 4 dB (2.S: I power ratio) the total RMS background
basis of two variables: [Link] and the'frequency of where k =Boltzmans Constant = 1.372 x 10-23 j/oK noise-voltage at the input will be
burst occurrence. The [Link] which will trip the
counter can be no lower than the background IJf noise peaks T = Absolute Temperature in OK ENTi = (y'I!) (ENIW (from eq~2))
of burst-free units, otherwise normal background noise win B = Noise Bandwidth in Hz
fail the DUT. = (v'23) (1.81) = 2.9 pVRMS
R = Value of the resistor in ohms.
553
ICAN-8732
operated, "On·Ofr' switching of nearby equipment intro. TO [Link] TERMINAl. OF SECOND
duces detectable transients into the system. These problems DECADE COUNTER IF COUNT >9
CARRY OUT
are eliminated by placing the test circuitry in a completely
"9- +IOV
shielded enclosure with a hinged top for easy access to the +7.5V
test unit. The external noise problem is best solved by use of
a shielded enclosure and by use of a battery-operated
power-supply contained within the enclosure. Fig. 6 shows a
photo of the [Link] board layouts of the test unit.
02- 05
4/5 CA3083
Fig. 6- Photo of circu;t-boBrd layout Fig. 5- Counter·latch-timer-control circuit schematic.
_____________________________________________________________________ 555
Abstracts of Other Application Notes
voltages: a 50-dB amplifier: a la-dB. 42-MHz CA3028B are suitable for use in a wide range ICAN-584I . . . . . . . . . . . . . . . 4 pages
amplifier: a twin-T bandpass amplifier: a Za-dB. of applications in dc, audio. and pulse aml'lifier Feedback-Type Volume-Control Circuits for
I D-MHz bandpass amplifil'r; and a voltage- service; they have ':been used as sense amplIfIers, RCA-CA3041 and CA3042 Integratad Circuits
follower. preamplifiers for low-level transducers. and dc This Note describes feedback-type volume
differential amplifiers. controls for use with RCA-CA3041 and CA3042
ICAN-5269 . . . . . . . . . . . . . . . 7 pages integrated circuits in television receivers. In
Integrated Circuits for FM Broadcast Receivers television sets using these integrated circuits,
This Note describes several approaches to ICAN-5338 . . . . . . . . . . . . . . . 14 pages the volume control is often located remote
FM receiver design using silicon monolithic Application of the RCA-CA3021, CA3022,.[Link] from the amplifier. The long leads required in
CA3023 Integrated-Circuit, Wideband AmplIfIers such a configuration sometimes pick up undesir-
in tcgratcd circuits. Th~ ~uncr ~.ction is described The CA3021, CA3022, and CA3023 inte-
first. and then the II-amphfler and detector able signals that, in turn, cause the system to
grated circuits arc multipurpose high-gain am- exhibit hum and noise at low volume levels.
sections. Performance characteristics are describ-
ed where applicable. The FM receivers discussed plifiers designed for use in video and AM or ~M. The proposed feedback-type volume control
arc designed for use from a +9-volt supply. if stages in single-power-supply systems. SpecIfI- reduces hum and noise pick-up by reducing the
The key to design simplicity is the use of the cally, they can be used in video amplifiers gain of the system rather than the signal level,
RCA multifundion integrated circuits CA3005, operating at frequencies through 30 MHz, A!'1 and thus eliminates the cost of shielding the
CA30l2, and CA3014. The CA3005 may be and FM if amplifiers, and buffer amplIfiers In leads.
which an isolation capability greater than 60
used as a cascade rf amplifier, a differential rf
amplifier, a mixer-oscillator. and an if amplif!er; dB at I MHz is desired.
ICAN-6259 . . . . . . . . . . . . . . . 10 pages
the CA3012 and CA3014 perform if amplIfIca- Integrated-Circuit Stereo Decoder Using the
tion. limiting, detection, and preamplification. ICAN-5380 . . . . . . . . . . . . . . . 7 pages CA3090AQ Stereo Multiplex Demodulator
Integrated - Circuit Frequency - Modulation if The CA3090AQ integrated-circuit provides
Amplifiers features heretofore unavailable to the receiver
ICAN-5296 . . . . . . . . . . . . . . 5 pages
Application of the RCA-CA3018 Integrated- The discussion in this Note shows that the designer. This device needs only a sin):le tuning
simplest approach I to the use of the CA3012 adjustment. which reduces to a mmlmum the
Circuit Transistor Array
The CA3018 integrated circuit consists of and CA3028 integrated circuits in FM if-ampli- manual effort during assembly; the phase-locked
four silicon epitaxial transistors produced by a fier strips is to replace each stage in present loop maintains performance under conditions
monolithic process on a single chip mounted in discrete-transistor if strips with a differential of temperature variations, humidity, and aging.
a 12-lead 1'0-5 package. The four active devices, amplifier. This integrated-circuit approach re- The compactness of the CA3090AQ and of the
two isolated transistors plus two transistors with quires a minimum of re-engineering be~ause a required external components, added to the
an emitter-base common connection, are es- cascade of individually tuned if stages IS used. other attributes, makes this stereo decoder a
pecially suitable for applications in which From a performant.-e point of view, this ap- significant advancement in the state of the art
closely matched device characteristics are re- proach results in better AM rejection than that of stereo decoder designs.
quired, or in which a number of active devices obtained with discrete circuits because of the
must be interconnected with non-integrable inherent limiting achieved with the differential-
amplifier configuration. ICAN-6302 . . . . . . . . . . . . . . . 9 pages
components such as tuned circuits, large-value Description and Application of the RCA-
resistors, variable resistors. and microfarad by- CA3120E I ntagrated-Circuit TV-Signal Processor
pass capacitors. Such areas of application include ICAN-5766 . . . . . . . . . . . . . . . 8 pages The CA 3120E is a 16-pin, dual-in-line-
if, rf (through 100 MHz). video, agc, audio, and Application of the RCA-CA3020 and CA3020A monolithic-silicon integrated circuit that pro-
de amplifiers. Integrated-Circuit Multipurpose Wideband cesses a video signal and provides the [Link]
Power Amplifiers outputs: non-inverted video output; nOlse-
ICAN-5299 . . . . . . . . . . . . . . . 6 pages The CA3020 and CA3020A integrated cir- processed, inverted .video output; dual-polarIty,
Application of the RCA-CA3019 Integrated- cuits are multipurpose, multifunction power composite synchronization signals; and auto-
Circuit Diode Array amplifiers designed for lise as power-output matic gain-control signals (agc). The IC, whIch
The CA 30 19 in tegra ted circuit diode array amplifiers and driver stages in portable and can be used in color or monochrome TV
provides four diodes internally connected in a fixed communications equipment and in ac reoeivers, requires a single-polarity power supply
diode-quad arrangement plus two individual servo-control systems. The flexibility of these (positive) and includes impulse noise inversion
diodes. Its applications include gating, mixing, circuits and the high-frequency capabilities of and delay circuits that reduce the deleterIOUS
modulating. and detecting circuits. Because all the circuit components make these types suit- effects of impulse noise in the receiver age and
the diodes are fabricated simultaneously on a able for a wide variety of applications such as synchronization (sync) circuits. Standard agc
single silicon chip. they have nearly identical broadband amplifiers, video amplifiers, and strobing techniques are also used. Th~ agc and
characteristics. and their parameters track each video line drivers. Voltage gains of 60 dB or impUlse-noise thresholds are ~utomal!cally s:'t
other with temperature variations. Consequent- more are available with a 3-dB bandwidth of and require no controls. The If maxlmu'!l-galn
Iy, the CA3019 is particularly useful in circuit 8 MHz. Applications covered include audio, bias and the tuner agc delay may be adjusted
configurations that require either a balanced wideband, and driver amplifiers. for optimun. TV-receiver performanoe; the
diode bridge or identical diodes.
time constant tor the sync-separator input can
ICAN-5831 . . . . . . . . . . . . 5 pages also be optimized by the set designer.
ICAN-5337 . . . . . . . . . . . . 10 pages Application of the RCA-CA3044 and CA3044VI
Application of the RCA-CA3028A and CA- Integrated Circuits in Automatic-Fine-Tuning
30288 Integrated-Circuit RD Amplifiers in the Systems ICAN-6724 . . . . . . . . . . . . . . . 8 pages
HF and VHF Ranges This Note describes the use of the CA3044 A Flexible Integrated-Circuit Color Demodu-
The C A3028A and CA3028B monolithic- and CA3044VI integrated circuits as automatic lator for Color Television
silicon integrated circuits are single-stage dif- fine-tuning (AFT) system components and dis- This Note describes the circuit operation
ferential amplifiers intended for service in cusses the advantages of integrated circuits in and application of the CA3067 in a .color tele-
communications systems opera ting at frequen- this application. The CA3044VI is electrically vision receiver. The CA3067, whIch IS supplIed
cies up to 100 MHz wilh single power supplies. identical to the CA3044, but is supplied with in a quad-in-line 16-lead plastic package,. pro-
This Note provides technical data and recom- formed leads for easier printed-circuit-board vides the following color-demodulator CIrCUIt
mended circuits for use of the CA3028A and mounting. The construction and performance functions: amplification, balanced chroma de-
CA3028B in rf amplifiers, au todyne converters, of a typical automatic-fine-tuning 'system for a modulation. dc-operated tint (phase) control,
if amplifiers, and limiters. The CA3028A and color television system are examined. and zener-diode voltage regulation.
____________________________________________________________ 557
RCA Sales Offices
Manufacturers'Representatives,
and Authorized Distributors
_ _ _ _ _ _ _ _ _ _ _ _ 559
RCA Manufacturers' Representatives
New Jer.., ...•. Thoma. AIIsocI ..... Inc••
ArIzona ...•...• C.T. Carlbelll Allsocl ...., (So. N.J.), 12 South Blackhorse Pika (215)827""5
4238 North Brown Ave., Bellmawr, NJ 08031 ..••.•••••••.••...•.. (60l)Il33-2800
Scottsdale, AZ 85251 •......•........... (802}277·2808 New Mexico ..•. C.T. Carl belli Allsocl.....
Caillomia •..... Beetronlca (San Diego Area) PO Box 3177. Station D.
7827 Convoy Court, Suite 407, Albuquerque. NM87110 ••.•..•.•••....•. (5CIS)2§1579
San Diego, CA 92111 .........••.......•. (714)278-2150 New YolII .•..•.. L·Mar Allsoclam. Inc••
Colorado ..•.•.. Waugaman AIIsocI ..... Inc. ([Link] Ny), 08 Elwell Ave.
4800 Van Gordon. Binghamton. NY 13901 •.•.•..••.••.••••. (607)723-1513
Wheatrldge, CO 80033 ..•.••........•..• (303)423-1020 New York •..•.•. L·Mer Allsocl ..... Inc ••
Delawara •...•.. Thoma. AIIsocI ...., Inc., (See New Jersey) (Upetate Ny) PO Box 7945.
florida ..•...•.• O.F. Bohman Allsoclata•• [Link]. NY 14608 .••.•••••••.••.••••• (718)328-5240
5104 No. Orange Blossom L·Mar Allsocl ..... Inc••
Trail, Suite 115, Rosemont Bldg. 216 Tilden Drive.
Orlando, FL 32804 ...................... (305)2115-6780 E. Syracuse. NY 13057 .•••..•..••..•...• (315)437·7779
O.F. Bohman Allsocl ..... North Dakota ••• Lorenz Sal... Inc•• (se. Iowa)
3172 SW 27th Ave., Apt. 3, Ohio ........... Arthur H. aaler Company.
Miami, FL 33133 ...•....•...••....•.••. (30S)584-3081 87 AI pha DrIve.
O.F. Bohman [Link]., Cleveland, OH 44143 .••.•.••.•...•.•.•.. (218)481-8181
4511 Bayahore Blvd. NE. Arthur H. aaler Company,
St. Petersburg, FL 33703 .......••••••.•.. (813)527"54 4040 Profit Way.
Idaho .•...•..•. [Link] Technical Sal... Inc., Dayton. OH 45414 .•.•....••.•••.•••.•.. (513)278-4128
(No. of Boise. see Washington) Oregon •..•.•••. W..tam Technl~al Sal••• Inc••
R2Mallletlng, (E. & S. of 2271 N.E. Comell Rd.,
Boise. see Utah) Hillsboro. OR 97123 ..........•...•..... (503)840-4821
IIIlnol•...•..•.. Kebco. (see Missouri) Pannsylvanla •.. Arthur H. aaler Company, ~. Pa., see Ohio)
Iowa ...•....•.. Loranz Sal... Inc., Suite 302, Pannayl"anla •.• Thoma. AllsocI ..... Inc•• (E. Pa•• see New Jersey)
Executive Plaza, South Dakota •.• Lorenz Sal.., Inc., (see Iowa)
Cedar Rapids, IA 52402 ..•..•..•.•....... (319)3113-8812 T............... C.T. Cerlberv Allsocl ..... (EI Paso)
Ken.a. • ••.•... [Link], 7070 West 107th St., Suite 160, Area. see New Mexico)
Overland Park. KS 68204 ••.••••........•. (913)848-2188 Jackson Amold Company.
[Link] •..... [Link] Amold Company. (see Texas) (Austin. Houston, San Antonio
Michigan •..•... Nlcon AllsocIata., 3835 W. Eight Area), PO Box 42388.
Mile Rd., DetrOit, MI48221 ••.•...•.•.•... (313)341.7886 Houston. TX 77042 ...••..•.••.•......•. (713)881-1;781
Mlnn._ ..•..• [Link]. Inc., Utah •.......... R2 Mallleting. 3886 West 2100 South.
2852 Anthony Lane South, Salt Lake City. UT84120 .•.•••..••.•...•• (901)872·6848
Minneapolis, MN 55114 •....•.........•. (612)788-8234 [Link] •.•. [Link] Technical Sal.., Inc••
MllIOuri .....•. Kabco, 75 Worthington Drive. PO Box 3923,
Maryland, MO 63043 .•••........•.•. (314)578-411014111 Bellevue, WA 98009 ...•.•...••...•.•.•.• (208)841-3800
Montana ..•.... R2 [Link]. (see Utah) Weat Vlrvlnla ... Arthur H. Baler Company. (see Ohio)
[Link]••ka .•..... Loranz Sal... Inc., (see Iowa) WI_.ln ...••. Key [Link].... 850 Elm
Nevada ...•.••. C.T. Carlberg AIIsocI .... (Clerk Co., Grove Road, Elm Grove, WI 53122 •.•..•... (414)784-3380
see Arizona) Wyoming ........ Waugaman Allaoclata•• Inc., (see Colorado)
_____________________________________________________________________ 561
RCA Authorized Distributors
Talwlll .••.••••. Hwa Sheng Electronic Co., Ltd., 3th Fl., Calilomia ...... Liberty/Sen Diego, 9525
117, Ren ..' Rd., Sec. 2, Chesapeake Drive, San Diego
Taipei, R.O.C.......................... (02)3218311-5 CA 92123 ............................. (714)585-8171
lballllld .•..•.. Anglo·lbal Eng. Ltd., PO Box 18, G.s. Marshall Company,
Bangkok 9874 Telstar Avenue,
Turkay •.•.•.••. Taknlka TAS, PO Box KarakDy 153, EI Monte, CA 91731 .•..•..............•• (213)888-0141
Istanbul ................................... 4381 00 RPS ElectroniCS, Inc., 1501
Taknlm Company Ltd., Rim Seh South Hili Street, Los Angeles,
Pehlevl Caddeal 7, Kavaklldere, CA90015 ............................. (213)7....,271
Ankara ..................................... 275800 Schwaber Electronlca Corp.,
Uruguay .•.••..• Amerlcan Pladucla 8.A., Av. Italla 4230, 17811 Gillette Ave.,
Montevideo Irvine, CA 92714 ........................ (714)558-3880
Venezuela •..••• Tala_a, C.A-, PO Box 3975, caracas Colorado ..•.... Elmar ElectronlcllDanver,
Yugollevla •.••. Avtotehna, PO Box 593, XI, 6777 East 50th Aven ue
TIIova3&, LjublJana 81000 ..•.••..•..•..•.•••. 317044 Commerce City, CO 80022 •..•..•.•...... (303)267-11811
UK •...••.•..•. Apex CompollMla Ltd., 398 Hllllllton·Awnet electronics,
Bath Road, Slough, Berka, 5921 North Broadway,
SL18JD ............................. Burnham 83741 Denver, CO 80216 ..•..••..•.•.•••..•.•• (303)534-1212
Cnliion Ltd. 3801388 Klerultf electroniCS, Inc.,
Bath Road, Slough, Berka, 10890 East 47th Avenue,
SL1 8JE .............................. Bumham 4434 Denver, CO 80239 ...................... (303)371-8500
Dlstronlc Ltd., 50151 Connecticut •... Arrow electroniCS, Inc.,
Burnt Mill, Elizabeth Way, 295 Treadwell Street,
Hartow, Essex, CM20 2HU .......•.. Hartow (0279)38701 Hamden, CT 06514 •...•................ (203)248-3801
m Electronic Sanlloa., edinburgh Way, CramarlCo_lout, 12 Beaumont Rd.,
Harlow, Essex, CM20 2DE ••••.••.••..••. Harlow 28811 Wallingford, CT 06492 ...••.......•..••.. (203)265-7741
Mogul Electronlca Ltd., Hamllton·Awnet Electronics,
273 High Street, 643 Danbury Road,
epping, Essex, CM 18 4DA •..••••..•.•••. epping 77388 Georgetown, CT06629 •.•••.•........... (203)762-0381
Semlcamp. (Northam) Ltd. Sch_bar Electronics Corp.,
East Bowmont Street, Kelso, Finance Drive, Commerce Industrial Park,
Roxboroughahlre TD5 7BZ ...•.....•..•.... Kelso 2388 Danbury, CT 06810 •.....•..•........... (203)782-3500
Flortda ..•.•...• Arrow Electronlca, Inc.,
1001 NW 62nd St., Suite 402,
U.S. Ft. Lauderdale, FL33309 ••••.•..•..••.•. (305)776-7790
Arrow electronics, Inc.,
115 Palm Bay Road, N.w., Suite 10,
Alllbama .•••.•• Hamllton·Awnet Electronics, Palm Bay, FL32905 •.•..••.••.••....••.. (306)725-1480
4692 Commercial Drive N.W., CrameliOrtando,
Huntsville, AL 35805 ......•...•..•...•.. (205)837-7201 345 Grsham Avenue,
Arbona •.•..•.• Hamllton·Awnet Electronics, Orlando, FL32803 ...................... (305)885-1511
2815 South 21st Street, [Link]·Awnet electronics,
Phoenix, AZ 85034 ...................... (802)275-7851 8800 N.W. 20th Avenue,
Klerultf electroniCS, Inc., Ft. Lauderdale, FL33309 ••••.•••.•..••.. (306)871·2900
4134 East Wood Street, Hamllton·Awnet Electronics,
Phoenix, AZ85040 ..•.•........•...•..•. (802)243-4101 3197 Tech Drive No.,
Artmna .•.••..• Uberty Electronlcl/Allmna, St. Petersburg, FL 33702 ...•............. (813)576-3830
8155 North 24th Avenue, Schweber electronics Corp~
Phoenix, AZ 85022 ...................... (802)2....2232 2630 North 28th Terrace,
Caillomia ...•.• CremeliSan Franclaco, 720 Hollywood, FL3302O ...•................ (305)827-0511
Palomer Avenue, Georgia ........ Arrow electronics, Inc., 3408 Oak Cliff
Sunnyvale, CA 94088 .•......•..••.••.•.. (408)739-3011 Rd., Doraville, GA 30350 ..•..•.•.....••.. (404)455-4054
Electronic Supply Corp. 2488 CrameliManla,8458
Third Street, Riverside, Warren Drive,
CA 92507 ............................. (714)883-7300 Norcross, GA 30071 .................... (404)448-9050
Elmer ElectroniCS, Inc., 2288 Hamllton·Awnet Electronics,
Charleaton Roed, Mt. View, 8700 165 Access Road, Suite 1E
CA 84042 .•..•..•...............•..•.. (415)881-3811 Norcross, GA 30071 ..•..•.....•..•..•.. (404)448-0800
Hamlllon·Awnet electronic., Illinois ......... CrameIiChlc_go, 1911
1175 Bordeaux Drive, South Busse Road,
Sunnyvale, CA 94088 ........•..•.....•.. (415)743-3300 _. Mt. Prospect, IL 60056 •..••..••.•.••..•.. (312)583-8230
Hamllton·Awnet electronics, Hamlllon·Awnet electronics,
8917 Complex Drive, Sen Diego, 3901 North 25th Avenue,
CA 92123 ••.••.•..••..•.........•..... (714)279-2421 Schiller Park,'L80178 ...•...•.....•..... (312)678-8310
Hamilion Electro Sal.., 10912 Newark electroniCS, 500
W. Washington Blvd., Culver North Pulaski Road,
City, CA 90230 ......................... (213)558-2020 Chlcago,IL80624 ....•..•..•..•.....•.. (312)638-4411
Klerulff electroniCS, Inc., Schwebar Electronics Corp.,
2585 Commerce Way, 1275 Brummel Ave., Elk
Los Angelea, CA 90040 ...•.......•...•.. (213)885-5511 Grove Village, IL80007 .....•..•..•..•... (312)593-2740
Klerulff electronics, Inc, Semiconductor Specialists, Inc~
3989 E. Bayshore Road, 195 Spangler Avenue,
Palo Alto, CA 94303 •.•.•.••.••..••.•.... (415)888-8292 Elmhurst, I L 80126 ...................... (312)279-1 000
Klerultf electroniCS, Inc. Indiana ........ Graham Electranlca Supply, Inc.,
8797 Balboa Avenue, 133 S. Pannsylvanla Street,
San Diego, CA 92123 ..•.••..•.•.•..•..•• (714)278-2112 Indianapolis, IN 46204 ....•.....•......• (317)834-8202
Uberty ElectroniCS, 124 Iowa ........... Desco, Inc., 2500
Maryland Avenue, 16th Avenue, S.W.,
EI Segundo, CA 90245 ................... (213)322·81 00 Cadar Rapids, IA 52801 ..............•... (318}385-7551
~ ___________________________________________________________________ 563
RCA Authorized Distributors
Ohio. . . . . . . . . •• eramerfCleveland, Taxa•..•....... Schwebar Elactronlcl Corp.
5835 Harper Road, 7420 Harwln Drive,
Solon, OH 44139 .........•.•..•........ (218)248-8400 Houston, TX 77063 ................•..•. (713)784-3800
Hamlllon·Amet Elactronlc., Sterling electronic., Inc.,
761 Beta Drive, Suite E. 2800 Longhom, Sulta 100,
Claveland, OH 44143 .•...•.............. (218)481·1400 Austin, TX 78758 ....................... (512)838-1341
Ham"lon·Amet Electronics, Sterling electronic., Inc.,
954 Senate Drive, 4201 Southwest Freeway,
Dayton,OH 45459 ...................... (513)433-0810 Houston, TX n027 ..•..•..•.......•.... (713)827·9800
Hugh_Petars, Inc., Sterling Electronics, Inc.,
481 East 11th Aveneu, 2875 Merrell Road,
Col umbu8, OH 43211 .....••.•.•.•.•.... (218)484-2970 Dallas, TX 75229 ....................... (214)357·9131
Schweber Electronics Corp., Trevino Elactronlcs, Inc.,
23880 Commerce Park Road, 2828 Walnut Hili Lane,
Beachwood, OH 44122 •.........•••.•.•. (218)484-2970 Dellas, TX 75229 •.•.•.•.....•.•••...... (214)358-2418
The SIotts BlIeclman Co., Utah •...•.•.•.• Hamlllon·Amet Elactronlc8,
2600 East River Road, 1585 West 2100 South,
Dayton, OH 45439 ....•......•..•.•..... (513)298-6555 Salt Lake City, UT 84119 •.•.•.•.•••••.•.• (801)972·2800
Oklahoma ...... Radio, Inc., Washington ..•. Hamlllon·Amet Elactronlcs,
1000 S. Main Streat, 13407 Northrup Way,
Tulsa, OK 74119 ........................ (918)587-8123 Bellevue, WA 98005 ......•..•.•.•.•....• (208)748-8750
Pennsylvania ... Harbach. Radaman, Inc., Uberty ElectnmlcalNorIh_st,
401 East Erie Avenue, 1750 132nd Ave. N.E.,
Philadelphia, PA 19134 •.•..•..••.•..••.. (215)426-1700 Bellevue, WA 98005 ..................... (208)453·8300
Pennsylvania ... Semiconductor Specialist., Inc., Robert E. Priebe Company,
1000 RIDC Plaza, Suite 207, 2211 5th Avenue,
Pittsburgh, PA 15238 ............•...•..• (412)781-812O Seattle, WA 98121 ......•.•............. (208)882-8242
Taxa•...•...... CramadTaxas, Wisconsin ...... Arrow electroniCS, Inc.,
13740 Midway [Link], 434 West Rawson Avenue,
Dallas, TX 75240 •..•..•......•........• (214)881-8300 Oak Creek, WI 53154 •......•.•.•.•.•.•.• (414)784-8800
Ham"ton·Amet electronics, Hllflllllon·Amet Electronics,
445 Sigma Road, 2975 South Moorland Road,
Dallas, TX 75240 ....................... (214)881·8881 New Berlin, WI 53151 ..•.•.•....•.•.•..• (414)784-4510
Hamlllon·Amet Elactronlcs, Taylor electric Company,
3939 Ann Arbor Street, 1000 W. Conges Bay Road,
Houston, TX n063 ..................... (713)780·1n1 Mequon, WI 53092 .....•.•...•......•... (414)24104321
Sch_bar ElectroniCS, Corp.,
14177 Proton Road,
Dallas, TX 75240 .••.•.•.•....•......... (214)881·5010
________________________________________________________________ 5~
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