Introduction to the ARM Processor

Instruction Set Architecture

CMPE 364
Microprocessor Based Design
SPRING 2019

Slides prepared by Prof. Qutaibah Malluhi and modified by Dr. Loay Ismail. 1
Some slides are adapted from slides by Dr. M. Almeer.
Lecture Objectives
 Objectives
 An Introduction to the ARM processor

 Expected to achieve:
 Know about ARM registers
 Know about ARM modes
 Overview of the ARM instruction set

2
A First Look at the ARM Processor: Main Features
 Load-Store architecture
 Fixed-length (32-bit) instructions
 3-operand instruction format (2 source operand reg’s, 1 result
operand reg.)
 Conditional execution of ALL instructions
 Load-Store multiple registers in one instruction
 A single-cycle n-bit shift with ALU operation
 Coprocessor instruction interfacing
 Thumb architecture (dense 16-bit compressed instruction set)
 Combines RISC and CISC features 3
RISC + CISC Features
 Not a pure RISC. Adds CISC features to make it suitable for
embedded systems. E.g.,
 Variable cycle execution for certain instructions
 Load-store-multiple: performance and code density
 Thumb 16-bit instruction set
 Execute both 16-bit and 32-bit instruction sets: code density
 Conditional execution of instructions
 Reduce branch instructions: performance and code density
 Inline barrel shifter
 Preprocess register before using in an instruction: perf. and code density

4
Data Sizes and Instruction Sets
 The ARM is a 32-bit architecture.

 When used in relation to the ARM:

 Byte means 8 bits
 Halfword means 16 bits (two bytes)
 Word means 32 bits (four bytes)

 Most ARM’s implement two instruction sets

 32-bit ARM Instruction Set
 16-bit Thumb Instruction Set
Register File
 Data items are placed in the register file
 16 32-bit registers
 The sign extend hardware converts signed 8-bit and 16-bit numbers
to 32-bit values.
 ARM instructions typically have two source registers, Rn and Rm,
and a single result or destination register, Rd.
 Source operands are read from the register file using the internal
buses A and B, respectively.
ARM Registers r0
r1
 Identified with the letter r prefixed to the register number r2
r3
 For example, register 4 is given the label r4. r4
r5
 Figure shows the active registers available in user mode r6
r7
 The processor can operate in seven different modes, which we r8
will introduce shortly. r9
r10
 All the registers shown are 32 bits in size. r11
 There are up to 18 active registers: 16 data registers and r12
r13 (sp)
2 processor status registers. r14 (lr)
r15 (pc)
 The data registers are visible to the programmer as r0 to r15.
cpsr
--
7
ARM Registers (2) r0
r1
 The ARM processor has three registers assigned to a r2
r3
particular task or special function: r13, r14, and r15. r4
r5
 Given different labels. r6
r7
 Register r13 is traditionally used as the stack pointer (sp) r8
to store the head of stack in the current processor mode. r9
r10
 Register r14 is called the link register (lr) stores the r11
r12
return address whenever it calls a subroutine. r13 (sp)
 Register r15 is the program counter (pc) r14 (lr)
r15 (pc)

cpsr
--
8
Current Program Status Register (CPSR)
 The ARM core uses the cpsr to monitor and control internal operations.
 The cpsr is a dedicated 32-bit register and resides in the register file
 The cpsr is divided into four fields, each 8 bits wide: flags, status,
extension, and control.
 The control field contains the processor mode, state, and interrupt
mask bits
 The flags field contains the condition flags
Flags Status Extension Control
Fields
Bit 31 30 29 28 7 6 5 4 0

N ZCV I FT Mode

Function
Condition Interrupt Processor
flags Masks mode 9
Thumb state
CPSR: Condition Flags
 N: Negative; the last ALU operation which changed the flags
produced a negative result (most significant bit of the 32-bit result
was a one).
 Z: Zero; the last ALU operation which changed the flags
produced a zero result (every bit of the 32-bit result was zero).
 C: Carry; the last ALU operation which changed the flags
generated a carry-out, either as a result of an arithmetic
operation in the ALU or from the shifter.
 V: oVerflow; the last arithmetic ALU operation which changed the
flags generated an overflow into the sign bit.
10
CPSR: States and Instruction Sets
 2 states: ARM (32-bit) and Thumb (16-bit)
 The ARM instruction set is only active when the processor is in ARM
state.
 Otherwise, processor is executing purely Thumb 16-bit instructions.
 CPSR (T bit) can switch the state (used instruction set).
ARM and Thumb instruction set features.
ARM (cpsr T = 0) Thumb (cpsr T = 1)
Instruction size Core 32-bit 16-bit
instructions 58 30
Conditional execution Most Only branch instructions
Data processing instructions Access to barrel shifter and ALU Separate barrel shifter and ALU instructions
Program status register Read-write in privileged mode No direct access
Register usage 15 general-purpose registers 8 general-purpose registers
+pc +7 high registers +pc 11
CPSR: Interrupt Mask
 Used to stop specific interrupt requests from interrupting the
processor.
 Interrupt request (IRQ) and
 Fast interrupt request (FIQ).
 CPSR(7,6) (I,F) controls IRQ and FIQ.

12
CPSR: ARM Processor Modes
 Each processor mode is either privileged or non-privileged
 A privileged mode allows full read-write access to the cpsr.
 A non-privileged mode only allows read access to the control
field in the cpsr but still allows read-write access to the condition
flags
 There are seven processor modes in total:
 Six privileged modes (abort, fast interrupt request, interrupt
request, supervisor, system, and undefined)
 One non-privileged mode (user).

13
Processor Modes
 The ARM has seven basic operating modes:
 User: unprivileged mode under which most tasks run
 FIQ: entered when a high priority (fast) interrupt is raised
 IRQ: entered when a low priority (normal) interrupt is raised
 Supervisor: entered on reset and when a software-interrupt
instruction is executed (typically, the OS operates in this mode)
 Abort: used to handle memory access violations
 Undefind: used to handle undefined instructions
 System: privileged mode; a special version of user mode (uses the
same registers as user mode); allows full read-write access to cpsr.
ARM Processor Modes Summary

 In CPSR, the Mode[4:0] controls the Mode settings

Processor modes
Mode Abbreviation Privileged Mode[4:0]

Abort abt yes 10111

Fast interrupt request fiq yes 10001
Interrupt request irq yes 10010
Supervisor svc yes 10011
System sys yes 11111
Undefined
User und
usr yes
no 11011
10000
15
Banked Registers

 20 from 37 registers are hidden from a program at different modes

 They are available only when the processor is in a particular mode.
 Abort mode has r13_abrt and r14_abrt, and spsr_abrt registers

 For example:
 When the processor is in the interrupt request mode, the instructions
you execute still access registers named r13 and r14.
 However, these registers are the banked registers r13_irq and
r14_irq.

16
Banked Registers
User Mode
r0
r1
r2
r3
r4
r5
r6 FIQ IRQ SVC Undef Abort
r7
r8 r8
r9 r9
r10 r10
r11 r11
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
-- spsr spsr spsr spsr spsr
 The ARM Banked Register Set (Animation)
Current Visible Registers
r0
Abort
SVC
Undef
FIQ
IRQ
User Mode
Mode
Mode
Mode
Mode r1
r2
r3 Banked out Registers
r4
r5
r6 User FIQ IRQ SVC Undef Abort
r7
r8 r8 r8
r9 r9 r9
r10 r10 r10
r11 r11 r11
r12 r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr spsr
Register Organization Summary
User FIQ IRQ SVC Undef Abort
r0
r1
User
r2 mode
r3 r0-r7,
r4 r15, User User User User
and mode mode mode mode Thumb state
r5
cpsr r0-r12, r0-r12, r0-r12, r0-r12, Low registers
r6
r15, r15, r15, r15,
r7 and and and and
r8 r8 cpsr cpsr cpsr cpsr
r9 r9
r10 r10 Thumb state
r11 r11 High registers
r12 r12
r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp) r13 (sp)
r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr) r14 (lr)
r15 (pc)

cpsr
spsr spsr spsr spsr spsr

Note: System mode uses the User mode register set

Two Instruction Sets
 ARM: Standard 32-bit instruction set
 THUMB: 16-bit compressed form offering good code density
 Instruction set features
 Load/Store architecture
 3-address data processing instructions
 Conditional execution
 Load/Store multiple registers
 Shift & ALU operation in single clock cycle
20
ARM Conditional Execution
 Most ARM instructions can be executed conditionally on the
value of the condition flags.

 A condition attribute (shown in the next table) is post fixed to

the instruction mnemonic, which is encoded into the instruction.

 Prior to execution, the processor compares the condition

attribute with the condition flags in the cpsr register.
 If they match, then the instruction is executed; otherwise the
instruction is ignored. 21
ARM Conditional Execution (2)
 Table lists the conditional execution code mnemonics.
 When a condition mnemonic is not present,
 The default behavior is to set it to always (AL) execute.
Mnemonic Name Condition flags
EQ equal Z
NE not equal z
CS HS carry set/unsigned higher or same C
CC LO carry clear/unsigned lower c
MI minus/negative N
PL plus/positive or zero n
VS overflow V
VC no overflow v
HI unsigned higher zC
LS unsigned lower or same Z or c
GE signed greater than or equal NV or nv
LT signed less than Nv or nV
GT signed greater than NzV or nzv
LE signed less than or equal Z or Nv or nV
AL always (unconditional) ignored 22
ARM Instruction Set
ARM
instruction set

Data
Data transfer
processing
instructions
instructions

Block transfer Branching

instructions instructions

Software
Multiply
interrupt
instructions
instructions 23
Data Processing Instructions (1)
 Arithmetic and logical operations
 3-address format:
 Two 32-bit operands
(op1 is register, op2 is register or immediate)
 32-bit result placed in a register
 Barrel shifter for op2 allows full 32-bit shift
within instruction cycle

24
Data Processing Instructions (2)
 Register movement operations:
 MOV, MVN
 Arithmetic operations:
 ADD, ADDC, SUB, SUBC, RSB, RSC
 Bit-wise logical operations:
 AND, EOR, ORR, BIC
 Other operations:
 E.g., Comparison, we can also include multiplication

25
Data Processing Instructions (3)

Conditional codes
+
Data processing instructions
+
Barrel shifter
=
Powerful tools for efficient coded programs

26
Data Processing Instructions (4)

e.g.:

if (z==1) R1=R2+(R3*4)

compiles to

ADDEQ R1,R2,R3, LSL #2

( SINGLE INSTRUCTION ! )

27
Data Transfer Instructions
 Load/store instructions
 Used to move signed and unsigned word, half word and byte to
and from registers
 Can be used to load PC
(if target address is beyond branch instruction range)
LDR Load Word STR Store Word
LDRH Load Half Word STRH Store Half Word
LDRSH Load Signed Half Word STRSH Store Signed Half Word
LDRB Load Byte STRB Store Byte
LDRSB Load Signed Byte STRSB Store Signed Byte 28
Block Transfer Instructions
 Load/Store Multiple instructions
Mi
(LDM/STM) LDM
Mi+1
 Whole register bank or a subset R0
Mi+2
is copied to memory or restored R1

with a single instruction R2

Mi+14
Mi+15
R14 STM
R15

29
Multiply Instructions
 Integer multiplication (32-bit result)
 Long integer multiplication (64-bit result)
 Built in Multiply Accumulate Unit (MAC)
 “Multiply and accumulate” instructions add product to running
total

30
Software Interrupt
 SWI instruction
 Forces CPU into supervisor mode
 Usage: SWI #n

31 28 27 24 23 0
Cond Opcode Comment field (ignored by processor)

 Suitable for running privileged code and making OS calls

 Comment field is ignored by processor but typically used by the
interrupt handler
 E.g., may pass a number to specify the handler ID
31
Branching Instructions
 Branch (B): jumps forwards/backwards up to 32 MB
 Branch link (BL): same as (B) + saves (PC+4) in LR
 Suitable for function call/return
 Condition codes for conditional branches
 Branch exchange (BX) and Branch link exchange (BLX):
same as (B/BL) + exchange instruction set (ARM  THUMB)
 Only way to swap instruction sets

32