VUMMENTHALA SUSHMA
B. Tech in Electronics and Communication Engg.,
Mobile: +91-9515030396
H. No: 2-3-647/A/63, Email:sushmareddy1397@[Link]
New Prem Nagar, Amberpet, Hyderabad– 500013.
CAREER OBJECTIVE
Seeking a position in an organization within the VLSI industry where I can contribute my
knowledge and skills for organization’s growth as well as myself.
CORE COMPETANCY
Good Knowledge about ASIC design flow.
Good at implementation of efficient floorplan with high macro count with the help of data
flow diagram and achieving optimum IR drop.
Performing Power aware Placement with less congestion which ensures good routability.
Proficient in implementing Physical Design flow stages like Power Planning, Clock Tree
Synthesis, Routing.
Good at understanding and analysing STA timing reports at each stage of PnR flow.
Comprehensive Knowledge on Static Timing Analysis and terminologies like Setup and
Hold, OCV, AOCV, CRPR, Clock Uncertainty etc.
Comprehensive knowledge on Digital design concepts and fundamentals of CMOS .
Have hands-on experience in industry standard EDA tools like IC Compiler II and Prime
Time from Synopsys.
Good at working with Linux environment.
ACADEMIC PROFILE
CGPA /
Degree Board / University Year
Percentage
Advanced Diploma in ASIC
RV-VLSI Design Center 2020 -
Design
B. Tech [Electronics and CVR College of
2015 - 2019 9.56 /10
Communication Engineering] Engineering,Ibrahimpatnam
Narayana Junior College,
Intermediate [MPC] 2013 - 2015 97.5%
Dilsukhnagar
Swamy Dayanand High
SSC 2013 10 /10
School, Amberpet
ACHIEVEMENTS & EXTRACURRICULAR ACTIVITIES
Awarded a merit momento by our school Principal for achieving 10 CGPA in SSC.
Participated as a Volunteer in “33rd International Conference on VLSI Design 2020”.
PROJECTS
DOMAIN SPECIFIC PROJECTS:
1) Block level Implementation in 40 nm Technology
Technology – 40nm, Supply Voltage -1.1V, Operating frequency – 1GHz, No. of clocks -05,
Macro count – 34, Area – 4.2 sqmm, Metal layers –07, Power consumption- 600mW, IR drop
budget -5% (VDD+VSS).
Tools
IC Compiler II from Synopsys.
Challenges
Performing efficient floorplan with more hard macros while providing the contiguous
core area for the placement of standard cells.
Performing multiple iterations of Powerplan to achieve the optimum IR drop as per
the specification without floating nets.
Reducing congestion during the Placement stage and performing Clock Tree
Synthesis using NDR rules.
2) Static Timing Analysis for Various Timing Paths
Performing Static Timing Analysis for the design with all kinds of timing paths and
analysing the timing reports by providing Design Constraints, Gate Level Netlist and Timing
libraries as inputs.
Tools
Prime Time from Synopsys
Challenges
Analysing the timing reports at every stage of APR flow which includes timing
exceptions such as half-cycle and multi-cycle paths, Differentiating false paths from
set of real paths.
Analysing the timing reports when clock uncertainty, CRPR, latency, skew, derate
factors, I/O delays are included for different timing paths.
Analysing the reports for Latch based designs by understanding Time-borrow
concepts.
Interpreting and visualizing the circuit from the timing reports.
B. TECH FINAL YEAR PROJECT:
Comparision of various low power design techniques for the reduction of leakage power in
CMOS Full Adder Circuit.
Designing of Full Adder Circuit using various low power design techniques like Sleep
Transistor technique, Stack technique, Sleepy Stack technique and Sleepy Keeper technique.
The designs are implemented in 90nm Technology at a schematic level with a power supply
of 1.2V. The power and delay values are calculated and compared for all the techniques.
Tools
Cadence Virtuoso Tool
.
PERSONAL DETAILS
Nationality : Indian
Date of Birth : February 13, 1997
Hobbies : Listening to music, Cooking, Dancing
Languages Known : English, Telugu, Hindi
DECLARATION
I hereby declare that the statements made above are true, complete and correct to the best of my
knowledge and belief.
Place : Hyderabad
Date : Vummenthala Sushma