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EECS 2021 Computer Organization Exam Sample

This document is a sample exam for a computer organization course. It provides instructions for taking the exam such as filling out identifying information, duration of the exam, and rules. The exam contains 10 multiple choice questions about RISC-V programming and concepts like pipelining, caches, and multiplexers. It also includes sample Verilog code for a 2-bit multiplexer.

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Roman Kovalchyk
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0% found this document useful (0 votes)
176 views5 pages

EECS 2021 Computer Organization Exam Sample

This document is a sample exam for a computer organization course. It provides instructions for taking the exam such as filling out identifying information, duration of the exam, and rules. The exam contains 10 multiple choice questions about RISC-V programming and concepts like pipelining, caches, and multiplexers. It also includes sample Verilog code for a 2-bit multiplexer.

Uploaded by

Roman Kovalchyk
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Name:

(Family/Last name) (Given/First name)

Student ID#: Registered Section:

York University
Department of Electrical Engineering and Computer Science
EECS 2021.03: Computer Organization
Exam – SAMPLE
NOTE: This sample exam is intended neither to list all the subjects to be covered during the
final exam nor to be a comprehensive set of exercises sufficient for your preparations for the
exam. Instead, it is intended to show you the structure of the exam, the way answers should be
recorded, and the level of of the final exam’s difficulty.

Rules and Instructions


• York University examination rules are in effect.
• This is a 180 minute-long, closed-book exam. No aids are allowed. In particular, the use
of calculators, laptops, tablets, or smartphones is not permitted.
• Fill in the box at the top of this page. Ensure your student number is filled-in correctly on
the Scantron sheet.
• Answer ALL questions by filling in the appropriate letters on the Scantron sheet provided
using an HB / No. 2 pencil. Your answers are machine marked so be sure to fill in the
bubbles very carefully. Blank, wrong, and multiple answers score zero (0). Also circle
your answers in this examination booklet as backup. Both the examination booklet and
the Scantron must be submitted together.
• Keep your eyes on your own work. At the discretion of the invigilators, students may be
moved.
• There are 68 questions and 22 pages in this double-sided booklet. Inform an invigilator if
your booklet is incomplete.
• Do not detach any pages from this booklet.

1
Question 1.
Consider a 1000 character-long text T represented in ASCII format. Assuming that the first
character of T is stored at address 1024 in main memory, what is the address of the last charac-
ter:

A. 2023, D. 9024,
B. 2024, E. none of the above.
C. 9023,

Question 2.
Consider a RISC-V program stored at address x1. What is the value of PC register so that the
execution of the program can begin:

A. 0, D. x1+8,
B. x1, E. sp-x1,
C. x1+4, F. depends on the 1-st instruction.

Question 3.
How many different register fields does a RISC-V instruction have?

A. 0, D. 32,
B. 1, E. depends on the instruction.
C. 3,

For the next two questions consider this RISC-V program:

addi x1,x0,1
beq x1,x1,16
addi x2,x0,2
addi x2,x0,3
addi x2,x0,4
addi x2,x0,5
addi x3,x0,6

2
Question 4.
The execution of this program will result in:

A. x2=0, D. x2=4,
B. x2=2, E. x2=5,
C. x2=3, F. x2=6.

Question 5.
The branch address 16 is represented in the immediate field of the beq x1,x1,16 instruction code
as number (in decimal):

A. 1, D. 8,
B. 2, E. 12,
C. 4, F. 16.

Question 6.
Consider the implementation of RISC-V datapath with control as discussed in class (consult the
datapath figure in lecture notes). The role of the adder Add is to:

A. calculate the address of the next instruction in sequential execution;


B. to perform arithmetic or logical operations when ALU is busy with other operations;
C. to augment the functionality of ALU in pipelining;
D. to shift the input by 4;
E. none of the above.

Question 7.
Complete this sentence so that it describes a fact concerning pipelines. Pipeline hazards:

A. exist only in theory because efficient implementation of pipelining is not possible;

B. increase in frequency when CPU’s speed is decreasing;

C. can be eliminated by expending cache;

D. can be reduced using a range of techniques but for some programs, they cannot be com-
pletely eliminated;

E. all of the above are facts about pipelining.

3
Question 8.
The main role of cache is:

A. to eliminate large but slow main memory,

B. to expand the limited number of CPU registers,

C. to support pipelining,

D. to prevent hazards occurring in pipelining,

E. none of the above.

For the next two problems use this circuit of a 2-bit multiplexer and a Verilog code dmo
(similar to those that you experimented with in your last labs).

Question 9.
Assuming that yMux1 is 2-to-1 multiplexer, does the code dmo correctly implement the de-
picted multiplexer:

A. yes, it does;

B. no, the inputs a and b should be declared as 2-bit registers;

C. no, the inputs a and b should be declared as 2-bit wires;

D. no, input the c should be declared as 2-bit register;

E. no, the input c should be declared as 2-bit wire.

4
Question 10.
Suppose that the above code is correct or can be easily fixed. Given the inputs a=10, b=01, what
is the value of z:

A. 10, D. 11,
B. 01, E. depends on c.
C. 00, F. none of the above

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