This article has been accepted for publication in a future issue of this journal, but has not been

fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

Self-Powered 380V DC SiC Solid-State Circuit

Breaker and Fault Current Limiter
D. Marroquí, José M. Blanes, A. Garrigós, Senior Member, IEEE, R. Gutiérrez

1Abstract— This article presents a new ultrafast DC Solid uninterruptible power supply (UPS), required for critical
State Circuit Breaker (SSCB) that uses a Silicon Carbide (SiC) situations, is based on batteries. In many papers, DC
cascode as the main switching and limiting semiconductor and distribution has been proposed for this application [8-11],
an isolated photovoltaic driver to control it. The proposed reducing the conversion steps and total losses, resulting in
topology is self-powered and fully implemented with discrete more efficient, reliable and economic data centers. Among all
parts.
the proposals, 48V and 380V DC distribution have been the
The SSCB’s cascode can work in three different states: fully
on during nominal operation, linear mode for current limitation
two most promising alternatives to the conventional AC
and fully off to disconnect the load. The time the SSCB operates distribution. Between these two alternatives, previous studies
in linear mode and the maximum current limit are easily set by show that the 380V DC option is better than 48 V as it has
discrete components. Control inputs have been also included to higher efficiency and lower costs [10].
reset the SSCB after a fault has been removed or to remotely As in AC systems, protection devices are also needed in
switch it on or off. 380V DC distribution systems in order to provide protection
This device can be used in DC distribution avoiding against overloads and faults. In [11] it is proposed a 3-level
deterioration due to the problems associated with electric arcs protection hierarchy architecture for 380V DC data centers
and mechanical aging of moving parts, limiting inrush currents where the lower level is the individual protection with a
and also minimizing conduction losses respect other kind of circuit breaker (CB) of each 2U (380V-2.5A) or 4U (380V-
circuit breakers.
3.5A) server. However, the lack of cost-effective DC
Functional, thermal and efficiency tests have been carried out
with three different 380V prototypes. Experimental results show
protection solutions remains a major barrier, hindering the
the excellent behaviour of the SSCB, it is able to block a 380V transition to efficient 380V DC power distribution [12].
short circuit failure in 570ns, authors have not found any faster There are some important issues in DC system protection
results in the literature. that must be considered when designing these protection
devices [13-15]:
Index Terms— Solid State Circuit Breaker (SSCB), Fault
Current Limiter, DC power distribution, WBG Semiconductors, 1. Arcing at the moment of disconnection: This issue
SiC cascode. is not important in AC systems because of the naturally
zero crossing of the AC current, but in DC systems it is
I. INTRODUCTION very important to have a method that assures that the load
Although AC is the dominant form of electric power current is zero before the physical disconnection of the
distribution, DC distribution systems are becoming more and load from the grid.
more popular [1,2]. The main reason is the progressive 2. DC loads usually have a high input capacitance to
change of the type of loads connected to the main grid. filter high frequency harmonics caused by switching DC-
Currently, DC loads, such as LED lights, computers, DC converters. The inrush current associated with this
communications and battery chargers, need an AC/DC capacitance may cause unexpected CB trips when the load
converter as a first stage to be connected to the AC grid, is first connected to the DC distribution system. On the
increasing power losses and costs [3]. Therefore, direct DC other hand, it is important to limit this inrush current
power distribution is an interesting option for systems with because it can cause voltage sags affecting other loads.
large amount of DC electronics loads and, in recent years, it 3. The high distributed capacitance in the DC bus
has been successfully applied in shipboards, airplanes, deals in very fast and high discharge currents in case of
telecommunication systems, buildings, electric vehicle low impedance load or short-circuit. This issue will affect
charge stations and data centers [1-7]. other loads if the fault is not isolated very fast.
Focusing on data centers, the increase in cloud computing
and internet services, has driven an exponential increase of In the market it can be found traditional mechanical DC
their electric consumption. Nowadays, data centers consume circuit breakers with different current ratings. However, these
about 3% of the world’s electricity production and it is breakers cannot deal with the issues previously listed because
estimated that it will double every five years [8]. Most of the of their slow response time, low lifetime due to the arcing and
data center loads are computers, servers, routers, switches and their lack of current limiting capability [2,16]. In the
storage devices, which are DC loads. Besides, the literature some DC Solid State Circuit Breakers (SSCB)

This work was supported by the Spanish Ministry of Economy and Alicante. Spain (e-mail: dmarroqui@[Link]; jmblanes@[Link];
Competitiveness through the research project ESP2015-68117-C2-2-R. augarsir@[Link]; [Link]@[Link]).
(Corresponding author: D. Marroquí)
D. Marroquí, José M. Blanes, A. Garrigós, R. Gutiérrez are with Industrial
Electronics Group (IE-g). Av. Universidad sn. Ed. Torrevaillo. 03202. Elche,

0885-8993 (c) 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission. See [Link] for more information.
This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

based on power semiconductors have been also proposed [14- C. Timer and latching circuit:
18]. They are very attractive due to their ultra-fast current
The time constant given by the R1-C1 network sets the time
interruption, arc-less interruption and current limiting
in which the SSCB operates in linear mode (Latching Time),
capability. However, their main drawback is the conduction
limiting the current to a preconfigured maximum value after
losses due to the semiconductor on resistance during nominal
a failure is detected and before the load is fully disconnected.
operation. As an alternative, hybrid solutions have also been
If the fault extinguishes before the Latching Time the circuit
proposed [19-22], using a mechanical switch in parallel with
returns to its nominal operation. The latching circuit R9, R10,
a semiconductor device allows low power losses, arc-less
R11, R12, R13, R14, Q3, Q4 and D2, provides a precise transition
interruption, current limiting and reasonable interruption
from Current Limiting Mode to Off Mode (open circuit).
speeds, but they are more complex and expensive.
The advent of new Silicon Carbide (SiC) semiconductors D. Biasing zener and current source:
has reactivate the option of using SSCBs [23-31]. The main
reason is that SiC devices have lower conduction resistance The protection is self-powered, it is supplied directly from
its input, the 380V bus, without needing auxiliary sources. Z1
than their Silicon counterparts, besides their thermal
acts as an internal power supply and sets the proper voltage
impedance is better and also, they can work at higher junction
for the current sensor, timer and latching circuit. Thus, these
temperatures, reducing the risk of failure due to high junction
circuits are also referred to zener voltage, minimizing power
temperature. Performance evaluation of multiple Si and SiC
devices for circuit breakers in 380V DC systems have been losses and voltage stress. A current source, J1 and R8, is used
for Z1 biasing. To minimize the J1 thermal stress, the current
reported in [24, 25], concluding that 1200V SiC devices are
flowing through it must be minimized. The losses of the
the best option for this application, and presenting a 5A/380V
current source are given by (1).
design based on a normally-on SiC JFET. The main drawback
of using a normally-on device is that the driver has to be
carefully designed to assure that the breaker trips off in a fault 𝑊𝑊𝐽𝐽1 = 𝑉𝑉𝐽𝐽1 · 𝐼𝐼𝐽𝐽1 ≈ (𝑉𝑉𝐼𝐼𝐼𝐼 − 𝑉𝑉𝑍𝑍1 ) · 𝐼𝐼𝐽𝐽1 (1)
condition. The proposed solution is quite complex and it E. Driver:
needs a high ratio buck DC/DC converter to power the driver
and a DSP to control the circuit. In [30] it is presented a An isolated photovoltaic driver (PV1) is used to control the
12.5A/400V SiC-based circuit breaker, its novelty is based on SiC cascode, M1. This solution offers the following
a control method of the gate voltage to reduce the overvoltage advantages over other isolated driver circuits: high electrical
across the semiconductor during the interruption process. The isolation capability, do not require external power supply, it
gate signal is generated by a Digital Signal Controller (DSC) provides direct analog voltage to operate the main cascode in
and a high-speed D/A converter with its ancillary power linear mode, simple fast turn-off circuits could be used (often
supply is also needed to sense the current. integrated in the driver) and finally, low photo-cell current
In this paper it is presented a simple ultra-fast self-powered enables naturally slow turn-on (especially attractive for
SSCB and fault current limiter based on a SiC JFET cascode inrush current control).
for 380V DC distribution systems. PV1 primary LED current is controlled by Q2 transistor and
The rest of the paper is organized as follows. Section II it will be drained through J1, so the current through through
introduces the proposed circuit and its principle of operation. J1 is 𝐼𝐼𝐽𝐽1 ≈ 𝐼𝐼𝑍𝑍1 + 𝐼𝐼𝑃𝑃𝑃𝑃1
Section III describes the experimental prototype and the most F. Remote Reset and Turn OFF:
relevant results obtained. The paper concludes with Section
IV. Two optoisolated inputs (Reset and Off) have been
included to control the SSCB. The Reset input is used to
II. PROPOSED SOLID STATE CIRCUIT BREAKER reconnect the SSCB from the off mode. It is performed
discharging C1 (latching circuit). Besides, the Off control
The proposed SSCB is based on a SiC cascode and an
input forces the SSCB to disconnect the load, opening Q2 and
isolated photovoltaic driver to generate the floating gate-
disconnecting the power supply to PV1.
source voltage needed to control it. The cascode works fully
on during nominal operation, in linear mode for current G. Freewheeling diode:
limitation and fully off to disconnect the load. The proposed
Finally, the SSCB includes a freewheeling diode (DFW) to
circuit is shown in Figure 1, it is self-powered and has been
handle inductive loads and prevent overvoltage in M1.
fully devised with discrete parts.
D1
The SSCB is divided into the following functional blocks: M1
RSHUNT ILOAD
In Out
A. Main Semiconductor: R13 Q1-1 Q1-2
R10
C1
As commented before, the circuit is based on a SiC cascode Reset D2 R6 R5
(M1) controlled by an isolated photovoltaic driver (PV1). R11
Off
Z1
R9 O1
B. Current Sensor: O2 Q3 Q4 Q2 R7
IBIAS

R2
It is made up by the current measuring resistor RSHUNT, the R1 R12 R14 R4 R3
two matched transistors Q1-1 and Q1-2, the biasing resistors R3 J1 I1 PV1
and R4 and the gain resistor R5. GND
DFW
R8

Figure 1: Electrical schematic of the proposed Solid State Circuit

Breaker.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

The SSCB operation is explained below with the help of cascode limiting the load current to the current limit threshold
Figure 2. Five different operation modes are identified: On (ILIMIT). The voltage balance given by (3) forces Q2 to regulate
Mode, Delay Mode, Protection Mode, Current Limiting the PV1 LED current, which generates the proper gate-source
Mode and Off Mode. voltage from the driver photo-cells. The low short-circuit
current of the driver ensures a very slow M1 switch-on
 t0 – On Mode:
dynamic, thus preventing oscillations and instabilities in the
In this mode, the cascode, M1, is fully on, supplying the SSCB. The equivalent circuit of the SSCB during this time
required current to the load, ILOAD. The equivalent circuit in interval is shown in Figure 3-d.
this state is shown in Figure 3-a. The voltage drop on RSHUNT The SSCB remains in Current Limiting Mode until Q3 turns
is not enough to activate Q1-1, so Q2 remains saturated, off and Q4 turns on. This time (tlatching) is adjusted by the timer
allowing a current flow through the primary LED of the circuit, R1-C1. Latching time is finally given by (5), where it
photovoltaic driver (PV1) and therefore providing at the driver is assumed R9 >> R1. This mode can be also used to limit the
output the open circuit voltage (Voc(PV1)) to M1 gate-source inrush current associated with the load input capacitance. So,
voltage. D1 is also in on-state, keeping Q3 switched on and the the Latching Time must be carefully designed depending on
timer capacitor, C1, discharged. The Q1-2 current, named IBIAS, the type of loads.
is defined by (2).
𝑉𝑉(𝑍𝑍1 )−𝑉𝑉𝐹𝐹 (𝐷𝐷1 )
𝑉𝑉(𝑍𝑍1 )−𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 ·𝑅𝑅𝑆𝑆𝑆𝑆𝑈𝑈𝑁𝑁𝑁𝑁 −𝑉𝑉𝐸𝐸𝐸𝐸 (𝑄𝑄1−2 ) 𝑡𝑡𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙ℎ𝑖𝑖𝑖𝑖𝑖𝑖 = 𝑅𝑅1 · 𝐶𝐶1 · ln (5)
𝑉𝑉𝐸𝐸𝐸𝐸 (𝑄𝑄3 )
𝐼𝐼𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 = (2)
𝑅𝑅3
If the fault (or an inrush current) extinguishes before the
The circuit will stay in this state until ILOAD reaches the Latching Time, Q2 will be turned on again, supplying PV1 and
necessary current level to activate Q1-1. In this case, naming thereby turning on M1. This returns the SSCB to the previous
ILIMIT the maximum ILOAD current. This current limit, ILIMIT, is state (On Mode), otherwise the circuit will enter in Off Mode.
given by (3), where IB(Q1-1) and IB(Q1-2) have been neglected
and it is assumed VEB(Q1-1) = VEB(Q1-2).
ILIMIT
𝐼𝐼𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 ·𝑅𝑅5 �𝑉𝑉(𝑍𝑍1 )−𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 ·𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 −𝑉𝑉𝐸𝐸𝐸𝐸 (𝑄𝑄1−2 )�·𝑅𝑅5
𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 = = (3)
ILOAD

𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆 𝑅𝑅3 ·𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆

t
Assuming V(Z1) >> (ILIMIT·RSHUNT + VEB(Q1-2)), the current V(Z1)-VECon(Q1-1)
limit threshold is finally approximated by (4).
V(R4)

IB(Q2)·R4
𝐼𝐼𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 ≈
𝑉𝑉(𝑍𝑍1 )·𝑅𝑅5
(4) t
𝑅𝑅3 ·𝑅𝑅𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆𝑆
I(PV1 LED)

 t1 – Delay Mode:
Just after the load current exceeds the current limit, the
SSCB starts a very short delay interval in which it does not t
limit current. As it can be observed in Figure 2, as soon as Q1- VOC(PV1)
VGS(M1)

1 is activated, Q2 is turned off and the PV1 LED current is

removed fast, however M1 capacitances must be discharged
before the SSCB is able to limit the current. The equivalent t
circuit is shown in Figure 3-b. This delay time depends on the
VIN
driver turn-off circuit and the M1 characteristics.
VDS(M1)

 t2 – Protection Mode:
t
Once M1 capacitances are discharged, it is turned off,
≈ (VOUT-VF(D1)) / R1
protecting the main DC bus and isolating the faulty load as
fast as possible. Besides, Q1-1 is turned off and Q2 saturates,
I(D1)

allowing again a current flow through the primary LED of t

PV1. Nevertheless the cascode continues off until the driver
V(Z1)-VF(D1) Latching Time
output voltage exceeds the threshold voltage, at this moment
τ = R1·C1
the SSCB will enter in Current Limiting Mode. The increase
V(R1)

VBEon(Q4)≈0,7V
of VDS(M1) forces D1 to turn off and the timer circuit starts t
charging C1. The Protection Mode time depends on the driver
Protection Mode

turn-on circuit and the M1 characteristics. The equivalent Delay Mode

SSCB is shown in Figure 3-c. Current

I(D2)

On Mode Off Mode

Limiting Mode
 t3 - Current Limiting Mode: VZ t
Current limiting mode refers to that mode of operation in t0 t1 t2 t3 t4
which the circuit maintains a constant current at a predefined Figure 2: Most important voltage and current waveforms during
value (ILIMIT). After the fault has been isolated, the current overload. From top to bottom: Load Current, V(R4), PV1 LED
feedback loop performed by Rshunt, Q1-1, Q1-2 and Q2 current, VGS(M1), VDS(M1), I(D1), V(R1), I(D2).
increments VGS(M1) dealing in a linear operation of the main

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

 t4: Off Mode: UJN1205K JFET and has been adjusted to 10mA in order to
If the fault remains active, after the predefined Latching minimise power losses (estimated losses around 3.7W). R3
Time, Q3 turns off and Q4 turns on. As soon as Q4 turns on, has been set to 51kΩ, obtaining IBIAS = 180µA and RSHUNT is
D2 also switches on and forces Q1-1 to saturation. During this 10mΩ. A DMMT5401 dual matched PNP transistor has been
time, R6 limits IC(Q1-2), avoiding variations in the ILIMIT value. selected for Q1-1 and Q1-2. The other relevant parts have been
Then, Q2 turns off, removing completely the PV1 LED varied depending on each particular test (see Table I).
D1
current. The SSCB remains latched through Q1-1, D2 and Q4,
ILOAD M1
needing an external input signal (Reset) to be restarted. In this In
RSHUNT
Out
state, the corresponding circuitry is as shown in Figure 3-e. R10
R13 Q1-1 Q1-2
C1
Reset D2 R6 R5 Off
III. EXPERIMENTAL RESULTS R11 Z1
O2 R9 O1
To verify the theoretical developments three different Q3 Q4 Q2 R7

IBIAS
R2
SSCBs has been designed and implemented. The SSCBs have R12
a) R1 R14 R4 R3
been designed for a 380V DC distribution system with
J1
different maximum load current limits (1.5A, 2.7A and 4.4A), I1 PV1
DFW
assuming a 50µF maximum load input capacitance and R8
D1
adjusting the Latching Time so they can deal with the inrush
ILOAD M1
current needed to charge this capacitance. In Table I it is In
RSHUNT
Out
shown the main characteristic of the three designed SSCBs. R10
R13 Q1-1 Q1-2
C1
Reset D2 R6 R5
TABLE I: Off
R11 Z1
DESIGNED SSCB BASICS CHARACTERISTCS O2 R9 O1
Q3 Q4 Q2 R7

IBIAS
SSCB Theoretical Parameters R2
ILimit = 1.5A b) R1 R12 R14 R4 R3
R2=10kΩ ; R3=51kΩ ; R4=51kΩ R5=86Ω ; J1 I1 PV1
R7=50kΩ ; V(Z1)=10V
Solid State R8
DFW
RSHUNT=0.01Ω ; VEB(Q1-2)=0.7V
Circuit Breaker 1
Latching Time = 22ms D1
(SSCB 1)
R1=180kΩ ; C1=47nF ; V(Z1)=10V RSHUNT ILOAD M1
In Out
VF(D1)=0.7V ; VBE(Q4)=0.7V
R13 Q1-1 Q1-2
R10
C1
ILimit = 2.7A Reset D2 R6 R5 Off
R2=10kΩ ; R3=51kΩ ; R4=51kΩ R5=147Ω ;
R11 Z1
R7=50kΩ ; V(Z1)=10V O2 R9 O1
Solid State Q3 Q4 Q2 R7

IBIAS
RSHUNT=0.01Ω ; VEB(Q1-2)=0.7V
Circuit Breaker 2 R2
Latching Time = 15ms
(SSCB 2) c) R1 R12 R14 R4 R3
R1=180kΩ ; C1=33nF ; V(Z1)=10V
VF(D1)=0.7V ; VBE(Q4)=0.7V J1 I1 PV1
DFW
R8
ILimit = 4.4A D1
R2=10kΩ ; R3=51kΩ ; R4=51kΩ R5=240Ω ; M1
RSHUNT ILOAD
Solid State R7=50kΩ ; V(Z1)=10V In Out
Circuit Breaker 3 RSHUNT=0.01Ω ; VEB(Q1-2)=0.7V R13 Q1-1 Q1-2
R10
(SSCB 3) Latching Time = 10ms C1
Reset D2 R6 R5
R1=180kΩ ; C1=22Ω ; V(Z1)=10V Off
VF(D1)=0.7V ; VBE(Q4)=0.7V R11 Z1
O2 R9 O1
Q3 Q4 Q2 R7
IBIAS

R2
USCi’s UJC1206K cascode has been selected as the main d) R1 R12 R14 R4 R3
power semiconductor controlled by the photovoltaic driver J1 I1 PV1
Vishay’s VOM1271. A SiC JFET cascode has been selected DFW
R8
instead of a SiC MOSFET because the on resistance is lower
D1
in devices with similar current and voltage ratings. The M1
ILOAD
UJC1206K (60mΩ) vs C2M0080120D (80mΩ) are In
RSHUNT
Out
representative devices, the use of the cascode represents an R10
R13 Q1-1 Q1-2
C1
improvement of 25% in conduction losses. Furthermore, SiC Reset D2 R6 R5 Off
cascode behavior under short circuit condition is better than R11 Z1
SiC MOSFET [32] O2 R9
Q3 Q4 Q2 R7
O1
IBIAS

It´s worth noting than in case of short circuit failure the R2

cascode selected will operate out of the Safe Operation Area e) R1 R12 R14 R4 R3

defined in the datasheet, but the aim of this paper is limited J1 I1 PV1

to demonstrate the correct behaviour of the proposed R8

DFW

topology. Other component should be chosen, or the latching

time/ limit current should be reduced for long term reliability. Figure 3: SSCB Equivalent States Circuits (a) Equivalent circuit
Please refer to Table II for the most relevant electrical during On Mode operation (b) Equivalent circuit during Delay Mode
characteristics of the power cascode and the photovoltaic (c) Equivalent circuit during Protection Mode. (d) Equivalent circuit
driver. The voltage reference is obtained from a 10V zener during Current Limiting Mode. (e) Equivalent circuit during Off
diode, (Z1). The biasing source, J1-R8, uses a USCi’s Mode.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

In Figure 4 it is shown the electronic main board of the load capacity is discharged, the SSCBs run under a short-
implemented SSCBs and the final prototype. A black circuit condition. As shown in Figure 5, due to the slow
anodized heatsink is used to reduce the cascode and JFET dynamics of the M1 gate charging process, no overshooting of
working temperature. the current is produced. The SSCB reaches its maximum
current while charging the load input capacitor. For the
TABLE II:
conditions analysed, the necessary time for charging the input
UJC1206K AND VOM1271 MAIN
ELECTRICAL CHARACTERISTICS (DATASHEET) capacitor is shorter than the tlatching (5). Therefore, the SSCB
UJC1206K VOM1271 does not change from Current Limiting Mode to Off Mode,
Parameter Value Parameter Value remaining in On Mode supplying the load.
Typ. Input
VDS max 1200V 10mA
Current
38A @25ºC Photo-Cell OC
ID max 8.4V @10mA
24A @100ºC Voltage
Photo-Cell SC
RDSon (max) 60mΩ 15µA @10mA
Current
Isolation
VGSth 4.9V 4500V
Voltage
Ciss 2214pF

Matched
In Transistors Commands Shunt 35.9mm

Figure 5: SSCB start limiting inrush current. Start with R-C load
(400Ω - 50µF) at 380V. Upper figure: Load Current (ILOAD)
(1A/division). Lower figure: Main cascode drain-source voltage
a) Out Driver GND Freewheel Diode
b) (VDS(M1)) (100V/division). Time scale: 5ms/division.
32.8mm

 Test II: SSCB 2 Overload sweep

In this test, the SSCB 2 as a representative sample, has been
used. Different overload levels have been carried out with a
380V input voltage. A pure resistive load of 200Ω is initially
available, and three different step loads (100Ω, 66Ω and 50Ω)
32.5mm

are performed in order to exceed the maximum current

thresholds.

c)

Figure 4: SSCB prototype. (a) Top view without cascode and JFET
(b) Bottom view without cascode and JFET (c) Lateral view. 1A
5µs

Regarding the experimental setup, a Keysight N8937A

high-voltage, high-power supply unit has been used (1500V;
10A). The electrical load consists in a power bank of ten
resistors (Multicomp, MC14683, 100Ω, 225W, wire-wound).
It has 1kW nominal power capability at 1kV with 1.95mH
parasitic series inductance (measured). Resistor shunting is
possible using MOSFETs and a digital controller to produce
step load variations.
 Test I: Switch on limiting inrush current.
In this test, all SSCBs are switched on in real working
conditions. The supply voltage is 380V and a 400Ω load is
Figure 6: SSCB 2 Overload sweep waveforms from 200Ω to [100,
connected at the output in parallel with a 50µF capacitor. The 66, 50] Ω at 380V. Upper figure: Load Current (ILOAD) (2A/division).
SSCB is initially in Off Mode, in t=0s the SSCB is changed to Lower figure: Main cascode drain-source voltage (VDS(M1))
On Mode using the Reset remote control. After Reset, as the (100V/division). Time scale: 5ms/division.

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

For the conditions analysed, the necessary time for and remains until the Latching Time ends and the load is fully
charging the input capacitor is shorter than the tlatching (5). disconnected, isolating the failure from the main DC Bus.
Therefore, the SSCB does not change from Current Limiting
Mode to Off Mode, remaining in On Mode supplying the SW1
SSCB

load. After that, the SSCB initiates a controlled start-up up to

+ -

ILOAD
the ILIMIT current (2.75A). Finally, after the Latching Time, + VDS(M1)
RLOAD

the SSCB disconnects the load from the source.

ILOAD SW3
VDS(M1) SW2
 Test III: Overload Start. MDO3104
In this test the three SSCBs are started under constant N8937A 590µF (x2) THDP0200
TCP0030A
overload conditions. The input voltage is 380V and a pure Figure 8: Short circuit test setup.
resistive load of 50Ω is available, resulting in a 7.6A current
demand, higher than ILIMIT of each SSCB. As in Test I, the In this test, the cascode turn-off time is faster than
SSCBs are in Off Mode state and are started with the Reset VOM1271 datasheet specification. In authors’ opinion, this is
command in t=0s. The results of the tests are shown in Figure due to the effect of the voltage across the cascode source
7. The SSCBs start and immediately operate in Current parasitic inductance on the fast turn-off circuit included in the
Limiting Mode providing the maximum current to the load. driver.
Finally, the load is disconnected after the latching time.

5A
500ns

100V
500ns

Figure 9: SSCB short circuit test waveforms. 300Ω to short

Figure 7: SSCB Overload start waveforms. Start with pure circuit. Upper figure: Load Current (ILOAD) (5A/division). Lower
resistive load (50Ω) at 380V. Upper figure: Load Current (ILOAD) figure: Main cascode drain-source voltage (VDS(M1))
(1A/division). Lower figure: Main cascode drain-source voltage (100V/division). Time scale: 3.5ms/division.
(VDS(M1)) (100V/division). Time scale: 5ms/division.
 Test V: Remote Reset-Off Control signals.
 Test IV: Short Circuit Protection. Remote controls have been evaluated using SSCB 2 as the
This test validates the SSCB behaviour in the worst-case representative sample. Figure 10 shows the results. The input
scenario, a short circuit failure. SSCB 2 has been selected as voltage is 380V and 200Ω load is initially available, the load
the representative sample for this purpose. A dedicated setup presents an input capacitance of 50µF.
has been designed for this test, please refer to Figure 8. In At t=0s a step load to 50Ω occurs, so the load current
order to test the short circuit failure, the sequence is as exceeds the threshold (2.7A). After the Latching Time, the
SSCB 2 disconnects the load from the source. At t=75ms, the
follows: First of all, two 590µF capacitors
overload is removed, but the SSCB remains in Off Mode At
(947D591K132DJRSN - Cornell Dubilier) are charged at
t=100ms the remote Reset control is used and the SSCB is
380V via SW1. When the capacitors are charged, SW1 is reset to its initial operating condition, carrying out a
switched off and the capacitors are connected to the load controlled start-up. At t=300ms, the remote Off control is
(300Ω / 1.3A) through SW2. 6ms later, the short-circuit is used, then the SSCB immediately blocks the current and
carried out by switching on SW3. remains in Off Mode until the input supply is removed or
Figure 9 depicts the results obtained from nominal Reset command used.
operation to the end of the test. The SSCB is able to block the In addition to all the experimental tests shown, SPICE
short circuit in 570ns. In this time a peak current value of 35A simulations were also performed. The simulation results
is reached, this value is limited by the set-up parasitic exhibit good agreement with experimental measurements.
inductance (approximately 5µH). It can be also observed the Table III summarizes theoretical, simulation and
overvoltage generated in the drain-source voltage of the measurements results of the Latching Time and ILIMIT.
cascode due to its parasitic source inductance. After the
current is removed, the SSCB starts in Current Limiting Mode

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This article has been accepted for publication in a future issue of this journal, but has not been fully edited. Content may change prior to final publication. Citation information: DOI 10.1109/TPEL.2019.2893104, IEEE
Transactions on Power Electronics

Overload

Reset

Off

Figure 11: Efficiency vs Power in SSCB 3 with 380V input

supply.

The thermal images shown in Figure 12 are taken with a

Fluke Industrial Thermal Imager TI450. The results are from
SSCB 3 with a 100Ω load and 380V supply. The upper image
(without heatsink) was carried out after only one minute of
operation and the J1 temperature was still rising. The lower
image (with heatsink) was carried out once J1 was thermally
stable. The environmental conditions were controlled in a
Figure 10: Remote Reset-Off Control Signals. Upper figure: thermal stabilized chamber at 25ºC and 45% relative
Control signals. Center figure: Load current (ILOAD) (1A/division).
humidity.
Lower Figure: Cascode drain-source voltage (VDS(M1))
(100V/division) Time scale: 50ms/division.

TABLE III: SUMMARIZED THEORETICAL,

SIMULATION AND MEASURAMENT RESULTS
36.5ºC
SSCB ILimit tlatching
Theoretic 1.5A 22ms
SSCB 1 Simulation 1.52A 21.8ms ºC
Measured 1.45A 22.5ms 85
Theoretic 2.7A 15ms 85ºC 80
75
SSCB 2 Simulation 2.64A 14.9 ms
70
Measured 2.75A 12.5ms
65
Theoretic 4.4A 10ms
60
SSCB 3 Simulation 4.34A 9.9 ms
55
Measured 4.75A 8.75ms 31.2ºC
50
45
49.5ºC
 Test VI: Efficiency & Thermal analysis 35

In this test, the SSCB is evaluated from the efficiency and 25

thermal management perspective. It has been chosen SSCB 3
as representative sample due to its higher power range. The
tests have been carried out under nominal operating
conditions, the input voltage is 380V for all cases. The 56.2ºC
theoretical efficiency expression of the SSCB is determined
by 6.

WJ1 +(I𝐿𝐿𝐿𝐿𝐿𝐿𝐿𝐿 )2 ·R𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 Figure 12: Real thermal performance in temperature and
𝜂𝜂 ≈ 1 − (6) humidity-controlled conditions (25ºC and 15%). Upper Figure:
𝑃𝑃𝐼𝐼𝐼𝐼
SSCB 3 at 380V - 100Ω without heatsink. Lower Figure: SSCB 3 at
The efficiency of the SSCB as function of the output power 380V - 100Ω with heatsink
is shown in Figure 11. For this purpose, with 380V constant
input voltage a discrete load sweep has been carried out, the
efficiency has been measured with a Yokogawa WT1800
precision power analyser.

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IV. CONCLUSION Power Electronics Conference and Exposition - APEC 2014, Fort
Worth, TX, 2014, pp. 2300-2305.
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Transactions on Power Electronics

David Marroquí was born in Elche, Spain, in Valencia, Spain, in 2000, and the Ph.D. degree
1990. He received the [Link]. degree in from Miguel Hernandez University of Elche
industrial engineering from the Miguel (UMH), Spain, in 2007. He is currently
Hernández University of Elche, in 2015. He is Associate Professor at the Department of
currently an Assistant Professor in the Electronics Technology, UMH, and he spent
Department of Materials Science, Optics and research periods at CERN (Switzerland), from
Electronics Technology, Miguel Hernández 2002 to 2004, ESA (The Netherlands), 2008, and
University of Elche, Spain. He spent 4-month University of Strathclyde (UK), 2015. He
research period at Center of Reliable Power participated in more than 20 research and
Electronics in Aalborg University, Denmark in technology transfer projects and co-authored
2018. around 80 international publications, most of
His main research interests include space them related to power electronics. Nowadays,
power systems and industrial electronics and his main research interests focus on space power
electronics reliability. electronics and their ancillary electronic systems.

José M. Blanes was born in Elche, Spain, in Roberto Gutiérrez was born in Orihuela,
1974. He received the [Link]. degree on Spain, in 1977. He received his [Link]. degree on
telecommunication engineering from the telecommunication engineering in 2003, and
Polytechnic University Valencia in 1998 and the Ph.D degree in electronic engineering in
the Ph.D. degree on industrial technologies 2011, both from the Universidad Politecnica de
from the University Miguel Hernández of Valencia, Spain.
Elche in 2011. He is assistant professor in the Department
He is currently Associate Professor of of Communication engineering at Universidad
Electronics Technology at University Miguel Miguel Hernandez, Elche since 2003. His
Hernandez of Elche, Spain. His main research current research interests include the design of
areas are space power systems and industrial FPGA-based systems, computer arithmetic,
electronics. VLSI signal processing and digital
communications.
Ausiàs Garrigós (M’04, SM’16) was born in Xixona, Spain, in 1976. He
received the [Link]. degree in Electronic Engineering from the University of

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