Using Dynamic Cache Management Techniques
to
Reduce Energy in General Purpose Processors
Nikolaos E. Bellas, Ibrahim N. Hajj, and Constantine D. Polychronopoulos
Abstract—The memory hierarchy of high-performance and embedded processors has been shown to be one of
the major energy consumers. For example, the Level-1 (L1) instruction cache (I-Cache) of the StrongARM
processor accounts for 27% of the power dissipation of the whole chip [1], whereas the instruction fetch unit
(IFU) and the I-Cache of Intel’s Pentium Pro processor are the single most important power consuming
modules with 14% of the total power dissipation [2]. Extrapolating current trends, this portion is likely to
increase in the near future, since the devices devoted to the caches occupy an increasingly larger percentage
of the total area of the chip. In this paper, we propose a technique that uses an additional mini cache, the L0-
Cache, located between the I-Cache and the CPU core. This mechanism
can provide the instruction stream to the data path and, when managed properly, it can effectively eliminate
the need for high utilization of the more expensive [Link] propose, implement, and evaluate five
techniques for dynamic analysis of the program instruction access behavior, which is then used to proactively
guide the access of the L0-Cache. The basic idea is that only the most frequently executed portions of the code
should be stored in the L0-Cache since this is where the program spends most of its [Link] present
experimental results to evaluate the effectiveness of our scheme in terms of performance and energy
dissipation for a series of SPEC95 benchmarks. We also discuss the performance and energy tradeoffs that
are involved in these dynamic schemes. Results for these benchmarks indicate that more than 60% of the
dissipated energy in the I-Cache subsystem can be saved. Index Terms—Low-power-design, memory,
performance-tradeoffs, system-level.
I. INTRODUCTION
INRECENT years, power dissipation has become a major design concern for the microprocessor industry. The
shrinking device size, and the large number of devices packed in a chip die
coupled with the large operating frequencies, have led to unacceptably high levels of power dissipation.
The problem appears to be more acute in portable systems which operate under the energy constraints of a battery.
These systems need a small battery for portability, which should provide
enough energy to keep the system running for as long as possible. Hence, the energy dissipation of the portable
system should be low so that it does not drain the battery quickly. On
the other hand, desktop systems operate in an increasingly “hot” environment. The layout compaction and the high
operating frequencies entail high power densities and, thus, high thermal stresses on the chip. If this trend is not
controlled by low power techniques, the chip will have reliability problems, such as electromigration,
which is due to the high current densities on the metal interconnects. Such low-power techniques also help in
keeping the cost of packaging low, thus reducing the cost of the final product.
The problem of the wasted power caused by unnecessary activity in various parts of the CPU during code execution
has traditionally been ignored in code optimization and architecture
design. Processor architects and compiler writers are concerned with system performance/throughput and they do
little, if anything at all, to eliminate energy/power dissipation at this level.
Researchers in the CAD community have started tackling the problem of power minimization through compiler
transformations, yet this process is still in its infancy. On the other hand, power dissipation is rapidly becoming the
major bottleneck in today’s systems integration and reliability.
Modern microprocessors are large power consumers: Table I shows clearly the power increase for the faster versions
of the same processor families. Higher frequencies and larger transistor
counts more than offset the lower voltages and smaller devices, and they result in larger power consumption in the
newest version in a processor family. This has prompted many manufacturers
to design low-power versions of their flagship processors for use in the mobile and multimedia computing industry.
Clearly, designing a low-power, high-performance processor is considered an extremely hard problem, which can
only be solved if power or energy reduction is a concern from the beginning
of the design process and not only an afterthought. As processor performance continues to grow, and high-
performance, wide-issue processors exploit the available Instruction-
Level Parallelism, the memory hierarchy should continuously supply instructions and data to the data path to keep
the execution rate as high as possible. Very often, the memory hierarchy
access latencies dominate the execution time of the program. The very high utilization of the instruction memory
hierarchy entails high-energy demands on the on-chip I-Cache subsystem.
In order to reduce the effective energy dissipation per instruction access, we propose the addition of an extra cache
(the L0-Cache) which serves as the primary cache of the processor,
and is used to store the most frequently executed portions of the code, and subsequently provide them to the
pipeline. In our case, the L0-Cache is a small, direct-mapped cache which can
accommodate 64 to 128 instructions, and has a block size of 8 to 16 bytes. Our approach seeks to manage the L0-
Cache in a