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OpenTitan DFT Specification Process

This document provides OpenTitan design for test (DFT) flow commands to insert observability coverage counters (OCCs) into an ABC core design. It reads the standard cell library, top-level Verilog files for the ABC core and OCC/memory modules, sets the current design to ABC, processes the OCC specification to insert counters, runs synthesis, and writes out the post-insertion Verilog netlist.

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Prafulani Gajbhiye
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51 views1 page

OpenTitan DFT Specification Process

This document provides OpenTitan design for test (DFT) flow commands to insert observability coverage counters (OCCs) into an ABC core design. It reads the standard cell library, top-level Verilog files for the ABC core and OCC/memory modules, sets the current design to ABC, processes the OCC specification to insert counters, runs synthesis, and writes out the post-insertion Verilog netlist.

Uploaded by

Prafulani Gajbhiye
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as TXT, PDF, TXT or read online on Scribd

set_context dft -no_rtl -design_identifier occ

read_cell_library ../library/std_libs.[Link]

#Read the verilog


read_verilog abc_top.[Link]
read_verilog [Link]
read_verilog [Link]

set_current_design acb
set_design_level top_block
read_config_data occ.dft_spec
process_dft_specification
run_synthesis
set_current_design
write_design -output_file abc_core_post_occ_insertion.[Link] -replace
exit

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