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Digital Logic Design Quiz Solutions

This document contains 3 problems related to finite state machines (FSM): 1. Draw the state diagram of an FSM with 3 states (S1, S2, S3) and inputs a and b based on its VHDL description. 2. Complete the timing diagram of an FSM with 3 states (S1, S2, S3) and outputs sclr, z, E based on its ASM representation. 3. Draw the state diagram of a sequence detector FSM that asserts output z=1 when the input sequence 1011 is detected and then looks for a new sequence.

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MARCO ANTONIO CALIZAYA MARTINEZ
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39 views2 pages

Digital Logic Design Quiz Solutions

This document contains 3 problems related to finite state machines (FSM): 1. Draw the state diagram of an FSM with 3 states (S1, S2, S3) and inputs a and b based on its VHDL description. 2. Complete the timing diagram of an FSM with 3 states (S1, S2, S3) and outputs sclr, z, E based on its ASM representation. 3. Draw the state diagram of a sequence detector FSM that asserts output z=1 when the input sequence 1011 is detected and then looks for a new sequence.

Uploaded by

MARCO ANTONIO CALIZAYA MARTINEZ
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY

ECE-2700: Digital Logic Design Winter 2019

Solutions - Quiz 4
(April 2nd @ 5:30 pm)

PROBLEM 1 (30 PTS)


▪ Draw the state diagram (in ASM form) of the FSM whose VHDL description is listed below:
library ieee; architecture behavioral of circ is
use ieee.std_logic_1164.all; type state is (S1, S2, S3);
signal y: state;
entity circ is begin
port ( clk, rstn: in std_logic; Transitions: process (rstn, clk, a, b)
a, b: in std_logic; begin
x,w,z: out std_logic); if rstn = '0' then y <= S1;
end circ; elsif (clk'event and clk = '1') then
case y is
when S1 =>
rstn=0 if a = '1' then y <= S2;
S1 else if b = '1' then y <= S3; else y <= S1; end if;
end if;

when S2 =>
a 0
z1 b 0 if b = '1' then y <= S2; else y <= S1; end if;

1 1 when S3 =>
if b = '1' then y <= S3; else y <= S1; end if;
S2 S3 end case;
x1 end if;
end process;

0 1 1
w1 Outputs: process (y,a)
b a
begin
0 x <= ‘0’; w <= ‘0’; z <= ‘0’;
case y is
when S1 => if a = ‘0’ then z <= ‘1’; end if;
0 1 when S2 => x <= ‘1’;
b when S3 => if a = ‘1’ then w <= '1'; end if;
end case;
end process;
end behavioral;

PROBLEM 2 (40 PTS)


▪ Complete the timing diagram of the following FSM (represented in ASM form):

resetn=0
S1
sclr  1 clock

0 resetn
s
1 s
S2
z

z
0
E1 sclr

1
E
sclr  1

S3 state S1 S1 S1 S2 S2 S2 S3 S1 S1 S2 S2 S3 S3 S1

done
0 1
done  1 s

1 Instructor: Daniel Llamocca


ELECTRICAL AND COMPUTER ENGINEERING DEPARTMENT, OAKLAND UNIVERSITY
ECE-2700: Digital Logic Design Winter 2019

PROBLEM 3 (30 PTS)


▪ Sequence detector: Draw the state diagram (any representation) of an FSM with input 𝑥 and output 𝑧. The detector asserts
𝑧 = 1 when the sequence 1011 is detected. Right after the sequence is detected, the circuit looks for a new sequence.

resetn=0
S1

0
x
1
S2

1
x
0
S3

0
x
1
S4

0 1
x z1

2 Instructor: Daniel Llamocca

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