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Advanced Computer Architecture Analysis

This document summarizes the configuration and performance of memory for two computer processors, an Intel i7 and Intel i5. It provides details on the memory configuration including cache size and CPU specifications. It then analyzes the results of a memory performance benchmark run on both processors. Graphs of the results show the i7 generally outperforming the i5. The document also includes code snippets from the benchmark and explanations of what the code is doing. A t-test is performed and shows a statistically significant performance difference between the two processors.

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8 views13 pages

Advanced Computer Architecture Analysis

This document summarizes the configuration and performance of memory for two computer processors, an Intel i7 and Intel i5. It provides details on the memory configuration including cache size and CPU specifications. It then analyzes the results of a memory performance benchmark run on both processors. Graphs of the results show the i7 generally outperforming the i5. The document also includes code snippets from the benchmark and explanations of what the code is doing. A t-test is performed and shows a statistically significant performance difference between the two processors.

Uploaded by

Aounaiza Ahmed
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

Advanced Computer Architecture

Sabina Akram 18I-1424@[Link]

September 24, 2019

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• Configuration of machines

1.1 Memory

(kB) i7 i5

MemTotal 2044783 228745

MemFree 772084 188464

MemAvailable 842952 476280

Bu ers 18956 2016

Cached 200716 227712

SwapCached 2520 92284

L1 cache 32 32

L2 cache 256 256

L3 cache 6025 3022

2
1.2 CPU

i7 i5

Processor 0 0

vendor d Intel Intel

cpu family 6 6

model 60 61

model name Intel(R) Core(TM) Intel(R) Core(TM)


i7-4700MQ CPU @ i5-5200U CPU @ 2.20GHz
2.40GHz

stepping 3 4

cpu MHz 2394.464 2194.920

cache size 6144 KB 3072 KB

cache alignment 64 64

• Memory Performance Program Raw Data

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2.1 i7 output

Clock frequency is approx. 2394.6 MHz

Memory Performance (MB/sec)

4
i181237@[Link] Saima Ahmed

2.1.1 i5 output

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2.2 3 D Graphs Of Memory Performance

2.2.1 i7

Figure 1: i7

.2 15

Figure 2: i5

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2.3 Explanation of Raw data and graphs associated with it

The conclusions that can be drawn are as follows:

1. The performance of i7 is better overall than i5, at all block sizes and strides.L1 cache
tends to be used with lower dimensions and steps, and when the steps are enhanced,
the efficiency degrades and then rebounds at 16 step As the steps get smaller, the L2
memory is used, then the RAM is shown to be lower.3. The efficiency at 1 step is very
nice at larger measurements, but it degrades rapidly before rising at 10 and then 16
steps. Memory works better if 1 step with a large block volume is produced.

2.

3. 4. 3 separate highs at step 16, 8 and 1 can be seen.

2.4 code questions

2.4.1 Q1

Explain how the next line computes the throughput. Speci cally, give
the units of each of the variables (size, stride, cycles, Mhz) and what
are the units of the resulting value.

Ans:It computes throughput in Megabytes per second.

According to code

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(size / stride) / (cycles / Mhz);=(bytes/number)/(cycle/(cycle/106 =sec))
= megabytes=sec

2.4.2 Q2

What is the size of this sorted array and how does this code keep the
array named "values" sorted by identifying which sorting algorithm is
(implicitly) used?

vAnswer: As information type is double and occurrence numbers are 3, 3 ∗ 16=48


frames are the ordered set and are used to handle Bubble sort.

2.5 Q3

Explain what this code is doing. What is the \ asm" directive? What
is the meaning of rdtscp? What values end up in the hi and lo variables
after running this code?

Ans: Asm Directive allows for assembler orders to execute a 64-bit


time-stamp counter(TSC) on some [Link] and restore a non-signed
integer number A 64-bit. The hi vector is 32 times greater and 32 digit
smaller to finish the 64 digit integrator from the respective edx and eax
records.

.6 Code Modi cation and Box Plot

2.6.1 BoxPlot

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Figure 3: i7

Figure 4: i5

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2.6.2 Explanation

We use the same algorithm, but we only alter the path to 16 and collect ten samples. This
means that each block size at step 16 has an general variance and output.

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2.7 T-result

t-Test: Two-Sample Assuming Unequal Variances

Variable 1 Varliable 2

Mean 4568.32 6472.25

continued on next page

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continued from previous page
Variance 342982.9107 36709.07833

Observations 10 10

Hypothesized 0
Mean Di erence

df 11

t Stat -9.770915556

P(T<=t) on-tail 0.0000004657461214

t Critical one-tail 1.795884819

P(T<=t) two-tail 0.0000009314922429

t Critical two-tail 2.20098516

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