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Computer Logic Design: ALU & Multipliers

Three systems perform the same process and their outputs are sent to a majority gate to produce a single output. If two or more systems produce the same output, that output is chosen; otherwise an error is flagged. An arithmetic-logic unit performs both logic and arithmetic operations on 8-bit inputs a and b based on a 4-bit selection value. A 4-bit multiplier circuit multiplies positive numbers by implementing an array multiplier with partial product generation and addition.

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6 views2 pages

Computer Logic Design: ALU & Multipliers

Three systems perform the same process and their outputs are sent to a majority gate to produce a single output. If two or more systems produce the same output, that output is chosen; otherwise an error is flagged. An arithmetic-logic unit performs both logic and arithmetic operations on 8-bit inputs a and b based on a 4-bit selection value. A 4-bit multiplier circuit multiplies positive numbers by implementing an array multiplier with partial product generation and addition.

Uploaded by

bryan challco coronel
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd

DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO

ECE-238L: Computer Logic Design Fall 2013

Notes - Chapter 4
TRIPLE MODULE REDUNDANCY: MAJORITY GATE
 Three systems perform the same
identical process (the input data is also N System N
identical for the three systems). The replica 1
three outputs go into a majority-voting
system (called ‘majority gate’) to produce N N N
a single output. System Majority
 If at least two systems produce identical replica 2 gate
outputs, then the majority gate will pick
y_error
that output. If the three system produce
N System N
different results, the majority gate will
assert an error flag (y_error = ‘1’). replica 3

ARITHMETIC-LOGIC UNIT (ALU) a 8


ARITHMETIC
 This circuit carries out two types of 8 UNIT
operations: logic (or bit-wise) and b
arithmetic. 0
8 y
1
 In this example, the inputs a[7..0] and
b[7..0] are 8-bits wide. The numbers'
representation is 2's complement. LOGIC UNIT
sel(3)

4
sel

 The output is selected via the input sel[3..0] in the following manner:

sel Operation Function Unit


0000 y <= a Transfer ‘a’
0001 y <= a + 1 Increment ‘a’
0010 y <= a - 1 Decrement ‘a’
0011 y <= b Transfer ‘b’
0100 y <= b + 1 Increment ‘b’ Arithmetic
0101 y <= b – 1 Decrement ‘b’
0110 y <= a + b Add ‘a’ and ‘b’
0111 y <= a – b Subtract ‘b’ from 'a'
1000 y <= not a Complement ‘a’
1001 y <= not b Complement ‘b’
1010 y <= a AND b AND
1011 y <= a OR b OR
1100 y <= a NAND b NAND Logic
1101 y <= a NOR b NOR
1110 y <= a XOR b XOR
1111 y <= a XNOR b XNOR

Instructor: Daniel Llamocca


DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING, THE UNIVERSITY OF NEW MEXICO
ECE-238L: Computer Logic Design Fall 2013

MULTIPLIER CIRCUIT (POSITIVE NUMBERS)


Multiplication of Positive Numbers (4-bit case):
a3 a2 a1 a0 x
cin b3 b2 b1 b0
x y
a3b 0 a2b0 a 1b0 a0b 0
FULL
ADDER a 3b1 a2b 1 a1b1 a 0b1
a3b2 a 2b2 a1b 2 a0b2
s a3b3 a2b3 a 1b3 a0b 3
cout
p7 p6 p5 p4 p3 p2 p1 p0
Array Multiplier:
b(3) b(2) b(1) b(0)

a(0)
a0b3 a0b2 a0b1 a0b0

m03 m02 m01 m00

s03 s02 s01 s00

c02 c01 c00


a(1)
a1b3 a1b2 a1b1 a1b0
m13 m12 m11 m10 p(0)

s13 s12 s11 s10


c12 c11 c10

a(2)
a2b3 a2b2 a2b1 a2b0
m23 m22 m21 m20 p(1)

s23 s22 s21 s20


c22 c21 c20

a(3)
a3b3 a3b2 a3b1 a3b0
m33 m32 m31 m30 p(2)

s33 s32 s31 s30


c32 c31 c30

m43 m42 m41 m40


p(3)

p(7) p(6) p(5) p(4)

Instructor: Daniel Llamocca

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