application UCC15701/2

INFO UCC25701/2
available
UCC35701/2
Advanced Voltage Mode Pulse Width Modulator
FEATURES DESCRIPTION
700kHz Operation The UCC35701/UCC35702 family of pulse width modulators is intended for
isolated switching power supplies using primary side control. They can be
Integrated Oscillator/ Voltage Feed
used for both off-line applications and DC/DC converter designs such as in
Forward Compensation
a distributed power system architecture or as a telecom power source.
Accurate Duty Cycle Limit
The devices feature low startup current, allowing for efficient off-line start-
Accurate Volt-second Clamp ing, yet have sufficient output drive to switch power MOSFETs in excess of
500kHz.
Optocoupler Interface
Voltage feed forward compensation is operational over a 5:1 input range
Fault Counting Shutdown and provides fast and accurate response to input voltage changes over a
Fault Latch off or Automatic Shutdown 4:1 range. An accurate volt-second clamp and maximum duty cycle limit
are also featured.
Soft Stop Optimized for Synchronous
Rectification Fault protection is provided by pulse by pulse current limiting as well as the
ability to latch off after a programmable number of repetitive faults has oc-
1A Peak Gate Drive Output curred.
130mA Start-up Current Two UVLO options are offered. UCC35701 family has turn-on and turn-off
thresholds of 13V/9V and UCC35702 family has thresholds of 9.6V/8.8V.
750mA Operating Current
The UCC35701/2 and the UCC25701/2 are offered in the 14 pin SOIC (D),
14 pin PDIP (N) or in 14 pin TSSOP (PW) packages. The UCC15701/2 is
offered in the 14 pin CDIP (J) package.
TYPICAL APPLICATION DIAGRAM
VIN S UP P LY

R1 R6
R2 VFF R7
6 VDD 3
R3
7 RT
VREF CT UCC35701
C6 VOUT
10 CT
R4 C1 C4

9 VS CLAMP
R8
R5 OUT 4
11 S YNC
CS R10
14 SS ILIM 2
C2
CF
RCS
1 COUNT
C3
RF 12 VREF P GND 5

R8 RGND VIN RETURN

8 FB GND 13

R11
VOUT
C5
R13
R12 C6
R14

C7
R15

UDG-98005-1

SLUS293C - JANUARY 2000 - REVISED JUNE 2005

 UCC15701/2
UCC25701/2
UCC35701/2
ABSOLUTE MAXIMUM RATINGS ORDERING INFORMATION
Supply voltage (Supply current limited to 20mA) . . . . . . . . 15V TA = TJ UVLO Package Part Number
Supply Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20mA Option
Input pins ( ILIM,VFF,RT,CT,VSCLAMP,SYNC,SS, FB) . . . 6V 13V / 9V CDIP-14 UCC15701J
Output Current (OUT) DC. . . . . . . . . . . . . . . . . . . . . +/–180mA –55°C to +125°C
9.6V / 8.8V CDIP-14 UCC15702J
Output Current (OUT) Pulse (0.5ms) . . . . . . . . . . . . . . +/–1.2A SOIC-14 UCC25701D
Storage Temperature. . . . . . . . . . . . . . . . . . . –65°C to +150°C 13V / 9V PDIP-14 UCC25701N
Junction Temperature . . . . . . . . . . . . . . . . . . . –55°C to +150°C TSSOP-14 UCC25701PW
Lead Temperature (Soldering, 10 sec.) . . . . . . . . . . . . +300°C –40°C to +85°C
SOIC-14 UCC25702D
Note: All voltages are with respect to GND. Currents are posi- 9.6V / 8.8V PDIP-14 UCC25702N
tive into the specified terminal. Consult Packaging Section of TSSOP-14 UCC25702PW
the Databook for thermal limitations and considerations of SOIC-14 UCC35701D
packages. 13V / 9V PDIP-14 UCC35701N
TSSOP-14 UCC35701PW
0°C to +70°C
CONNECTION DIAGRAMS SOIC-14 UCC35702D
9.6V / 8.8V PDIP-14 UCC35702N
DIL-14, SOIC-14, TSSOP-14 (TOP VIEW) TSSOP-14 UCC35702PW
N or J, D, PW PACKAGE The D and PW packages are available taped and reeled. Add
TR suffix to the device type (e.g., UCC35701DTR).
COUNT 1 14 SS

ILIM 2 13 GND

VDD 3 12 VREF

OUT 4 11 S YNC

P GND 5 10 CT

VFF 6 9 VS CLAMP

RT 7 8 FB

ELECTRICAL CHARACTERISTICS:Unless otherwise specified, VDD = 11V, RT = 60.4k, CT = 330pF, CREF = CVDD =
0.1m F, VFF = 2.0V, and no load on the outputs.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
UVLO Section
Start Threshold (UCCX5701) 12 13 14 V
(UCCX5702) 8.8 9.6 10.4 V
Stop Threshold (UCCX5701) 8 9 10 V
(UCCX5702) 8.0 8.8 9.6 V
Hysteresis (UCCX5701) 3 4 V
(UCCX5702) 0.3 0.8 V
Supply Current
Start-up Current (UCCX5701) VDD = 11V, VDD Comparator Off 130 200 mA
(UCCX5702) VDD = 8V, VDD Comparator Off 120 190 mA
IDD Active VDD Comparator On 0.75 1.5 mA
VDD Clamp Voltage (UCCX5701) IDD = 10mA 13.5 14.3 15 V
(UCCX5702) IDD = 10mA 13 13.8 15 V
VDD Clamp – Start Threshold (UCCX5701) 1.3 V
(UCCX5702) 4.2 V
Voltage Reference
VREF VDD = 10V to 13V, IVREF = 0mA to 2mA 4.9 5 5.1 V
Line Regulation VDD = 10V to 13V 20 mV
Load Regulation IVREF = 0mA to 2mA 2 mV
Short Circuit Current VREF = 0V, TJ = 25°C 20 50 mA

2
 UCC15701/2
UCC25701/2
UCC35701/2
ELECTRICAL CHARACTERISTICS:Unless otherwise specified, VDD = 11V, RT = 60.4k, CT = 330pF, CREF = CVDD =
0.1m F, VFF = 2.0V, and no load on the outputs.
PARAMETER TEST CONDITIONS MIN TYP MAX UNITS
Line Sense
Vth High Line Comparator 3.9 4 4.1 V
Vth Low Line Comparator 0.5 0.6 0.7 V
Input Bias Current –100 100 nA
Oscillator Section
Frequency VFF = 0.8V to 3.2V 90 100 110 kHz
Frequency VFF = 0.6V to 3.4V (Note 1) 90 100 110 kHz
SYNC VIH 2 V
SYNC VIL 0.8 V
SYNC Input Current VSYNC = 2.0V 3 10 mA
RT Voltage VFF = 0.4V 0.5 0.6 0.7 V
VFF = 0.8V 0.75 0.8 0.85 V
VFF = 2.0V 1.95 2.0 2.05 V
VFF = 3.2V 3.15 3.2 3.25 V
VFF = 3.6V 3.3 3.4 3.5 V
CT Peak Voltage VFF = 0.8V (Note 1) 0.8 V
VFF = 3.2V (Note 1) 3.2 V
CT Valley Voltage (Note 1) 0 V
Soft Start/Shutdown/Duty Cycle Control Section
ISS Charging Current 10 18 30 mA
ISS Discharging Current 300 500 750 mA
Saturation VDD = 11V, IC Off 25 100 mV
Fault Counter Section
Threshold Voltage VFF = 0.8V to 3.2V 3.8 4 4.2 V
Saturation Voltage VFF = 0.8V to 3.2V 100 mV
Count Charging Current 10 18 30 mA
Current Limit Section
Input Bias Current –100 0 100 nA
Current Limit Threshold 180 200 220 mV
Shutdown Threshold 500 600 700 mV
Pulse Width Modulator Section
FB Pin Input Impedance VFB = 3V 30 50 100 kW
Minimum Duty Cycle VFB <= 1V 0 %
Maximum Duty Cycle VFB >= 4.5V, VSCLAMP >= 2.0V 95 99 100 %
PWM Gain VFF = 0.8V 35 50 70 %/V
Volt Second Clamp Section
Maximum Duty Cycle VFF = 0.8V, VSCLAMP = 0.6V 69 74 79 %
Minimum Duty Cycle VFF = 3.2V, VSCLAMP = 0.6V 17 19 21 %
Output Section
VOH IOUT = –100mA, (VDD – VOUT) 0.4 1 V
VOL IOUT = 100mA 0.4 1 V
Rise Time CLOAD = 1000pF 20 100 ns
Fall Time CLOAD = 1000pF 20 100 ns
Note 1: Ensured by design. Not 100% tested in production.

3
 UCC15701/2
UCC25701/2
UCC35701/2
DETAILED BLOCK DIAGRAM

2*IRT

S 11 S YNC
VFF 6
3m A
Q RD

RT 7 P EAK
IRT 3 VDD
CT 10
P WM

0.7V 0.2V
VALLEY S Q 4 OUT
+

FB 8
RD
1.5R R
5 P GND

VS CLAMP 9
4V
HIGH LINE
VREF RUN 13/9V (35701)
LOW LINE 9.6/8.8V (35702)
I
0.6V
4.5V
SS 14
S S DONE
25*I
0.6V CURRENT FAULT

R Q
ILIM 2 CURRENT LIMIT 0.2V VDD
VREF SD
0.2V
I FAULT
D Q
R Q LATCH
P WM 5.0V
12 VREF
S S DONE R REF
SD
COUNT 1 4V
13 GND

S HUTDOWN
LATCH

UDG-98004

PIN DESCRIPTIONS
VDD: Power supply pin. A shunt regulator limits supply RT: The voltage on this pin mirrors VFF over a 0.8V to
voltage to 14V typical at 10mA shunt current. 3.2V range. A resistor to ground sets the ramp capacitor
PGND: Power Ground. Ground return for output driver charge current. The resistor value should be between
and currents. 20k and 200k.

GND: Analog Ground. Ground return for all other circuits. CT: A capacitor to ground provides the oscillator/
This pin must be connected directly to PGND on the feedforward sawtooth waveform. Charge current is 2 ·
board. IRT, resulting in a CT slope proportional to the input volt-
age. The ramp voltage range is GND to VRT.
OUT: Gate drive output. Output resistance is 10W maxi-
Period and oscillator frequency is given by:
mum.
VR T · CT
VFF: Voltage feedforward pin. This pin connects to the T= + t DIS CH » 0 . 5 · RT · CT
2 · IR T
power supply input voltage through a resistive divider
and provides feedforward compensation over a 0.8V to 2
F»
3.2V range. A voltage greater than 4.0V or less than R T · CT
0.6V on this pin initiates a soft stop cycle.

4
 UCC15701/2
UCC25701/2
UCC35701/2
PIN DESCRIPTIONS (cont.)
VSCLAMP: Voltage at this pin is compared to the CT source. While the soft start capacitor is charging, and
voltage, providing a constant volt-second limit. The com- while VSS < (0.4 VFB), the duty cycle, and therefore the
parator output terminates the PWM pulse when the ramp output voltage of the converter is determined by the soft
voltage exceeds VSCLAMP. The maximum on time is start circuitry.
given by:
At High Line or Low Line fault conditions, the soft start
V · CT
t ON = VS CLAMP capacitor is discharged with a controlled discharge cur-
2 · IR T rent of about 500mA. During the discharge time, the duty
cycle of the converter is gradually decreased to zero.
The maximum duty cycle limit is given by:
This soft stop feature allows the synchronous rectifiers to
t ON VVS CLAMP gradually discharge the output LC filter. An abrupt shut
DMAX = =
T VR T off can cause the LC filter to oscillate, producing unpre-
dictable output voltage levels.
FB: Input to the PWM comparator. This pin is intended
to be driven with an optocoupler circuit. Input impedance All other fault conditions (UVLO, VREF Low, Over Cur-
is 50kW Typical modulation range is 1.6V to 3.6V. rent (0.6V on ILIM) or COUNT) will cause an immediate
stop of the converter. Furthermore, both the Over Current
SYNC: Level sensitive oscillator sync input. A high level fault and the COUNT fault will be internally latched until
forces the gate drive output low and resets the ramp ca- VDD drops below 9V or VFF goes below the 600mV
pacitor. On-time starts at the negative edge the pulse. threshold at the input of the Low Line comparator.
There is a 3mA pull down current on the pin, allowing it to
be disconnected when not used. After all fault conditions are cleared and the soft start ca-
pacitor is discharged below 200 mV, a soft start cycle will
VREF: 5.0V trimmed reference with 2% variation over be initiated to restart the converter.
line, load and temperature. Bypass with a minimum of
0.1mF to ground. ILIM: Provides a pulse by pulse current limit by terminat-
ing the PWM pulse when the input is above 200mV. An
SS: Soft Start pin. A capacitor is connected between this input over 600mV initiates a latched soft stop cycle.
pin and ground to set the start up time of the converter.
After power up (VDD>13V AND VREF>4.5V), or after a COUNT: Capacitor to ground integrates current pulses
fault condition has been cleared, the soft start capacitor generated when ILIM exceeds 200mV. A resistor to
is charged to VREF by a nominal 18mA internal current ground sets the discharge time constant. A voltage over
4V will initiate a latched soft stop cycle.

APPLICATION INFORMATION
(Note: Refer to the Typical Application Diagram on the first The circuit will start at this point. IVDD will increase from
page of this datasheet for external component names.) All the the start up value of 130mA to the run value of 750mA.
equations given below should be considered as first order ap- The capacitor on SS is charged with a 18mA current.
proximations with final values determined empirically for a spe-
When the voltage on SS is greater than 0.8V, output
cific application.
pulses can begin, and supply current will increase to a
Power Sequencing level determined by the MOSFET gate charge require-
VDD is normally connected through a high impedance ments to IVDD ~ 1mA + QT · fs. When the output is ac-
(R6) to the input line, with an additional path (R7) to a tive, the bootstrap winding should be sourcing the supply
low voltage bootstrap winding on the power transformer. current. If VDD falls below the UVLO stop threshold, the
VFF is connected through a divider (R1/R2) to the input controller will enter a shutdown sequence and turn the
line. controller off, returning the start sequence to the initial
condition.
For circuit activation, all of the following conditions are
required: VDD Clamp
1. VFF between 0.6V and 4.0V (operational input voltage An internal shunt regulator clamps VDD so the voltage
range). does not exceed a nominal value of 14V. If the regulator
is active, supply current must be limited to less than
2. VDD has been under the UVLO stop threshold to reset 20mA.
the shutdown latch.
3. VDD is over the UVLO start threshold.
5
 UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
Output Inhibit VFF is intended to operate accurately over a 4:1 range
During normal operation, OUT is driven high at the start between 0.8V and 3.2V. Voltages at VFF below 0.6V or
of a clock period and is driven low by voltages on CT, FB above 4.0V will initiate a soft stop cycle and a chip restart
or VSCLAMP. when the under/over voltage condition is removed.

The following conditions cause the output to be immedi- Volt-Second Clamp

ately driven low until a clock period starts where none of A constant volt-second clamp is formed by comparing the
the conditions are true: timing capacitor ramp voltage to a fixed voltage derived
1. ILIM > 0.2V from the reference. Resistors R4 and R5 set the
volt-second limit. For a volt-second product defined as
2. FB or SS is less than 0.8V VIN tON(max), the required voltage at VSCLAMP is:
Current Limiting æ R2 ö
ILIM is monitored by two internal comparators. The cur-
ç ( )
÷ · VIN · t ON (ma x)
èR1 + R 2 ø
.
rent limit comparator threshold is 0.2V. If the current limit RT · CT
comparator is triggered, OUT is immediately driven low
and held low for the remainder of the clock cycle, provid- The duty cycle limit is then:
ing pulse-by-pulse over-current control for excessive VVS CLAMP VVS CLAMP
, or .
loads. This comparator also causes CF to be charged for VVFF æ R2 ö
the remainder of the clock cycle. VIN · ç ÷
èR1 + R 2 ø
If repetitive cycles are terminated by the current limit
The maximum duty cycle is realized when the
comparator causing COUNT to rise above 4V, the shut-
feedforward voltage is set at the low end of the operating
down latch is set. The COUNT integration delay feature
range (VFF = 0.8V).
will be bypassed by the shutdown comparator which has
a 0.6V threshold. The shutdown comparator immediately The absolute maximum duty cycle is:
sets the shutdown latch. RF in parallel with CF resets the VVS CLAMP VR EF R5
COUNT integrator following transient faults. RF must be DMAX = = ·
0.8 0.8 R 4 + R 5
greater than (4 · R4) · (1 – DMAX).
Frequency Set
Latched Shutdown
The frequency is set by a resistor from RT to ground and
If ILIM rises above 0.6V, or COUNT rises to 4V, the shut-
a capacitor from CT to ground. The frequency is approxi-
down latch will be set. This will force OUT low, discharge
2
SS and COUNT, and reduce IDD to approximately mately: F =
(RT · CT )
750mA. When, and if, VDD falls below the UVLO stop
threshold, the shutdown latch will reset and IDD will fall External synchronization is via the SYNC pin. The pin
to 130mA, allowing the circuit to restart. If VDD remains has a 1.5V threshold , making it compatible with 5V and
above the UVLO stop threshold (within the UVLO band), 3.3V CMOS logic. The input is level sensitive, with a high
an alternate restart will occur if VFF is momentarily re- input forcing the oscillator ramp low and the output low.
duced below 1V. External shutdown commands from any An active pull down on the SYNC pin allows it to be un-
source may be added into either the COUNT or ILIM connected when not used.
pins.
Gate Drive Output
Voltage Feedforward
The UCC35701/2 is capable of a 1A peak output current.
The voltage slope on CT is proportional to line voltage Bypass with at least 0.1mF directly to PGND. The capac-
over a 4:1 range and equals 2·VFF (RT·CT). The capac- itor must have a low equivalent series resistance and in-
itor charging current is set by the voltage across RT. ductance. The connection from OUT to the power
V(RT) tracks VFF over a range of 0.8V to 3.2V. A chang- MOSFET gate should have a 2W or greater damping re-
ing line voltage will immediately change the slope of sistor and the distance between chip and MOSFET
V(CT), changing the pulse width in a proportional manner should be minimized. A low impedance path must be es-
without using the feedback loop, providing excellent dy- tablished between the MOSFET source (or ground side
namic line regulation. of the current sense resistor), the VDD capacitor and
PGND. PGND should then be connected by a single path
(shown as RGND) to GND.

6
 UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
Transitioning From UCC3570 To UCC35701 UCC35701/2 is pin to pin compatible to UCC3570 but is
The UCC35701/2 is an advanced version of the popular, not a direct drop-in replacement for UCC3570 sockets.
low power UCC3570 PWM. Significant improvements The changes required to the power supply printed circuit
were made to the IC’s oscillator and PWM control sec- board of for existing UCC3570 designs are minimal. For
tions to enhance overall system performance. All of the conversion, only one extra resistor to set the volt-second
key attributes and functional blocks of the UCC3570 clamp needs to be added to the existing PC board lay-
were maintained in the UCC35701/2. A typical applica- outs. In addition, some component values will need to
tion using UCC3570 and UCC35701/2 is shown in Fig. 6 be changed due to the functionality change in of four of
for comparison. the IC pins.

The advantages of the UCC35701/2 over the UCC3570 The Pinout Changes from UCC3570 are as follows.
are as follows. Pin 7 was changed from SLOPE to RT (for timing
resistor)
Improved oscillator and PWM control section.
Pin 8 was changed from ISET to VSCLAMP (requiring
A precise maximum volt-second clamp circuit. The
one additional resistor from pin 9 to VREF)
UCC3570 has a dual time base between oscillator and
feedforward circuitry. The integated time base in Pin 10 was changed from RAMP to CT (single timing
UCC35701/2 improves the duty cycle clamp accuracy, capacitor)
providing better than ± 5% accurate volt- second
clamp over full temperature range. Pin 11 was changed from FREQ to SYNC (input only)
Additional Information
Separately programmable oscillator timing resistor
(RT) and capacitor (CT) circuits provide a higher Please refer to the following two Unitrode application
degree of versatility. topics on UCC3570 for additional information.
An independent SYNC input pin for simple external [1] Application Note U-150, Applying the UCC3570 Volt-
synchronization. age-Mode PWM Controller to Both Off-line and DC/DC
Converter Designs by Robert A. Mammano
A smaller value filter capacitor (0.1mF) can be used
with the enhanced reference voltage. [2] Design Note DN-62, Switching Power Supply Topol-
ogy, Voltage Mode vs. Current Mode by Robert
Mammano

TYPICAL WAVEFORMS

FEEDBK

VS CLAMP

CT

S OFTS T

S OFT S TART HIGH DC LOW DC ZERO DC S OFT S TOP

V-S CLAMP UDG-98207

Figure 1. Timing diagram for PWM action with forward, soft start and volt-second clamp.

7
 UCC15701/2
UCC25701/2
UCC35701/2
TYPICAL WAVEFORMS (cont.)

VFF

CT

S YNC

UDG-98208

Figure 2. Timing diagram for oscillator waveforms showing feedforward action and synchronization.

TYPICAL CHARACTERISTIC CURVES

1000 1.03
VFF=3.2
1.02
NORMALIZED DUTY CYCLE
FREQUENCY [kHz]

1.01
VFF=0.8
100 100pF 1.00
150pF
220pF 0.99
330pF
470pF 0.98

10 0.97
20 60 100 140 180 220 -55 -35 -15 5 25 45 65 85 105 125
RT [K ] TEMPERATURE [°C]

Figure 3. Oscillator frequency vs. RT and CT. Figure 5. Normalized maximum duty cycle vs.
temperature.

1.02
CT=330pF
FOSC = 100kHz
NORMALIZED FREQUENCY

1.01
VFF=0.8

0.99
VFF=3.2

0.98
-55 -35 -15 5 25 45 65 85 105 125
TEMPERATURE [°C]

Figure 4. Oscillator frequency vs. temperature.

8
 UCC15701/2
UCC25701/2
UCC35701/2
APPLICATION INFORMATION (cont.)
VIN+

R1 R5
R2 UCC3570 R6
6 VFF VDD 3
VOUT
R3
C4
7 S LOP E
C1
CR R8
10 RAMP OUT 4

R4 R9
9 IS ET ILIM 2

CT
C2
11 FREQ
RT R S NS

CS S
14 SS P GND 5

CF
1 COUNT
RF
R GND
C3
12 VREF

R7 GND 13
8 FB

R11
VOUT
C5
R13
R12 C6
R14

C7
R15

VIN+

R1 UCC35701 R5
R2 R6
6 VFF VDD 3
VOUT
R3
C4
7 RT
C1
CT R8
10 CT OUT 4

R4 R9
9 VS CLAMP ILIM 2

C2
R NEW
11 S YNC R S NS

CS S
14 S S P GND 5

CF
1 COUNT
RF
R GND
C3
12 VREF

R7 GND 13
8 FB

R11
VOUT
C5
R13
R12 C6
R14

C7
R15

UDG-98210

Figure 6. Single-ended forward circuit comparison between UCC3570 and UCC37501.

9
 UCC15701/2
UCC25701/2
UCC35701/2

REVISION HISTORY
DATE REVISION REASON
02/16/05 SLUS293B Add FB to abs max table. Created revision history table.
6/16/05 SLUS293C Updated block diagram and the SS pin description.

10
 PACKAGE OPTION ADDENDUM

[Link] 24-Jan-2013

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Qty Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing (2) (3) (4)

UCC15701J OBSOLETE CDIP J 14 TBD Call TI Call TI -55 to 125

UCC15701L OBSOLETE LCCC FK 20 TBD Call TI Call TI -55 to 125
UCC25701D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25701D
& no Sb/Br)
UCC25701DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25701D
& no Sb/Br)
UCC25701DTR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25701D
& no Sb/Br)
UCC25701DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25701D
& no Sb/Br)
UCC25701N ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UCC25701N
& no Sb/Br)
UCC25701NG4 ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UCC25701N
& no Sb/Br)
UCC25701PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25701
& no Sb/Br)
UCC25701PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25701
& no Sb/Br)
UCC25701PWTR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25701
& no Sb/Br)
UCC25701PWTRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25701
& no Sb/Br)
UCC25702D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25702D
& no Sb/Br)
UCC25702DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25702D
& no Sb/Br)
UCC25702DTR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25702D
& no Sb/Br)
UCC25702DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 UCC25702D
& no Sb/Br)
UCC25702N ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UCC25702N
& no Sb/Br)
UCC25702NG4 ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 UCC25702N
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 24-Jan-2013

Orderable Device Status Package Type Package Pins Package Qty Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing (2) (3) (4)

UCC25702PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25702
& no Sb/Br)
UCC25702PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25702
& no Sb/Br)
UCC25702PWTR ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25702
& no Sb/Br)
UCC25702PWTRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR -40 to 85 25702
& no Sb/Br)
UCC35701D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UCC35701D
& no Sb/Br)
UCC35701DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UCC35701D
& no Sb/Br)
UCC35701DTR ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UCC35701D
& no Sb/Br)
UCC35701DTRG4 ACTIVE SOIC D 14 2500 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UCC35701D
& no Sb/Br)
UCC35701N ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UCC35701N
& no Sb/Br)
UCC35701NG4 ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UCC35701N
& no Sb/Br)
UCC35701PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 35701
& no Sb/Br)
UCC35701PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 35701
& no Sb/Br)
UCC35701Q OBSOLETE UTR 20 TBD Call TI Call TI 0 to 70
UCC35701QTR OBSOLETE UTR 20 TBD Call TI Call TI 0 to 70
UCC35702D ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UCC35702D
& no Sb/Br)
UCC35702DG4 ACTIVE SOIC D 14 50 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 UCC35702D
& no Sb/Br)
UCC35702N ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UCC35702N
& no Sb/Br)
UCC35702NG4 ACTIVE PDIP N 14 25 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 UCC35702N
& no Sb/Br)
UCC35702PW ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 35702
& no Sb/Br)

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

[Link] 24-Jan-2013

Orderable Device Status Package Type Package Pins Package Qty Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Top-Side Markings Samples
(1) Drawing (2) (3) (4)

UCC35702PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS CU NIPDAU Level-2-260C-1 YEAR 0 to 70 35702

& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check [Link] for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
Only one of markings shown within the brackets will appear on the physical device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF UCC15701, UCC35701 :

• Catalog: UCC35701
• Military: UCC15701

NOTE: Qualified Version Definitions:

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

[Link] 24-Jan-2013

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

[Link] 26-Jan-2013

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UCC25701DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UCC25701PWTR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
UCC25702DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
UCC25702PWTR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
UCC35701DTR SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 26-Jan-2013

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
UCC25701DTR SOIC D 14 2500 333.2 345.9 28.6
UCC25701PWTR TSSOP PW 14 2000 367.0 367.0 35.0
UCC25702DTR SOIC D 14 2500 333.2 345.9 28.6
UCC25702PWTR TSSOP PW 14 2000 367.0 367.0 35.0
UCC35701DTR SOIC D 14 2500 333.2 345.9 28.6

Pack Materials-Page 2
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