The combinational circuit does not use any memory.

Hence the previous state of input does not

have any effect on the present state of the circuit. But sequential circuit has memory so output
can vary based on input. This type of circuits uses previous input, output, clock and a memory
element.

Block diagram

Flip Flop
Flip flop is a sequential circuit which generally samples its inputs and changes its outputs only at
particular instants of time and not continuously. Flip flop is said to be edge sensitive or edge
triggered rather than being level triggered like latches.

S-R Flip Flop

It is basically S-R latch using NAND gates with an additional enable input. It is also called as
level triggered SR-FF. For this, circuit in output will take place if and only if the enable input (E)
is made active. In short this circuit will operate as an S-R latch if E = 1 but there is no change in
the output if E = 0.
Block Diagram

Circuit Diagram

Truth Table

Operation
S.N. Condition Operation

If S = R = 0 then output of NAND gates 3 and 4 are forced to

become 1.
1 S = R = 0 : No change
Hence R' and S' both will be equal to 1. Since S' and R' are the
input of the basic S-R latch using NAND gates, there will be no
change in the state of outputs.
2 S = 0, R = 1, E = 1
Since S = 0, output of NAND-3 i.e. R' = 1 and E = 1 the output
 of NAND-4 i.e. S' = 0.

Hence Qn+1 = 0 and Qn+1 bar = 1. This is reset condition.

Output of NAND-3 i.e. R' = 0 and output of NAND-4 i.e. S' = 1.
3 S = 1, R = 0, E = 1
Hence output of S-R NAND latch is Qn+1 = 1 and Qn+1 bar = 0.
This is the reset condition.
As S = 1, R = 1 and E = 1, the output of NAND gates 3 and 4
4 S = 1, R = 1, E = 1 both are 0 i.e. S' = R' = 0.

Hence the Race condition will occur in the basic NAND latch.

Master Slave JK Flip Flop

Master slave JK FF is a cascade of two S-R FF with feedback from the output of second to input
of first. Master is a positive level triggered. But due to the presence of the inverter in the clock
line, the slave will respond to the negative level. Hence when the clock = 1 (positive level) the
master is active and the slave is inactive. Whereas when clock = 0 (low level) the slave is active
and master is inactive.

Circuit Diagram

Truth Table
Operation
S.N. Condition Operation

When clock = 0, the slave becomes active and master is

1 J = K = 0 (No change) inactive. But since the S and R inputs have not changed, the
slave outputs will also remain unchanged. Therefore outputs
will not change if J = K =0.
Clock = 1 − Master active, slave inactive. Therefore outputs of
the master become Q1 = 0 and Q1 bar = 1. That means S = 0 and
R =1.

Clock = 0 − Slave active, master inactive. Therefore outputs of

the slave become Q = 0 and Q bar = 1.
2 J = 0 and K = 1 (Reset)
Again clock = 1 − Master active, slave inactive. Therefore even
with the changed outputs Q = 0 and Q bar = 1 fed back to
master, its output will be Q1 = 0 and Q1 bar = 1. That means S
= 0 and R = 1.

Hence with clock = 0 and slave becoming active the outputs of

slave will remain Q = 0 and Q bar = 1. Thus we get a stable
output from the Master slave.
Clock = 1 − Master active, slave inactive. Therefore outputs of
the master become Q1 = 1 and Q1 bar = 0. That means S = 1 and
R =0.
3 J = 1 and K = 0 (Set)
Clock = 0 − Slave active, master inactive. Therefore outputs of
the slave become Q = 1 and Q bar = 0.

Again clock = 1 − then it can be shown that the outputs of the

slave are stabilized to Q = 1 and Q bar = 0.
Clock = 1 − Master active, slave inactive. Outputs of master will
toggle. So S and R also will be inverted.

Clock = 0 − Slave active, master inactive. Outputs of slave will

toggle.
4 J = K = 1 (Toggle)
These changed output are returned back to the master inputs.
But since clock = 0, the master is still inactive. So it does not
respond to these changed outputs. This avoids the multiple
toggling which leads to the race around condition. The master
slave flip flop will avoid the race around condition.

Delay Flip Flop / D Flip Flop

Delay Flip Flop or D Flip Flop is the simple gated S-R latch with a NAND inverter connected
between S and R inputs. It has only one input. The input data is appearing at the output after
some time. Due to this data delay between i/p and o/p, it is called delay flip flop. S and R will be
the complements of each other due to NAND inverter. Hence S = R = 0 or S = R = 1, these input
condition will never appear. This problem is avoid by SR = 00 and SR = 1 conditions.

Block Diagram

Circuit Diagram

Truth Table

Operation
S.N. Condition Operation

1 E=0
Latch is disabled. Hence no change in output.
If E = 1 and D = 0 then S = 0 and R = 1. Hence irrespective of the
2 E = 1 and D = 0
present state, the next state is Qn+1 = 0 and Qn+1 bar = 1. This is the reset
condition.
3 E = 1 and D = 1 If E = 1 and D = 1, then S = 1 and R = 0. This will set the latch and Qn+1
= 1 and Qn+1 bar = 0 irrespective of the present state.

Toggle Flip Flop / T Flip Flop

Toggle flip flop is basically a JK flip flop with J and K terminals permanently connected
together. It has only input denoted by T as shown in the Symbol Diagram. The symbol for
positive edge triggered T flip flop is shown in the Block Diagram.

Symbol Diagram

Block Diagram

Truth Table

Operation
S.N. Condition Operation

1 T = 0, J = K = 0 The output Q and Q bar won't change

2 T = 1, J = K = 1 Output will toggle corresponding to every leading edge of clock signal.

Digital Circuits - Flip-Flops

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In previous chapter, we discussed about Latches. Those are the

basic building blocks of flip-flops. We can implement flip-flops
in two methods.
In first method, cascade two latches in such a way that the first
latch is enabled for every positive clock pulse and second latch
is enabled for every negative clock pulse. So that the
combination of these two latches become a flip-flop.
In second method, we can directly implement the flip-flop,
which is edge sensitive. In this chapter, let us discuss the
following flip-flops using second method.
• SR Flip-Flop
• D Flip-Flop
• JK Flip-Flop
• T Flip-Flop
SR Flip-Flop
SR flip-flop operates with only positive clock transitions or
negative clock transitions. Whereas, SR latch operates with
enable signal. The circuit diagram of SR flip-flop is shown in
the following figure.

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’.
The operation of SR flipflop is similar to SR Latch. But, this
flip-flop affects the outputs only when positive transition of the
clock signal is applied instead of active enable.
The following table shows the state table of SR flip-flop.

S R Q(t + 1)
0 0 Q(t)
0 1 0
1 0 1
1 1 -
Here, Q(t) & Q(t + 1) are present state & next state respectively.
So, SR flip-flop can be used for one of these three functions
such as Hold, Reset & Set based on the input conditions, when
positive transition of clock signal is applied. The following table
shows the characteristic table of SR flip-flop.

Present Inputs Present State Next State

S R Q(t) Q(t + 1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 x
1 1 1 x

By using three variable K-Map, we can get the simplified

expression for next state, Q(t + 1). The three variable K-Map
for next state, Q(t + 1) is shown in the following figure.
The maximum possible groupings of adjacent ones are already
shown in the figure. Therefore, the simplified expression for
next state Q(t + 1) is
Q(t+1)=S+R′Q(t)
D Flip-Flop
D flip-flop operates with only positive clock transitions or
negative clock transitions. Whereas, D latch operates with
enable signal. That means, the output of D flip-flop is insensitive
to the changes in the input, D except for active transition of the
clock signal. The circuit diagram of D flip-flop is shown in the
following figure.

This circuit has single input D and two outputs Q(t) & Q(t)’. The
operation of D flip-flop is similar to D Latch. But, this flip-flop
affects the outputs only when positive transition of the clock
signal is applied instead of active enable.
The following table shows the state table of D flip-flop.
 D Q(t + 1)
0 0
1 1

Therefore, D flip-flop always Hold the information, which is

available on data input, D of earlier positive transition of clock
signal. From the above state table, we can directly write the next
state equation as
Q(t + 1) = D
Next state of D flip-flop is always equal to data input, D for
every positive transition of the clock signal. Hence, D flip-flops
can be used in registers, shift registers and some of the
counters.
JK Flip-Flop
JK flip-flop is the modified version of SR flip-flop. It operates
with only positive clock transitions or negative clock transitions.
The circuit diagram of JK flip-flop is shown in the following
figure.

This circuit has two inputs J & K and two outputs Q(t) & Q(t)’.
The operation of JK flip-flop is similar to SR flip-flop. Here, we
considered the inputs of SR flip-flop as S = J Q(t)’ and R =
KQ(t) in order to utilize the modified SR flip-flop for 4
combinations of inputs.
The following table shows the state table of JK flip-flop.

J K Q(t + 1)
0 0 Q(t)
0 1 0
1 0 1
1 1 Q(t)'

Here, Q(t) & Q(t + 1) are present state & next state respectively.
So, JK flip-flop can be used for one of these four functions such
as Hold, Reset, Set & Complement of present state based on the
input conditions, when positive transition of clock signal is
applied. The following table shows the characteristic table of
JK flip-flop.

Present Inputs Present State Next State

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

By using three variable K-Map, we can get the simplified

expression for next state, Q(t + 1). Three variable K-Map for
next state, Q(t + 1) is shown in the following figure.
The maximum possible groupings of adjacent ones are already
shown in the figure. Therefore, the simplified expression for
next state Q(t+1) is
Q(t+1)=JQ(t)′+K′Q(t)
T Flip-Flop
T flip-flop is the simplified version of JK flip-flop. It is obtained
by connecting the same input ‘T’ to both inputs of JK flip-flop.
It operates with only positive clock transitions or negative clock
transitions. The circuit diagram of T flip-flop is shown in the
following figure.
This circuit has single input T and two outputs Q(t) & Q(t)’. The
operation of T flip-flop is same as that of JK flip-flop. Here, we
considered the inputs of JK flip-flop as J = T and K = T in order
to utilize the modified JK flip-flop for 2 combinations of inputs.
So, we eliminated the other two combinations of J & K, for
which those two values are complement to each other in T flip-
flop.
The following table shows the state table of T flip-flop.

D Q(t + 1)
0 Q(t)
1 Q(t)’

Here, Q(t) & Q(t + 1) are present state & next state respectively.
So, T flip-flop can be used for one of these two functions such
as Hold, & Complement of present state based on the input
conditions, when positive transition of clock signal is applied.
The following table shows the characteristic table of T flip-
flop.

Present Next
Inputs
State State
T Q(t) Q(t + 1)
0 0 0
0 1 1
1 0 1
1 1 0

From the above characteristic table, we can directly write the

next state equation as
Q(t+1)=T′Q(t)+TQ(t)′
⇒Q(t+1)=T⊕Q(t)
The output of T flip-flop always toggles for every positive
transition of the clock signal, when input T remains at logic
High (1). Hence, T flip-flop can be used in counters.
In this chapter, we implemented various flip-flops by providing
the cross coupling between NOR gates. Similarly, you can
implement these flip-flops by using NAND gates.