LABORATORY RECORD

FOR

VLSI Design LAB

III [Link], ECE

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VLSI Design LAB: PART-A
LIST OF EXPERIMENTS

[Link]. Name of the experiment

1. CMOS Inverter
2. CMOS - NAND and NOR Gates
3. CMOS – AND and OR Gates
4. CMOS - Ex-OR Gate and Ex-NOR Gate
5. CMOS AOI Gate

OBJECTIVE:
Objective of this lab is to learn the Virtuoso tool as well learn the first
step in flow of the Full Custom IC design cycle. In this process you will design
the circuit and verify its functionality using simulation. You will create a new
cell with schematic view and hence build the schematic by instantiating various
components. Once schematic is done, this circuit is verified by doing various
simulations using spectre. In the process, you will learn to use spectre,
waveform window options, waveform calculator, etc...

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 PROCEDURE

Procedure to enter in to the virtuoso Environment

 Right click on the desktop and click on the open terminal.
 A new window opens. Give the commands:
mount –t nfs cadence: /root/cadenceDB/ /root/cadenceDB/
cd database

csh

source cshrc1
cd cadence_ms_labs_613
virtuoso
 A command interpreter window will open.
Procedure to create Schematic
 Go to file -> library -> Create Library and cell view.
 A virtuoso schematic window opens, then create your own schematic.
 To create schematic, go to create -> instance (I). Add instance window opens, then
browse Library -> gpdk180/analog lib ->pmos /nmos/Vdd/Vdc/gnd -> symbol and then
close.
 To connect the terminals, go to create -> wire narrow (W).
 For input, output or input-output pins, go to create -> pin (P).
 To change the properties of any component, select the component and press „Q‟.
 Using the above steps required schematic can be created.
 Go to file -> check & save.
Procedure for the Transient Analysis:
 Go to launch -> ADEL. Virtuoso Analog Design Environment window will open.
 Click on setup->select stimuli to apply inputs.
 Click on analyses -> choose. For transient response, enable „trans‟ and enter some value
for stop time. Enable „moderate‟ and then click apply & OK.
 Go to outputs -> to be plotted -> select on schematic. Select the input and output wires in
the schematic and return to ADE window. Go to simulation ->netlist& run.
 After few seconds, the transient response will be displayed. In that, click on „strip chart
mode‟, to split the plotted waveforms.

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VLSI Design LAB: PART-B
LIST OF EXPERIMENTS

[Link]. Name of the experiment

6. Logic Gates

7. Full Adder
8. Full Subtractor
9. 2to 8 DECODER
10. 8X1 MULTIPLEXER
11. Flip Flop’s
12. Binary counter

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PROCEDURE TO WORK WITH XILINX TOOL
After installing Xilinx software go to start menu, Programs →Xilinx→ Project
navigator

1. Select file →New project

2. A window given below will be appearing. Write the project name like “and
gate” then click next.

3. The below window will be displayed. In the project device options select the
following options shown in the fig. and then click on Next.

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4. The following window will be displayed. Click on new source.

5. Then the following window will be displayed. Select VHDL Module and
write the file name as same as project name. And click Next button.

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6. Then the following window will be displayed. Provide inputs and outputs.
And click next

7. Click finish button. Then the following window will be displayed.

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8. Click Next two times and Finish once for upcoming windows. A dummy
program will be created as shown in the following window.

9. Make the changes in the program according to your requirements and save
the program.

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[Link] check syntax if the check syntax is completed successfully.
Synthesize the program. You will get the synthesis report, schematic and
Technology Schematic.

CREATING TEST BENCH FOR THE VHDL MODEL

1. Create a test bench by Right clicking on the project name and Select new
source. As shown in the fig.
2.

2. Select VHDL Test bench and give the file name as “tb_Program name” and
click next. A dummy test bench will be created. Provide the test bench and save
the test bench.

3. Perform Check syntax and simulate test bench. SIMULATION RESULTS

will bedisplayed

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VFSTR UNIVERSITY DEPT OF ECE

[Link] DATE:
[Link] INVERTER

AIM:-
To design a CMOS Inverter and verify its functionality using transient response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:
The inverter is universally accepted as the most basic logic gate doing a Boolean operation on
a single input variable and CMOS is sometimes referred to as complementary-symmetry metal–
oxide–semiconductor. The words "complementary-symmetry" refer to the fact that the typical digital
design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide
semiconductor field effect transistors (MOSFETs) for logic functions. Two important characteristics
of CMOS devices are high noise immunity and low static power consumption. Significant power is
only drawn while the transistors in the CMOS device are switching between on and off states.
Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for
example transistor-transistor logic (TTL) or NMOS logic, which uses all n-channel devices without p-
channel devices.
The CMOS inverter, a logic gate which converts high input to low and low to high. When the input is
high, the n-MOSFET on the bottom switches on, pulling the output to ground. The p-MOSFET on top
switches OFF. When the input is low, the gate-source voltage on the n-MOSFET is below its
threshold, so it switches off, the p-MOSFET switches on to pull the output high. It consists of only
two transistors, a pair of one N-type and one P-type transistor. If the input voltage is „1‟ (VCC) the P-
type transistor on top is non-conducting and provides a path from GND to the output Y. The output
level therefore is „0‟. On the other hand, if the I/P level is „0‟, the P-transistor is conducting and
provides a path from VCC to the output Y, so that the output level is „1‟ while N-type transistor is
blocked.

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SYMBOL:

__
Vdd Vout=(Vin)‟
Vi Vout
n

gnd

TRUTH TABLE:

Vin Vout (Theoritical) Vout ( Practical)

0(0v) 1(1.8v)

1(1.8v) 0(0v)

TRANSIENT ANALYSIS:

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THE SWITCHING LEVEL OPERATION (ON/OFF) OF THE CMOS INVERTER :

Vin PMOS NMOS Conduction Path of Y
T1 T2 Transistors
0(0v) ON OFF T1 1(1.8v)
1(1.8v) OFF ON T2 0(0V)

RESULT:

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MODEL VIVA QUESTIONS

1) What is the latch up problem that arises in bulk CMOS technology? How is it overcome?
2) Explain the operation of CMOS Inverter using transfer characteristic curves.
3) Distinguish between the bulk CMOS technology with the SoI technology fabrications?
4) In CMOS inverter, PMOS is preferably in pull up stage and NMOS in pull down stage. Why?
5) How CMOS inverter will acts if we interchange NMOS and PMOS positions?
6) Draw the ideal characteristics of a CMOS inverter and compare it with the actual
characteristics?
7) What is noise margin? Find out the noise margin from the actual characteristics the inverter.
8) What is the lower limit of supply voltage of a CMOS inverter? What happens if the supply
voltage is further reduced?
9) What are the various ways to reduce the delay time of a CMOS inverter?
10) Explain the commonly used technique to estimate the delay time of a CMOS inverter?
11) Define nMOS and pMOS transistors.
12) Differentiate enhancement and depletion mode transistors.
13) Compare nMOS and CMOS.
14) What is the abbreviation of ECAD.
15) What is meant by Gpdk 180nm Technology.

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NAND GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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[Link] DATE:
NAND and NOR GATES
AIM:-
To design a two-input CMOS NAND and NOR gates and verify their functionalitiesusing
transient response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:
NAND GATE:
NAND gate is actually a combination of two logic gates: AND gate followed by NOT gate.
The first part is an AND gate and second part is a dot after it represents a NOT gate. So it is clear
that during the operation of NAND gate, the inputs are first going through AND gate and after that
the output is reversed and we get the final [Link] its output is complement of the output of an
AND gate.
The NAND gate and the NOR gate can be said to be universal gates since combinations of
them can be used to accomplish any of the basic operations and can thus produce an Inverter, an OR
gate or an AND gate. The non-inverting gates do not have this versatility since they can‟t produce an
invert.
The output of NAND gate is high if any of the inputs are low. In the NAND gate the P-type
transistors are connected in parallel between VCC and the output Y, while the N-type transistors are
connected in series from GND to the output Y. If any of the input is LOW, one of two PMOS
transistor will ON and path is established between Output and VDD, hence Output is HIGH. If both
the two inputs are LOW, then both the PMOS transistors are ON and both the NMOS transistors are
OFF. Therefore, path is established between output and VDD and no path is existed between GND
and Output. Hence, Output is HIGH. If the both inputs are HIGH, then both the NMOS transistors
are ON and both the PMOS transistors are OFF. Therefore, path is established between output and
GND and no path is existed between VDD and Output. Hence, the Output is LOW.

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NOR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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NOR GATE:
THEORY:
NOR gate is actually a combination of two logic gates: OR gate followed by NOT gate. The
first part is an OR gate and second part is a dot after it represents a NOT gate. So it is clear that
during the operation of NOR gate, the inputs are first going through OR gate and after that the output
is reversed and we get the final [Link] its output is complement of the output of an OR gate.
The NAND gate and the NOR gate can be said to be universal gates since combinations of
them can be used to accomplish any of the basic operations and can thus produce an Inverter, an OR
gate or an AND gate. The non-inverting gates do not have this versatility since they can‟t produce an
invert.
.The output of NOR gate isLOW if any of the inputs are HIGH. In the NOR gate the N-type
transistors are connected in parallel between GND and the output Y, while the P-type transistors are
connected in series fromVDD to the output Y. If any of the input is HIGH, one of two NMOS
transistor will ON and path is established between Output and GND, hence Output is LOW. If both
the two inputs are HIGH, then both the PMOS transistors are OFF and both the NMOS transistors
are ON. Therefore, path is established between output and GND and no path is existed between
VDD and Output. Hence, Output is LOW. If the both inputs are LOW, then both the PMOS
transistors are ON and both the NMOS transistors are OFF. Therefore, path is established between
output and VDD and no path is existed between GND and Output. Hence, the Output is HIGH.

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NAND GATE:

TRUTH TABLE:

a b Therical Y Practical Y
0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v)

1(1.8v) 1(1.8v) 0(0v)

SYMBOL:

Y = (a.b)’

TRANSIENT ANALYSIS:

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NOR GATE:
TRUTH TABLE:
Vin1 Vin2 Theoretical Practical
Vout Vout
0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 0(0v)
1(1.8v) 0(0v) 0(0v)
1(1.8v) 1(1.8v) 0(0v)

SYMBOL:

Vout = ( a+b)’

TRANSIENT ANALYSIS:

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THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE CMOS NAND GATE:

A B PMOS PMOS NMOS NMOS Conduction Path of Y
T1 T2 T3 T4 Transistors
0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v)
1(1.8v) 1(1.8v) 0(0v)

The switching level operation (ON/OFF) of the CMOS NOR GATE:

Vin1 Vin2 PMOS PMOS NMOS NMOS Conduction Path of Y
T1 T2 T3 T4 Transistors
0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 0(0v)
1(1.8v) 0(0v) 0(0v)
1(1.8v) 1(1.8v) 0(0v)

RESULT:

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MODEL VIVA QUESTIONS

1. How the transfer characteristic of a CMOS NAND gate is affected with increase in fan-in?
2. How the transfer characteristic of a CMOS NOR gate is affectedwith increase in fan-in?
3. How switching characteristic of a CMOS NAND gate is affectedwith increase in fan-in?
4. How switching characteristic of a CMOS NOR gate is affectedwith increase in fan-in?
5. How noise margin of a CMOS NAND/NOR gate is affected withincrease in fan-in?
6. What are universal gates? Why called so.
7. Draw the pull up section of NAND gate and NOR gates?
8. Draw the pull down section of NAND gate and NOR gates?
9. Explain the logical operation of NAND gate with the help of a truth table?
10. Explain the logical operation of NOR gate with the help of truth table.
[Link] the 3 input CMOS NAND gate.
[Link] the 3 input CMOS NOR gate.

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AND GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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[Link]: 03 DATE:
AND and OR GATES
AIM:-To design a two-input CMOS AND and OR gates and verify their functionalities using transient
response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

AND GATE:
THEORY:
The AND gate is a basic digital logic gate that implements logical conjunction. A HIGH
output (1) results only if both the inputs to the AND gate are HIGH (1). If neither or only one input to
the AND gate is HIGH, a LOW output results. In another sense, the function of AND effectively finds
the minimum between two binary digits. Therefore, the output is always 0 except when all the inputs
are [Link] available Digital Logic AND Gate IC‟s include:
TTL Logic AND GatesCMOS Logic AND Gates

 CD4081 Quad 2-input 74LS08 Quad 2-input

 74LS11 Triple 3-input CD4073 Triple 3-input
 74LS21 Dual 4-input CD4082 Dual 4-input

If no specific AND gates are available, one can be made from NAND or NOR gates, because NAND
and NOR gates are considered the "universal gates," meaning that they can be used to make all the
others. XOR Gates can also be used to simulate AND functions, but are rarely used to do so.

NAND construction for

Desired gate
AND NOR construction for AND

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OR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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VFSTR UNIVERSITY DEPT OF ECE

OR GATE:
THEORY:
The OR gate is a digital logic gate that implements logical disjunction. A HIGH output (1)
results if one or both the inputs to the gate are HIGH (1). If neither input is high, a LOW output (0)
results. In other sense, the function of OR effectively finds the maximum between two library digits.
Commonly available Digital Logic OR Gate IC‟s include:
TTL Logic OR GatesCMOS Logic OR Gates

 74LS32 Quad 2-input CD4071 Quad 2-input

CD4075 Triple 3-input

CD4072 Dual 4-input

If no specific OR gates are available, one can be made from NAND or NOR gates in the configuration
shown in the image below. Any logic gate can be made from a combination ofNAND or NOR gates.

NAND Construction for OR NOR construction for OR

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AND GATE:
TRUTH TABLE:
X Y Z Z
Theoretical Practical
0(0v) 0(0v) 0(0v)
0(0v) 1(1.8v) 0(0v)
1(1.8v) 0(0v) 0(0v)
1(1.8v) 1(1.8v) 1(1.8v)

SYMBOL:

Z = ( X.Y)

TRANSIENT ANALYSIS:

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THE SWITCHING LEVEL OPERATION (ON/OFF) OF THE CMOS AND GATE:

A B PMOS PMOS NMOS NMOS Conduction Path of Y
T1 T2 T3 T4 Transistors
0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 0(0v)
1(1.8v) 0(0v) 0(0v)
1(1.8v) 1(1.8v) 0(0v)

THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE CMOS OR GATE:

A B PMOS PMOS NMOS NMOS Conduction Path of Y
T1 T2 T3 T4 Transistors
0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v)
1(1.8v) 1(1.8v) 0(0v)

RESULT:

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OR GATE:
SYMBOL:

Vout = (Vin1 +Vin2)

TRUTH TABLE:
Vin1 Vin2 Theoretical Practical
Vout Vout
0(0v) 0(0v) 0(0v)
0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v)
1(1.8v) 1(1.8v) 1(1.8v)

TRANSIENT ANALYSIS:

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MODEL VIVA QUESTIONS

1. How the transfer characteristic of a CMOS AND gate is affected with increase in fan-in?
2. How the transfer characteristic of a CMOS OR gate is affected with increase in fan-in?
3. How switching characteristic of a CMOS AND gate is affected with increase in fan-in?
4. How switching characteristic of a CMOS OR gate is affected with increase in fan-in?
5. How noise margin of a CMOS AND/OR gate is affected with increase in fan-in?
6. What are basic gates? Why called so.
7. Draw the pull up section of AND gate and OR gates?
8. Draw the pull down section of AND gate and OR gates?
9. Explain the logical operation of AND gate with the help of a truth table?
10. Explain the logical operation of OR gate with the help of a truth table?
[Link] the 3 input CMOS NAND gate.
[Link] the 3 input CMOS NOR gate.

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Ex-OR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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[Link] DATE:
EX-OR and EX-NOR GATES
AIM :-To design a two-input CMOS EX-OR and EX-NOR gates verify their functionalities using
transient response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

EX-OR GATE:
THEORY:
The X in the EXOR gate stands for “exclusive.” This means that the output from this gate will
be a 1 only when one or the other of the inputs is a 1. If an XOR gate has more than two inputs, then
its behaviour depends on implementation. In the vast majority of cases, an XOR gate will output true
if and odd number of its inputs is true. However, it‟s important to note that this behaviour differs from
the strict definition or exclusive OR, which insists that exactly one input must be true for the output to
be true.
Exclusive-OR Gates are used mainly to build circuits that perform arithmetic operations and
calculations especially Adders and Half-Adders as they can provide a “carry-bit” function or as a
controlled inverter, where one input passes the binary data and the other input is supplied with a
control signal.
Commonly available Digital Logic Exclusive-OR Gate IC‟s include:

TTL Logic Ex-OR GatesCMOS Logic Ex-OR Gates

 74LS86 Quad 2-input CD4030 Quad 2-input

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Ex-NOR GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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VFSTR UNIVERSITY DEPT OF ECE

EX-NOR GATE:
THEORY:
An XNOR gate is a digital logic gate with two or more inputs and one output that performs
logical equality. The output of an XNOR gate is true when all of its inputs are true or when all of its
inputs are false. If some of its inputs are true and others are false, then the output of XNOR gate is
false. XNOR gates are represented in most TTL and CMOS IC families. The standard 4000 series
CMOS IC is the 4077 and the TTL IC is the 74266. Both include four independent, two-input, XNOR
gates. OUTPUT is high only if all its inputs are the same.
Ex-NOR gates are used mainly in electronic circuits that perform arithmetic operations and
data checking such as Adders, Subtractors or Parity Checkers, etc. As the Ex-NOR gate gives an
output of logic level “1” whenever its two inputs are equal it can be used to compare the magnitude of
two binary digits or numbers and so Ex-NOR gates are used in Digital Comparator circuits.
Commonly available Digital Logic Exclusive-NOR Gate IC‟s include:
TTL Logic Ex-NOR Gates CMOS Logic Ex-NOR Gates

74LS266 Quad 2-input CD4077 Quad 2-input

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Ex-OR GATE:
TRUTH TABLE:

A B Y (Theoretical) Y( Practical)
0(0v) 0(0v) 0(0v)
0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v)
1(1.8v) 1(1.8v) 0(0v)

SYMBOL:

Y = a‟ b + a b‟

TRANSIENT ANALYSIS:

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THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE Ex-OR GATE:

A B PM0 PM1 PM2 PM3 NM0 NM1 NM2 NM3 Conduction Path of Y
T1 T2 T3 T4 T5 T6 T7 T8 Transistors
0v 0v 0v

0v 1.8v 1.8v

1.8v 0v 1.8v

1.8v 1v 0v

THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE Ex-NOR GATE:

A B PM0 PM1 PM2 PM3 NM0 NM1 NM2 NM3 Conduction Path of Y
T1 T2 T3 T4 T5 T6 T7 T8 Transistors
0v 0v 0v

0v 1.8v 1.8v

1.8v 0v 1.8v

1.8v 1v 0v

RESULT:

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Ex-NOR GATE:
TRUTH TABLE:
A B Y Y
(Theoretical) (Practical)
0(0v) 0(0v) 1(1.8v)

0(0v) 1(1.8v) 0(0v)

1(1.8v) 0(0v) 0(0v)

1(1.8v) 1(1.8v) 1(1.8v)

SYMBOL:

Y = (a‟ b + a b‟)‟

TRANSIENT ANALYSIS:

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MODEL VIVA QUESTIONS

1. How the transfer characteristic of a CMOS Ex-OR gate is affected with increase in fan-in?
2. How the transfer characteristic of a EX-NOR gate is affected with increase in fan-in?
3. How switching characteristic of a CMOS Ex-OR gate is affected with increase in fan-in?
4. How switching characteristic of a CMOS Ex-NOR gate is affected with increase in fan-in?
5. How noise margin of a CMOS Ex-OR/ Ex-NOR gate is affected with increase in fan-in?
6. What are arithmetic gates? Why called so.
7. Draw the pull up section of Ex-OR gate and Ex-NOR gates?
8. Draw the pull down section of Ex-OR gate and Ex-NOR gates?
9. Explain the logical operation of Ex-OR gate with the help of a truth table?
10. Explain the logical operation of Ex-NOR gate with the help of a truth table?
11. What is equivalence gate.

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AOI GATE:
BLOCK DIAGRAM WITH ITS BEHAVIOUR:

SCHEMATIC DIAGRAM:

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[Link] GATE
AIM:-To design anAOI gate and verify their functionalities using transient response.
TOOLS USED:
 Cadence Virtuoso
 Gpdk 180nm Technology

THEORY:
The AOI gate, as its name suggests, enables the sum-of-products realization of a
BooleanFunction in one logic stage. The pull-down net of the AOI gate consistsofparallel branches of
series-connected N-MOS driver transistors. The corresponding p-typepull-up network can simply be
found using the dual-graph concept.

A function is a good example of AND-OR-INVERT (AOI) because it

performs the NOR of apair of two input ANDs.
AOI gates are particularly advantaged in that the total number of transistors (or gates) is less
than if the AND, NOT, and OR functions were implemented separately. This results in increased
speed, reduced power, smaller area, and potentially lower fabrication cost.
The OAI gate, on the other hand, enables the product-of-sums realization of aBoolean function in one
logic stage. The pull-down net of the OAI gateconsists of series branches of parallel-connected nMOS
driver transistors, while thecorresponding p-type pull-up network can be found using the dual-graph
concept.

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TRUTH TABLE:

A B C D Theoretical Practical
Y Y
0(0v) 0(0v) 0(0v) 0(0v) 1(1.8v)
0(0v) 0(0v) 0(0v) 1(1.8v) 1(1.8v)
0(0v) 0(0v) 1(1.8v) 0(0v) 1(1.8v)
0(0v) 0(0v) 1(1.8v) 1(1.8v) 0(0v)
0(0v) 1(1.8v) 0(0v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 0(0v) 1(1.8v) 1(1.8v)
0(0v) 1(1.8v) 1(1.8v) 0(0v) 1(1.8v)
0(0v) 1(1.8v) 1(1.8v) 1(1.8v) 0(0v)
1(1.8v) 0(0v) 0(0v) 0(0v) 1(1.8v)
1(1.8v) 0(0v) 0(0v) 1(1.8v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v) 0(0v) 1(1.8v)
1(1.8v) 0(0v) 1(1.8v) 1(1.8v) 0(0v)
1(1.8v) 1(1.8v) 0(0v) 0(0v) 0(0v)
1(1.8v) 1(1.8v) 0(0v) 1(1.8v) 0(0v)
1(1.8v) 1(1.8v) 1(1.8v) 0(0v) 0(0v)
1(1.8v) 1(1.8v) 1(1.8v) 1(1.8v) 0(0v)

LOGIC DIAGRAM:

TRANSIENT ANALYSIS:

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THE SWITCHING LEVEL OPRERATION (ON/OFF) OF THE Ex-OR GATE:

A B C D PM0 PM1 PM2 PM3 NM0 NM1 NM2 NM3 Conduction Y
T1 T2 T3 T4 T5 T6 T7 T8 Path of
Transistors
0V 0V 0V 0V 1.8V
0V 0V 0V 1.8 V 1.8V
0V 0V 1.8 V 0V 1.8V
0V 0V 1.8 V 1.8 V 0V
0V 1.8 V 0V 0V 1.8V
0V 1.8 V 0V 1.8 V 1.8V
0V 1.8 V 1.8 V 0V 1.8V
0V 1.8 V 1.8 V 1.8 V 0V
1.8V 0V 0V 0V 1.8V
1.8V 0V 0V 1.8 V 1.8V
1.8V 0V 1.8 V 0V 1.8V
1.8V 0V 1.8 V 1.8 V 0V
1.8V 1.8 V 0V 0V 0V
1.8V 1.8 V 0V 1.8 V 0V
1.8V 1.8 V 1.8 V 0V 0V
1.8V 1.8 V 1.8 V 1.8 V 0V

RESULT:

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MODEL VIVA QUESTIONS

13) For a complex/compound CMOS logic gate, how do you realize the pull-up and the pull-
down networks?
14) Give the two possible topologies AND-OR-INVERT AND-ORINVERT (AOI) and OR-
AND-INVERT (OAI) to realize CMOS logic gate. Explain with an example.
15) Give the AOI and OAI realizations for the sum and carry functions of a full adder.
16) what are Compound Gate? Explain why.
17) Explain the operation of AOI gate with the help of truth table?
18) Draw all possible ways to implement AOI Gates?
19) Draw all possible ways to implement OAI Gates?
20) Draw the Digital implementation of AOI gates with help of universal gates?
21) Draw the Digital implementation of OAI gates with help of universal gates?
22) Compare the PULL DOWN sections of XOR GATES AND AOI gates?

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6. Logic Gates

Aim: Design of all Basic gates, Universal gates and simulates it on Xilinx Software.

Software Used: Xilinx ISE

Theory:

A logic gate is an elementary building block of a digital circuit. Most of the logic gates have two
inputs and one output. At any given moment, every terminal is in one of the two binary conditions low
(0) or high (1), represented by different voltage levels. The logic state of a terminal can, and generally
does, change often, as the circuit processes data. In most logic gates, the low state is approximately
zero volts (0 V), while the high state is approximately five volts positive (+5 V).There are seven basic
logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

Algorithm:

 Make sure that Logic Diagram/Symbol and truth table should be known for all the logic gates.
 For all logic gates input have to instantiated in the entity declarations.i.e., A,B is declared as
inputs and Z is declared as output is of signal type std_logic
 Inside the Architecture body, all the logic gates inputs have to assigned to the output by using
signal assignment statement ( Z<=A and B).

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Logic Symbol for AND Gate:

Truth Table for AND Gate

Model graph for AND Gate

Logic Symbol for OR Gate:

Truth Table for OR Gate

Model graph for OR Gate

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VHDL Code for Logic Gates:

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Logic Symbol for NOT Gate:

Truth Table for NOT Gate

Model graph for NOT Gate

Logic Symbol for NAND Gate:

Truth Table for NAND Gate

Model graph for NAND Gate

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VHDL Code for Logic Gates:

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Logic Symbol forNOR Gate:

Truth Table for NAND Gate

Model graph for NOR Gate

Logic Symbo l forEx-OR Gate:

Truth Table for Ex-OR Gate

Model Graph forEx-OR Gate

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Test Bench for Logic Gates:

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Logic Symbol forEx-NOR Gate

Truth Table for Ex-NOR Gate

Model graph for Ex-Nor Gate

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Test bench for logic gates:

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Model Viva Questions:

1. Define logic gate?
2. Difference between universal gates and basic gates?
3. Implement inverter using nand gates?
4. Implement inverter using NOR gates?
5. Implement OR gate using multiplexer?
6. Implement the following function using VHDL coding. (Try to minimize if you can).
F(A,B,C,D)=(A′+B+C) . (A+B′+D′). (B+C′+D′) . (A+B+C+D)
7. What will be the no. of rows in the truth table of N variables?
8. What are the advantages of VHDL?
9. Design Ex-OR gate using behavioral model?
10. Implement the following function using VHDL codef=AB+CD.

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7. Full Adder
Aim: Design of afull adderusing 3 modeling stylesand simulate it on Xilinx Software.

Software Used:Xilinx ISE

Theory:

Half Adder:

A combinational circuit that performs an addition of two bits is called half adder. For this the circuit
needs two binary inputs and two binary outputs. The input variables designate the augend and addend
bits; the output variable produces the sum and carry.

Algorithm 2:

1. Make sure that Logic Diagram and truth table should be known for the Full Adder .
2. For all Full Adder inputs have to instantiated in the entity declarations i.e., A,B,C in is declared
as inputs and sum,carry is declared as outputs and is of signal type std_logic
3. Full adder can be implemented either in dataflow,structural and behavioral style of modeling.

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Logic Diagram for Full Adder:

Truth Table for the Full Adder:

Model graphs for the Full Adder:

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VHDL Code for Full Adder

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VHDL Code for Full Adder:

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VHDL Code for Full Adder

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Test bench for Full Adder

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Model Viva Questions:

1. What are the differences between half adder and full adder?
2. What are the advantages of minimizing the logical expressions?
3. What does a combinational circuit mean?
4. Implement the half adder using VHDL code?
5. Implement the full adder using two half adders and write VHDL program in structural model?
[Link] expression for difference and borrow in Half adder.
[Link] expression for difference and borrow in Full adder.
[Link] Full adder using Half adders.
[Link] many NAND are needed to implement Half adder?
[Link] many NAND are needed to implement Full adder?
[Link] many NOR are needed to implement Half adder?
[Link] many NOR are needed to implement Full adder?

Results:

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8. Full Subtractor
Aim: Design of full subtractor using 3 modeling styles and simulate it on Xilinx Software.

Software Used:Xilinx ISE

Theory:

Full Subtractor:

A full subtractor is a combinational circuit that performs a difference of three input bits. For this the
circuit needs three binary inputs and two binary outputs. Two of the input variables represent two
significant bits to be subtracted. The third input represents a borrow from the previous lower
significant position. A two-output variable represents the difference and borrow.

Algorithm 1:

1. Make sure that Logic Diagram and truth table should be known for the Full Subtarctor .
2. For all Full Subtractor inputs have to instantiated in the entity declarations i.e., A,B,Bin is
declared as inputs and Difference, Borrow is declared as outputs and are of signal type
std_logic
3. Full Subtractor can be implemented in dataflow, structural and behavioral style of modeling.

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Logic Diagram for Full Subtractor:

Truth Table for the Full Subtractor:

Model graphs for the Full Subractor:

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VHDL Code for Full Subtractor

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Test Bench for Full Subtractor:

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VHDL Code for Full Subtractor

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Test bench for Full Subtractor

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Model Viva Questions:
1. Give expression for difference and borrow in Half Subtractor
2. Give expression for difference and borrow in Full Subtractor
3. Implement Full Subtractor using Half Subtractors
4. How many NAND are needed to implement Half Subtractor?
5. How many NAND are needed to implement Full Subtractor?
6. How many NOR are needed to implement Half Subtractor?
7. How many NOR are needed to implement Full Subtractor?
8. Implement Half Subtractor using VHDL code.
9. Implement Full Subtractor using Half Subtractor and write VHDL program in structural style.
10. Difference in expressions of Half Adder and Half Subtractor
11. Difference in expressions of Full Adder and Full Subtractor

Results:

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9. 2to 8 DECODER
Aim:Design & Write a VHDL code for 2-4 Decoder and verify its functionality by writing test bench.

Software Used: Xilinx ISE

Theory:

A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into
coded outputs, where the input and output codes are different.
The input code generally has fewer bits than the output code, and there is a one-to-one
mapping from input code words into output code words.
In a one-to-one mapping, each input code word produces a different output code word.

[Link] circuit structure.

The general structure of a decoder circuit is shown in above Figure. The enable inputs, if
present, must be asserted for the decoder to perform its normal mapping function.
The most commonly used input code is an n-bit binary code, where an n-bit word represents one of 2n
different coded values, normally the integers from 0 through 2n-1.

2-4Decoder
This Decoder has one enable input which is active high and 4 outputs which are active high.
The binary decoder‟s truth table introduces a “don‟t-care” notation for input combinations. If
one or more input values do not affect the output values for some combination of the remaining inputs,
they are marked with an “x” for that input combination. This convention can greatly reduce the
number of rows in the truth table, as well as make the functions of the inputs more clear.

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Logic Symbol:

Truth Table:
Inputs outputs
EN I1 I0 Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0

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Algorithm:

 2-to-4 Decoder has 2 code inputs (I1,I0) and 4 code outputs (Y3downto Y0).
 1 enable input (E), one is active high enable.
 Declare the code inputs, Enable inputs and code outputs in Entity declaration part.

 Declare the required components and signals in Architecture definition part. (STRUCTURAL
STYLE)

 Declare the component label, name and port map with required component instantiation
statement for structural style. Otherwise based on VHDL styles define Architecture body.
(STRUCTURAL STYLE)

 Write the signal assignment statements for the logic. (dataflow)

 Write the process statement and logic. (behavioral)

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Logic Diagram:

Model Output Waveforms:

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VHDL Code:

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Test Bench:

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MODEL VIVA QUESTIONS:

1. Define functionality of decoder.

2. Write the syntax of CASE statement.
3. What are the applications of decoders
4. A device which converts BCD to Seven Segment is called -----
5. What is difference between demultiplexer and a decoder.
6. What does priority encoder mean?
7. How many 2-4 decoders are needed to construct 4X16 decoder?
8. What is the difference between decoder and encoder?
9. Write the syntax for exit statement?
10. Explain briefly about next statement?
11. How to specify the delay in VHDL program?
12. Write the syntax for component declaration.

Result:

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10. 8x1 MULTIPLEXER
AIM:Design & Write a VHDL code for 8X1 Multiplexer and verify its functionality by writing test
bench.
Software Used: Xilinx ISE

Theory:

Multiplexer is a digital switch or Many into One and also called Data Selector. Multiplexer allows
digital information from several sources routed on to single data out put.

Fig. Multiplexer structure with inputs and outputs

The selection of particular input line is controlled by a set of select lines. Normally there are 2n input
lines and n select lines. Select lines determine whose input is selected.
The 74x151 is 8-input 1-bit Multiplexer, The 74x151, selects among eight 1-bit inputs. The
select inputs are named C, B, and A, where C is most significant numerically. The enable input EN_L
is active low; both active-high (Y) and active-low (Y_L) versions of the output are provided.
Algorithm:
 8-to-1 Multiplexer has 8 data inputs (D0 to D7), Y is the output and Y_L is the negated output.
 3 select inputs (A, B and C), all three are the active high.
 One Enable input EN_L : Enable Low : Enables when 0,
Disables when 1.
 EN_L is active low then based on selection inputs output selects the data input otherwise the
output is the “null”.
 C is the Most Significant select input Bit
 A is the Least Significant select input Bit
 Declare the data inputs, Enable input and outputs (active high and low) in Entity declaration
[Link] the required components and signals in Architecture definition part.
 Declare the component label, name and port map with required component instantiation
statement for structural style. Otherwise based on VHDL styles define Architecture body.

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Logic Symbol:

Truth Table:

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VHDL Code:

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Logic Diagram:

Model Output Waveforms:

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Test Bench:

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MODEL VIVA QUESTIONS:

1. What is meant by multiplexer.

2. Write the syntax of IF statement.
3. What is the difference between CASE & WITH statements.
4. How many select lines required for 64:1 mux.
5. What does demultiplexer mean?
6. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
7. Compare decoder with demultiplexer?
8. Design a full adder using 8X1 multiplexer?
9. What are the two kinds of subprograms?
10. What are the difference between function and procedure?
11. Explain briefly about subprogram overloading?

Result:

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11. Flip Flops

AIM: Design & Write a VHDL code for Flip-Flop‟s and verify its functionality by writing test bench,
using any two VHDL Styles.

Software Used: Xilinx ISE

Theory:

Flip-flops can be divided into common types: the SR ("set-reset"), D ("data" or

[11]
"delay" ), T ("toggle"), and JK types are the common ones. The behavior of a particular type can be
described by what is termed the characteristic equation, which derives the "next" (i.e., after the next
clock pulse) output, Qnext in terms of the input signal(s) and/or the current output, .

D flip-flop:

The D flip-flop is widely used. It is also known as a "data" or "delay" [Link] D flip-flop captures
the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock).
That captured value becomes the Q output. At other times, the output Q does not change.[21][22] The D
flip-flop can be viewed as a memory cell, a zero-order hold, or adelay line.

SR Flip Flop:

The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair of
cross-coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an active
LOW SR NAND Gate Latch, so that there is feedback from each output to one of the other NANDgate
inputs. This device consists of two inputs, one called the Set, S and the other called the Reset,R with
two corresponding outputs Q and its inverse or complement Q (not-Q) as shown logic diagram

The Set State

Consider the circuit shown above. If the input R is at logic level “0” (R = 0) and input S is at logic
level “1” (S = 1), the NAND gate Y has at least one of its inputs at logic “0” therefore, its
output Q must be at a logic level “1” (NAND Gate principles). Output Q is also fed back to input “A”
and so both inputs to NAND gate X are at logic level “1”, and therefore its output Q must be at logic
level “0”.

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Logic Symbol:
SR Flip Flop:

JK Flip Flop:

T Flip Flop:

D-Flip Flop:
PIN DIAGRAM:

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Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic “1”
with Sremaining HIGH also at logic level “1”, NAND gate Y inputs are now R = “1” and B = “0”.
Since one of its inputs is still at logic level “0” the output at Q still remains HIGH at logic level “1”
and there is no change of state. Therefore, the flip-flop circuit is said to be “Latched” or “Set”
with Q = “1” and Q = “0”.

Reset State

In this second stable state, Q is at logic level “0”, (not Q = “0”) its inverse output at Q is at logic level
“1”, (Q = “1”), and is given by R = “1” and S = “0”. As gate X has one of its inputs at logic “0” its
outputQ must equal logic level “1” (again NAND gate principles). Output Q is fed back to input “B”,
so both inputs to NAND gate Y are at logic “1”, therefore, Q = “0”.

If the set input, S now changes state to logic “1” with input R remaining at logic “1”, output Q still
remains LOW at logic level “0” and there is no change of state. Therefore, the flip-flop circuits
“Reset” state has also been latched and we can define this “set/reset” action in the following truth
table.

.JK flip-flop:

The JK flip-flop augments the behavior of the SR flip-flop (J=Set, K=Reset) by interpreting the S = R
= 1 condition as a "flip" or toggle command. Specifically, the combination J = 1, K = 0 is a command
to set the flip-flop; the combination J = 0, K = 1 is a command to reset the flip-flop; and the
combination J = K = 1 is a command to toggle the flip-flop, i.e., change its output to the logical
complement of its current value. Setting J = K = 0 does NOT result in a D flip-flop, but rather, will
hold the current state. To synthesize a D flip-flop, simply set K equal to the complement of J.
Similarly, to synthesize a T flip-flop, set K equal to J. The JK flip-flop is therefore a universal flip-
flop, because it can be configured to work as an SR flip-flop, a D flip-flop, or a T flip-flop.

The characteristic equation of the JK flip-flop is:

T flip-flop

If the T input is high, the T flip-flop changes state ("toggles") whenever the clock input is strobed. If
the T input is low, the flip-flop holds the previous value. This behavior is described by the
characteristic equation:

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CIRCUIT DIAGRAM:

Truth Table:
D Flip Flop:

JK Flip Flop:

T-Flip Flop:

(expanding the XOR operator)

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Algorithm:
D-Flip Flop: (74X74)
 Identify the how many inputs and outputs are required for developing of Dflipflop& Next write
the entity declaration.
 In between of the architecture develop the function of Dflipflop 7474 with help of truth table.
 For simulation to develop the test bench.
 Give the sufficient time dimensions.(observe the model graphs).
SR Flip Flop:
 Identify the how many inputs and outputs are required for developing of SR flipflop&Next
write the entity declaration.
 Declare the required components and signals in Architecture definition part.

 Declare the component label, name and port map with required component instantiation
statement for structural style. Otherwise based on VHDL styles define Architecture body.

 For simulation to develop the test bench.

 Give the sufficient time dimensions.(observe the model graphs).
Remaing Flip Flop also follows the same way.(Choose any design style in VHDL)

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VHDL Code:

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Model Output Waveforms:

JK Flip Flop:

D Flip Flop:

SR Flip Flop:

T-Flip Flop:

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VHDL Code:

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Test Bench:

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MODEL VIVA QUESTIONS:

1. Write the behavioral code for the IC 74x74.

2. Write the dataflow code for the IC 74x74.
3. What is the difference between sequential and combinational circuit?
4. What is a flip-flop?
5. Explain the functions of preset and clear inputs in flip-flop?
6. What is meant by a clocked flip-flop?
7. What is meant by excitation table?
8. What is the difference between flip-flop and latch?
9. What are the various methods used for triggering flip-flops?
10. Explain level triggered flip-flop?
11. Write the behavioral code for IC 74X74.
12. Write the syntax of IF statement?

Result:

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12. Binary Counter

AIMDesign & Write a VHDL code for Binary Counter and verify its functionality by writing test
bench.
Software Used: Xilinx ISE

Theory:
The modulus of a counter is the number of states in the cycle. A counter with m states is called a
modulo-m counter or, sometimes, a divide-by-m counter. A counter with a nonpower- of-2 modulus
has extra states that are not used in normal operation.
An n-bit binary counter can be constructed with just n flip-flops and no other components, for any
value of n.
T flip-flop changes state (toggles) on every rising edge of its clock input. Thus, each bit of the counter
toggles if and only if the immediately preceding bit changes from 1 to 0. This corresponds to a normal
binary counting sequence—when a particular bit changes from 1 to 0, it generates a carry to the
next most significant bit. The counter is called a ripple counter because the carry information ripples
from the less significant bits to the more significant bits, one bit at a time.

Algorithm:
 First write the entity for T FF by describing T, CLK, CLR as inputs and Q as INOUT.
 Initialize Q as „0‟
 Write the architecture body declaration
 Declare process statement with clk, clr as sensitivity list
 Use the IF statement to declare conditions for clk, clr
 Create a test bench for T FF for functional verification.
 Now write the program for decade counter using T FF using following instructions.
 Write the entity for decade counter with clock as input and Q(3)Q(2)Q(1)Q(0) as inout.
 Write the architecture body for decade counter by its syntax.
 Create 4 T FF instances using component instantiation statements or port map statements.
 Create a test bench for the above decade counter program.
 Give the clock stimuli and check the functional behavior of the Binary counter.

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Logic Diagram:

Truth Table:
Present state Next state
Clock( Negative Edge Transition) Q(3)Q(2)Q(1)Q(0) Q(3)Q(2)Q(1)Q(0)
1-0 0000 0001
1-0 0001 0010
1-0 0010 0011
1-0 0011 0100
1-0 0100 0101
1-0 0101 0110
1-0 0110 0111
1-0 0111 1000
1-0 1000 1001
1-0 1001 1010
1-0 1010 1011
1-0 1011 1100
1-0 1100 1101
1-0 1101 1110
1-0 1110 1111
1-0 1111 0000

Model Output Waveforms:

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VHDL Code:

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VHDL Code:

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Test Bench:

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MODEL VIVA QUESTIONS

[Link] is a sequential circuit?

[Link] between synchronous and asynchronous counter?
[Link] many [Link] flip-flops are required for decade counter?
[Link] is meant by excitation table?
[Link] are the meanings of different types of values in std_ulogic?
[Link] are the objects in VHDL?
[Link] the syntax for a signal?
[Link] the difference between signal and variable?
[Link] about enumeration types?
[Link] the modulus of a counter is 12 how many flip-flops are required?

Result:

VLSI Design LAB Page | 109