REPORT TITLE:
Intelligent Memory
Computers
2019-2020
Department: قسم هندسة الحاسوب
Student Name: ى
مرتض جنة تمار
Stage: المرحلة الثانية
Study: الدراسة الصباحية
College of Engineering
Class: A Mustansiriyah University
Course Name: Computer Architecture
Email: janna.alward8@[Link]
الحاسوب قسم الهندسة كلية الهندسة – الجامعة المستنصرية
A : الشعبة/ الثانية :المرحلة جنة تمار مرتضى : االسم
Introduction:
While processor performance has increased by about 58% annually since 1994,
memory system performance has not increased as quickly as the processor’s
performance. Dynamic Random Access Memory (DRAM) latency has decreased by
only about 7% annually, and DRAM bandwidth has increased about 15% annually.
The performance gap between the memory system and the processor has become a
performance bottleneck to total computer system performance.
The memory-processor performance gap is increasing as time progresses, making
the performance bottleneck worse.
Intelligent memory systems show promise in overcoming the memory system
performance bottleneck by building computational ability into the memory system.
Several intelligent memory systems have already been proposed, such as Active
Pages, the Data IntensiVe Architecture (DIVA), Intelligent RAM (IRAM), the User-
Level Memory Thread (ULMT) architecture, and others. Many of these intelligent
memory system architectures have shown impressive application speedup in
simulation.
In particular, The Active Pages project can improve performance by a factor of
about 1000 times, a Vector IRAM (VIRAM) architecture can provide a 100%
speedup, and the ULMT can provide up to a 58% speedup for some applications,
despite only acting as a prefetching device.
Despite impressive simulation studies, none of the proposed intelligent memory
system architectures has gained popular support for consumer computer systems.
Except for ULMT, perhaps this is due to the expense of integrating logic and DRAM
onto a single silicon die instead of using commodity DRAM. [1]
DRAM:
DRAM (Dynamic Random Access Memory) is the main memory used for all desktop
and larger computers. Each elementary DRAM cell is made up of a single MOS
transistor and a storage capacitor (Figure 1). Each storage cell contains one bit of
information. This charge, however, leaks off the capacitor due to the sub-threshold
current of the cell transistor. Therefore, the charge must be refreshed several times
each second.
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[2]
Figure 1. DRAM Cell
Active Pages:
Active Pages are another concept for relocating processing of instructions to the
memory. In contrast to the aforementioned approaches, Active Pages are based
on so-called RADram (Reconfigurable Architecture DRAM) which means, that the
logic functions integrated in the memory can be changed during the execution.
This gives the possibility to specifically adjust the logic to the requirements of an
executed program. The system is flexible, so the same hardware can be used for
more varying systems leading to lower costs. Another advantage is that Active
Pages integrates in normal systems by using the same interface as conventional
memory systems, hence, it is not replacing conventional architectures. Active
Page functions are invoked through memory-mapped writes. Synchronization is
accomplished through user-defined memory locations.
A special kind of connecting memory to a system of several processors exists in
the parallel sysplex architecture of IBM mainframe computers. The so-called
coupling facility is a central memory concurrently used from all subsystems. It
ensures the integrity and consistency of the data. This is achieved through a
special processor with attached memory, which is connected to all processing
elements of the sysplex configuration. [3]
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Figure 2. A simplified view of Active Pages. The additional processing logic is colored green, while
the logic and DRAM cells normally found in DRAM chips is colored blue. [1]
DIVA:
The DIVA (Data IntensiVe Architecture) Project has developed a prototype
workstation class system using VLSI PIM (Processor-In-Memory) chips as smart-
memory coprocessors to a conventional microprocessor. These chips represent the
first smart memory devices to support virtual addressing and be capable of
executing multiple threads of control. The DIVA PIM VLSI is fabricated in TSMC 0.18-
micron technology. The chip measures 9.8 mm on a side and contains 55 million
transistors.
The goals of the DIVA Project were to demonstrate the capabilities of PIM
technology as smart memory in a system:
1. Exploit the inherent memory bandwidth
embedded DRAM technology
2. Cover a broad range of applications:
irregular memory accesses (sparse-matrices & pointers)
image processing and multimedia (streaming computations)
3. Evolutionary application migration path
PIMs also support standard memory accesses
familiar parallel programming paradigm
4. Prototype a workstation-class system
VLSI PIM chips in standard memory modules
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System Architecture A driving principle of the DIVA system architecture is to efficiently
utilize PIM technology in a way that requires only “evolutionary” software support.
This principle demands an approach that enables integration of PIM features into
conventional systems as seamlessly as possible. Therefore, DIVA chips will be packaged
as conventional memory modules. Inserted onto a conventional microprocessor
motherboard, the memory on the DIVA chips is accessed by the host microprocessor as
if it were conventional memory.
In Figure 3, we show a small set of PIMs connected to a single external host processor
through a host-memory interface. The PIM chips communicate through separate PIM-
to-PIM channels.
Figure 3. DIVA system architecture
This separate memory-to-memory interconnect enables communication between
memories without involving the host processor. [4]
The MAUI Architecture:
Similar to the Active Pages and DIVA architectures, MAUI memory operations are
explicitly invoked by the host processor, meaning that the processor’s instruction set is
augmented to include MAUI instructions. The MAUI architecture performs vector
operations on arbitrary size vectors.
These computations include addition and multiplication of two vectors, scaling of a
single vector, and data movement. Other, more complicated operations could be
possible. However, other memory bound operations, such as pointer chasing,
searching, and sorting are not presented in this paper.
By providing the host processor with explicit control of specialized memory operations,
the MAUI architecture resembles both the Active Pages and DIVA architectures1.
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The placement of computational power within the memory controller decreases
latency and increases bandwidth to memory when compared to the host processor.
Additionally, the expression of massive Instruction Level Parallelism (ILP) allows for
more efficient access to memory and reduced cache overhead. By avoiding the
integration of processing logic and DRAM onto a single chip, the MAUI architecture is
made less expensive than the Active Pages, DIVA, and IRAM architectures by using
current processing technologies and conventional consumer DRAM chips.
The MAU:
The Active Pages project demonstrated that the performance gain in using intelligent
memory system architectures is due mostly to Instruction Level Parallelism (ILP). To
exploit available ILP, the MAUI architecture performs vector computations on vectors
as wide as a cacheline. With the SimpleScalar architecture, the MAU supports two
thirty-two byte vector operands. That means that the MAU performs eight integer
arithmetic operations in parallel.
Future possibilities for operations include searches, scatter-gather operations, pointer
chasing, or other memory access bound operations which express significant ILP.
As the MAU is located on the same chip as the memory controller, it is limited to the
same process technology, clock cycle, and power requirements as the memory
controller.
Fortunately, this limitation is mitigated by the fact that the MAU has a more efficient
connection to main memory than the host processor and the SIMD nature of the vector
operations it supports allows for significant exploitation of ILP.
The MAUI:
The MAUI controls memory computations and acts as the intelligent memory system’s
interface to the rest of the computer system. The MAUI the heart of the MAUI
intelligent memory system computational model. The MAUI coordinates its caches,
includes dedicated registers to hold the source and destination addresses, block size,
and other run time information, performs address computation, and issues read and
write requests to the DRAM system.
The MAUI is also responsible for supplying the MAU with vector operands from
memory. Lastly, the MAUI is responsible for ensuring the logical ordering of traditional
memory accesses and MAUI operations. While enforcing logical ordering, the MAUI
also allows non-MAUI memory operations to “leap-frog” long latency MAUI
instructions and complete before the MAUI instructions are finished. A block level
schematic of the MAUI architecture is shown in Figure 4.
Notice that all of the data flow in the MAUI architecture passes through the MAUI. [1]
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Figure 4. The block diagram of the MAUI architecture.
MAUI commands are divided into setup and execution commands. The setup
commands are used to load the source, destination, and size registers within the MAUI.
The source registers shown in Figure 2 are registers A and B. These registers hold the
beginning address of the source vectors. That means the source vectors occupy the
memory ranges of A to A+size−1 and from B to B+size−1. The beginning address for the
destination vector is held in the register C, meaning that the destination vector
occupies the memory range from C to C+size−1. The MAUI needs to be setup before
any execution command is issued.
Once the MAUI is setup with valid source and destination vectors, the processor may
issue a MAUI execution command. When the MAUI receives an execution command, it
begins the execution of that command. Generally, the MAUI begins the execution of
the command by issuing read requests to main memory. When the data comes back
from memory, it is stored in the MAUI cache until there are enough operands to
perform some arithmetic in the MAUI cache. Once the required operands have been
fetched from memory they are transferred to the MAU, which performs the actual
arithmetic. Then, the result from the MAU’s operation is sent back to memory with a
write request to main memory. As an example of how the MAUI coordinates the data
flow during the execution of a MAUI command, Figure 5 graphically details the
execution of a MAUI-ADD( ) command and how the data flows through the MAUI
architecture.
To maximize the performance of the MAUI augmented memory system, non-MAUI
memory operations are permitted to reorder with MAUI memory operations. However,
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the reordering cannot violate the logical ordering of memory operations and reorder
dependent memory operations.
To that end, one very important responsibility of the MAUI is to maintain the logical
ordering of memory commands while allowing subsequent, independent memory
operations to complete without waiting for the completion of the MAUI operation.
To maintain the logical ordering of traditional memory accesses and MAUI operations,
the MAUI architecture introduces the concept of locking memory. The MAUI maintains
two types of memory locks, Read and Write locks. A Read lock is placed on MAUI
source addresses, or those memory locations that the MAUI needs to read. A Write
lock is placed on MAUI destination addresses, or those memory locations that the
MAUI needs to write to. A Read lock prevents later memory operations from modifying
the data, but allows the data to be read by the host processor. A Write lock prevents
later memory operations from modifying or reading the data. So, the Read lock
prevents the processor from modifying data that the MAUI hardware has not read yet,
and the Write lock prevents the processor from reading stale data that the MAUI
hardware has not yet over-written.
To enforce correctness, the MAUI stalls those memory commands which violate either
the read or write locks. The MAUI rechecks stalled memory commands to see if they
can be executed each time the MAUI completes any operation.
When the MAUI is idle, memory commands are never artificially stalled. Because the
MAUI must be able to stall memory commands that are not MAUI commands, the
MAUI observes every command that enters the memory controller.
[1]
Figure 5. MAUI-ADD()
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References:
1- Teller J., Charles B. Silio, Jr., Jacob B., (2005). Performance Characteristics of
MAUI: An Intelligent Memory System Architecture, Chicago, USA.
2- Matas B., DeSubercausau C., (May, 1997). Memory, 1997: Complete Coverage of
DRAM, Sram, EPROM, and Flash Memory IC's, 15022 N. 75th Street Scottsdale,
AZ, United States.
3- Brinkschulte U., Ungerer T., Hochberger C., Spallker R. G.(Eds.), (February 2008).
Architecture of Computing Systems – ARCS 2008, Dresden, Germany.
4- Granacki J. J., Hall M., Draper J., LaCoss J., Chame J., Barrett T., Despain A.,
Gaudiot J., (June 2004). DIVA (DATA INTENSIVE ARCHITECTURE), Rome NY
13441-4505.
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