23/09/2016
BJT AC Analysis Chapter
9/23/2016 msa2016
BJT Transistor Modeling
• A model is an equivalent circuit that represents the AC
characteristics of the transistor.
• A model uses circuit elements that approximate the
behavior of the transistor.
• There are two models commonly used in small signal AC
analysis of a transistor:
– re model
9/23/2016 msa2016
1
23/09/2016
The re Transistor Model
• BJTs are basically current-controlled devices; therefore the re model
uses a diode and a current source to duplicate the behavior of the
transistor.
• One disadvantage to this model is its sensitivity to the DC level. This
model is designed for specific circuit conditions.
9/23/2016 msa2016
Common-Base Configuration
I c I e I e 1I b I b re
26 mV
Ie
Input impedance:
Z i re
Output impedance:
ro = output impedance for early
Z o ro voltage situtaion
Voltage gain:
R L RL
A V ( IoRL ) / Iere (IeRL ) / Iere When loadded
re re
with RL
Current gain:
A i 1
ro
9/23/2016 msa2016
2
23/09/2016
Common-Base Configuration
• The input is applied to the
emitter.
• The output is taken from the
collector.
• Low input impedance.
• High output impedance.
• Current gain less than unity.
• Very high voltage gain.
• No phase shift between input
and output.
9/23/2016 msa2016
Phase Relationship
Ii Ie Ic
e c Vo
Vi Io
Ic=Ie +
+ RE re RC vo t
t Vi ~
- ro
_
b
Zi Zo
AV has a positive sign, thus, Vi and Vo are in phase
If given the value of Vi , you can calculate Vo
9/23/2016 msa2016
3
23/09/2016
Calculations
Input impedance:
Z i R E || re
Output impedance:
Zo R C
Voltage gain:
Vo R C R C
Av
Vi re re
Current gain:
I
A i o 1
Ii
9/23/2016 msa2016
Example 1
4
23/09/2016
+VCC Effect Of RL and RS
+VCC
RC
vo Loaded RC
+VCC V
AVWL = o vo
Vi
vi
RC RL
RE
vo
Unloaded + RS RE
-VEE RL ~
vS -
Vo vi
AVNL = -VEE
Vi
RE Loaded with RS
Vo
-VEE AVs =
Vs with RL and Rs
For the same configuration,
AVNL > AVWL > AVs
The gain that results due to the application of a load or
source resistance can have a dramatic effect on all the
amplifier parameters
Two methods to analyze networks with an applied load
and/or source resistance:
re model
Two-port equivalent model
:: nuraa001::FKE::UTeM::
10
5
23/09/2016
With RL and RS
+VCC
RC
C2
vo
RL
C1
+ RS RE
~
vS -
CB Configuration (npn)
-VEE
:: nuraa001::FKE::UTeM::
11
re model
RS Ii Ie Ic
e c
+ Io
Ic=Ie +
+ Vi RE re RC RL V
~ ro o
VS - _ _
b
Zi Zo
You can simplify the model if
RE 10re OR ro 10RC
Determine re and ro from dc analysis
Impedance:
Zi = RE || re Zo = RC || ro
re RC ro 10RC
RE 10re
:: nuraa001::FKE::UTeM::
12
6
23/09/2016
Load resistance effect, Load and source resistance effect,
AVWL= Vo = Ie(RC||RL||ro) AVs = Vo = Vo Vi = AVWL Zi
X
Vi Vi Vs Vi Vs Zi+Rs
= IeRC||RL||ro = (RC||RL||ro) Zi
X
reIe re Zi+RS
= (RC||RL||ro)
re
Current gain,
Ai = Io 𝑉𝑜/𝑍𝑜 = AVWL Zi
=
𝑉𝑖/𝑍𝑖
Ii RL
:: nuraa001::FKE::UTeM::
13
Common-Emitter Configuration
The diode re model can be replaced by
the resistor re. Then the input side for Zi
is Vi /Ib
I e 1I b I b
Ic
26 mV
re βIb
Ie βre
more…
9/23/2016 msa2016
7
23/09/2016
Common-Emitter Configuration
Input impedance:
Z i re Ic
Output impedance:
Z o ro βIb
βre
Voltage gain:
RL
AV
re
Current gain:
A i ro
9/23/2016 msa2016
Common-Emitter Configuration
+VCC
+VCC
Fixed-Bias
RC
RB RC
vo RB
vo
vi
vi
+VCC
RE
CE
RC
R1
vo
Emitter-Bias (Unbypassed)
vi
Voltage-Divider Bias Emitter-Bias (Bypassed)
R2 RE
CE
:: nuraa001::FKE::UTeM::
16
8
23/09/2016
Common-Emitter Fixed-Bias
Configuration
• The input is applied to the base
• The output is from the collector
• High input impedance
• Low output impedance
• High voltage and current gain
• Phase shift between input and
output is 180
9/23/2016 msa2016
Common-Emitter Fixed-Bias
Configuration
AC equivalent
re model
9/23/2016 msa2016
9
23/09/2016
Common-Emitter Fixed-Bias Calculations
Input impedance:
Z i R B || re
Z i re R E 10 re
Output impedance:
Z o R C || rO
Z o R C ro 10R C
Voltage gain: Current gain:
V (R || r )
Av o C o I R B ro
Vi re Ai o
I i (ro R C )(R B re )
RC
Av ro 10R C
re A i ro 10RC , R B 10re
Current gain from voltage gain:
Zi
Ai A v
RC
9/23/2016 msa2016
Common-Emitter Voltage-Divider Bias
re model requires you to determine , re, and ro.
9/23/2016 msa2016
10
23/09/2016
Common-Emitter Voltage-Divider Bias
Calculations
Input impedance:
R R 1 || R 2
Z i R || re
Output impedance:
Z o R C || ro Current gain:
I R ro
Z o R C ro 10R C Ai o
I i (ro R C )(R re )
I R
Voltage gain: Ai o r 10R C
I i R re o
Vo R C || ro I
Av A i o ro 10R C , R 10 re
Vi re Ii
Vo R
Av C ro 10R C
Vi re Current gain from voltage gain:
Z
Ai A v i
RC
9/23/2016 msa2016
Common-Emitter Emitter-Bias
Configuration -Unbypassed
9/23/2016 msa2016
11
23/09/2016
Impedance Calculations
Input impedance:
Z i R B || Z b
Z b re ( 1)R E
Z b (re R E )
Z b R E
Output impedance:
Zo R C
9/23/2016 msa2016
Gain Calculations
Voltage gain:
Vo R C
Av
Vi Zb
Vo RC
Av
Vi re R E Z b (re R E )
Vo R
Av C Z b R E
Vi RE
Current gain: Current gain from voltage gain:
I R B Zi
Ai o Ai A v
Ii R B Zb RC
9/23/2016 msa2016
12
23/09/2016
Effect Of RL and RS
Impedance Calculation: Fixed Bias
Input impedance, Zi
Zi = RB || re
Output impedance, Zo
Zo = RC || ro
Ii RS Ib Ic Io
b c
+ + +
vs vi RB re ro RC RL vo
_ _ Ic=Ib _
e
Zi :: nuraa001::FKE::UTeM::
Zo 25
Gain Calculation
Without RL
Voltage gain, AVNL Voltage gain, AVs
Vo = -IoRC Vo = AVNL Vi
= - ro Ib Vs Vs
( )RC = AVNL Zi
RC + ro
Vi Zi+RS
= -ro (re) Current gain, Ai
(R + r )RC
C o Io = - AVNL Zi
Vo = -roRC Is RC
Vi re (RC + ro)
Ii RS Ib Ic Io
b c
+ +
+
ro RC vo
vs vi RB re RL
_ Ic=Ib _
_
e
:: nuraa001::FKE::UTeM::
Zi Zo 26
13
23/09/2016
With RL
Voltage gain, AVWL Voltage gain, AVs
Vo = -Ic (Zo||RL) Vo = AVWL Vi
= -Ib(Zo||RL) Vs Vs
= - Vi (Zo||RL) = AVWL Zi
re Zi+RS
Vo = - (Zo||RL) Current gain, Ai
Vi re Io = - AVWL Zi
Is RL
Ii RS Ib Ic Io
b c
+ +
+
vs RB re ro RC RL vo
vi
_ Ic=Ib _
_
e
Zi Zo
:: nuraa001::FKE::UTeM::
27
Simplified Equivalent Circuit
RB 10re OR ro 10RC
Ii RS Ib Ic Io
b c
+ +
+
RC RL vo
vs vi re
_ Ic=Ib _
_
e
Zi Zo
THUS,
Input impedance, Zi Voltage gain, AVNL
Zi = re Vo = -IoRC = -(-Ib) RC = Vi RC
re
Output impedance, Zo
AVNL = Vo = -RC
Zo = RC Vi re
:: nuraa001::FKE::UTeM::
28
14
23/09/2016
Simplified Equivalent Circuit
IF AND ONLY IF
RB 10re OR ro 10RC
Ii RS Ib Ic Io
b c
+ +
+
RC RL vo
vs vi re
_ Ic=Ib _
_
e
Zi Zo
AND,
Voltage gain, AVWL Current gain, Ai
Vo = -IoRL = -IbRCRL = - ViRCRL Io = RC = RC
RC+RL re (RC+RL) Ii RC+RL RC+RL
AVWL = Vo = -RCRL Ai = Io = -AVWLZi
Vi re (RC+RL) Ii RL
:: nuraa001::FKE::UTeM::
29
Emitter-Bias
(a)Bypassed
+VCC
RC
RB
vo
RS C2
vi
C1
RL
RE
CE
:: nuraa001::FKE::UTeM::
30
15
23/09/2016
re model
Ii RS Ib Ic Io
b c
+ + +
vs RB re ro RC RL vo
vi
_ _ Ic=Ib _
e
Zi Zo
The re model of this configuration is THE SAME with CE
fixed-bias configuration.
:: nuraa001::FKE::UTeM::
31
Emitter-Bias with Rs and RL
(b)Unbypassed
+VCC
RC
RB
vo
RS C2
vi
C1
RL
RE
:: nuraa001::FKE::UTeM::
32
16
23/09/2016
re model
Approximate
Ii RS Ib c Ic Io analysis
b
+
(ignore ro)
+ + Ic=Ib
re ro
vs vi RB RC RL
Vi Vi
e vo = = re+RE
RE Ie (+1)Ib
_ _ _
Zi Zo
Ii RS Ib Ic Io
b c
Zb
Vi
= (+1)(re+RE) + + +
Ib vs (re+RE) RC RL vo
vi RB
(re +RE) _ Ic=Ib _
_
Zi e Zo
:: nuraa001::FKE::UTeM::
Go to Fixed-Bias 33
Ii RS Ib Ic Io
b c
+ +
+ (re+RE)
vs RB RC RL vo
vi
_ _ Ic=Ib _
Zi e Zo
Input impedance, Zi
Zi = RB||(RE+ re)
Output impedance, Zo
Zo = RC
No-Load Voltage Gain, AVNL
AVNL = -RC
Find AVWL, AVs
and Ai
RE+re
:: nuraa001::FKE::UTeM::
34
17