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TPS51216-EP
SLUSCA7 – NOVEMBER 2015

TPS51216-EP Complete DDR2, DDR3 and DDR3L Memory Power Solution Synchronous
Buck Controller, 2-A LDO, Buffered Reference
1 Features 2 Applications
1• Synchronous Buck Controller (VDDQ) • DDR2/DDR3/DDR3L Memory Power Supplies
– Conversion Voltage Range: 3 to 28 V • SSTL_18, SSTL_15, SSTL_135, and HSTL
– Output Voltage Range: 0.7 to 1.8 V Termination
– 0.8% VREF Accuracy
3 Description
– D-CAP™ Mode for Fast Transient Response
The TPS51216-EP provides a complete power supply
– Selectable 300-kHz/400-kHz Switching for DDR2, DDR3 and DDR3L memory systems in the
Frequencies lowest total cost and minimum space. It integrates a
– Optimized Efficiency at Light and Heavy Loads synchronous buck regulator controller (VDDQ) with a
With Auto-Skip Function 2-A sink/source tracking LDO (VTT) and buffered low
noise reference (VTTREF). The TPS51216-EP
– Supports Soft-Off in S4/S5 States employs D-CAP™ mode coupled with 300 kHz/400
– OCL/OVP/UVP/UVLO Protections kHz frequencies for ease-of-use and fast transient
– Powergood Output response. The VTTREF tracks VDDQ/2 within
excellent 0.8% accuracy. The VTT, which provides 2-
• 2-A LDO (VTT), Buffered Reference (VTTREF)
A sink/source peak current capabilities, requires only
– 2-A (Peak) Sink and Source Current 10-μF of ceramic capacitance. In addition, a
– Requires Only 10-μF of Ceramic Output dedicated LDO supply input is available.
Capacitance The TPS51216-EP provides rich useful functions as
– Buffered, Low Noise, 10-mA VTTREF Output well as excellent power supply performance. It
– 0.8% VTTREF, 20-mV VTT Accuracy supports flexible power state control, placing VTT at
high-Z in S3 and discharging VDDQ, VTT, and
– Support High-Z in S3 and Soft-Off in S4/S5 VTTREF (soft-off) in S4/S5 state.
• Thermal Shutdown
• 20-Pin, 3 mm × 3 mm, WQFN Package Device Information(1)
• Supports Defense, Aerospace, and Medical PART NUMBER PACKAGE BODY SIZE (NOM)
Applications TPS51216-EP WQFN (20) 3.00 mm × 3.00 mm

– Controlled Baseline (1) For all available packages, see the orderable addendum at
the end of the data sheet.
– One Assembly/Test Site
– One Fabrication Site Application Diagram
– Available in Military (–55°C to 125°C) VIN

Temperature Range (1)

5VIN
– Extended Product Life Cycle TPS51216
PGND VBST 15
12 V5IN
– Extended Product-Change Notification VDDQ
DRVH 14
– Product Traceability S3 17 S3
SW 13
S5 16 S5
PGND
DRVL 11
6 VREF PGND 10

PGOOD 20 Powergood
8 REFIN VDDQSNS 9

VLDOIN 2
7 GND VTT 3 VTT

19 MODE VTTSNS 1

18 TRIP
VTTGND 4

VTTREF 5 VTTREF PGND

AGND
AGND UDG-10138
(1)
1
Additional temperature ranges available - contact factory

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.3 Feature Description................................................. 15
2 Applications ........................................................... 1 8.4 Device Functional Modes........................................ 17
3 Description ............................................................. 1 9 Application and Implementation ........................ 18
4 Revision History..................................................... 2 9.1 Application Information............................................ 18
9.2 Typical Application ................................................. 21
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 23
7 Specifications......................................................... 4 11 Layout................................................................... 24
11.1 Layout Guidelines ................................................. 24
7.1 Absolute Maximum Ratings ...................................... 4
11.2 Layout Example .................................................... 25
7.2 ESD Ratings.............................................................. 4
7.3 Recommended Operating Conditions....................... 5 12 Device and Documentation Support ................. 26
7.4 Thermal Information .................................................. 5 12.1 Community Resources.......................................... 26
7.5 Electrical Characteristics........................................... 6 12.2 Trademarks ........................................................... 26
7.6 Typical Characteristics .............................................. 8 12.3 Electrostatic Discharge Caution ............................ 26
12.4 Glossary ................................................................ 26
8 Detailed Description ............................................ 14
8.1 Overview ................................................................. 14 13 Mechanical, Packaging, and Orderable
8.2 Functional Block Diagram ....................................... 14
Information ........................................................... 26

4 Revision History
DATE REVISION NOTES
November 2015 * Initial release.

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5 Description (continued)
Programmable OCL with low-side MOSFET RDS(on) sensing, OVP/UVP/UVLO and thermal shutdown protections
are also available.
The TPS51216-EP is available in a 20-pin, 3 mm × 3 mm, WQFN package and is specified for junction
temperature from –55°C to 125°C.

6 Pin Configuration and Functions

RUK Package
20-Pin WQFN
Top View

PGOOD

MODE

TRIP

S3

S5
20 19 18 17 16

VTTSNS 1 15 VBST

VLDOIN 2 14 DRVH

VTT 3 Thermal Pad 13 SW

VTTGND 4 12 V5IN

VTTREF 5 11 DRVL

6 7 8 9 10
PGND
VREF

GND

REFIN

VDDQSNS

Pin Functions
PIN
I/O DESCRIPTION
NAME NO.
DRVH 14 O High-side MOSFET gate driver output.
DRVL 11 O Low-side MOSFET gate driver output.
GND 7 — Signal ground.
MODE 19 I Connect resistor to GND to configure switching frequency and discharge mode. (See Table 2.)
PGND 10 — Gate driver power ground. RDS(on) current sensing input (+).
PGOOD 20 O Powergood signal open drain output. PGOOD goes high when VDDQ output voltage is within the target range.
Reference input for VDDQ. Connect to the midpoint of a resistor divider from VREF to GND. Add a capacitor for
REFIN 8 I
stable operation.
SW 13 I/O High-side MOSFET gate driver return. RDS(on) current sensing input (–).
S3 17 I S3 signal input. (See Table 1.)
S5 16 I S5 signal input. (See Table 1.)
TRIP 18 I Connect resistor to GND to set OCL at VTRIP / 8. Output 10-μA current at room temperature, TC = 4700 ppm/°C.
VBST 15 I High-side MOSFET gate driver bootstrap voltage input. Connect a capacitor from the VBST pin to the SW pin.
VDDQSNS 9 I VDDQ output voltage feedback. Reference input for VTTREF. Also serves as power supply for VTTREF.
VLDOIN 2 I Power supply input for VTT LDO. Connect VDDQ in typical application.
VREF 6 O 1.8-V reference output.
VTT 3 O VTT 2-A LDO output. Need to connect 10 μF or larger capacitance for stability.
VTTGND 4 — Power ground for VTT LDO.

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Pin Functions (continued)

PIN
I/O DESCRIPTION
NAME NO.
VTTREF 5 O Buffered VTT reference output. Need to connect 0.22 μF or larger capacitance for stability.
VTTSNS 1 I VTT output voltage feedback.
V5IN 12 I 5-V power supply input for internal circuits and MOSFET gate drivers.
Thermal
— — Connect to GND
pad

7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VBST –0.3 36
VBST (3) –0.3 6
SW –5 30
Input voltage (2) VLDOIN, VDDQSNS, REFIN –0.3 3.6 V
VTTSNS –0.3 3.6
PGND, VTTGND –0.3 0.3
V5IN, S3, S5, TRIP, MODE –0.3 6
DRVH –5 36
DRVH (3) –0.3 6
DRVH (3) (duty cycle < 1%) –2.5 6
VTTREF, VREF –0.3 3.6
Output voltage (2) V
VTT –0.3 3.6
DRVL –0.3 6
DRVL (duty cycle < 1%) –2.5 6
PGOOD –0.3 6
Junction temperature, TJ –55 135 °C
Storage temperature, Tstg –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to the network ground terminal unless otherwise noted.
(3) Voltage values are with respect to the SW terminal.

7.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) ±2000
V(ESD) Electrostatic discharge Charged-device model (CDM), per JEDEC specification JESD22- V
±500
C101 (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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7.3 Recommended Operating Conditions

MIN NOM MAX UNIT
Supply voltage V5IN 4.5 5.5 V
VBST –0.1 33.5
VBST (1) –0.1 5.5
SW -3 28
SW (2) –4.5 28
Input voltage range V
VLDOIN, VDDQSNS, REFIN –0.1 3.5
VTTSNS –0.1 3.5
PGND, VTTGND –0.1 0.1
S3, S5, TRIP, MODE –0.1 5.5
DRVH –3 33.5
DRVH (1) –0.1 5.5
DRVH (2) –4.5 33.5
Output voltage range VTTREF, VREF –0.1 3.5 V
VTT –0.1 3.5
DRVL –0.1 5.5
PGOOD –0.1 5.5
TJ Operating junction temperature –55 125 °C

(1) Voltage values are with respect to the SW terminal.

(2) This voltage should be applied for less than 30% of the repetitive period.

7.4 Thermal Information

TPS51216-EP
THERMAL METRIC (1) RUK (WQFN) UNIT
20 PINS
RθJA Junction-to-ambient thermal resistance 94.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 58.1 °C/W
RθJB Junction-to-board thermal resistance 64.3 °C/W
ψJT Junction-to-top characterization parameter 31.8 °C/W
ψJB Junction-to-board characterization parameter 58.0 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 5.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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7.5 Electrical Characteristics

TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
SUPPLY CURRENT
IV5IN(S0) V5IN supply current, in S0 TJ = 25°C, No load, VS3 = VS5 = 5 V 590 μA
IV5IN(S3) V5IN supply current, in S3 TJ = 25°C, No load, VS3 = 0 V, VS5 = 5 V 500 μA
IV5INSDN V5IN shutdown current TJ = 25°C, No load, VS3 = VS5 = 0 V 1 μA
IVLDOIN(S0) VLDOIN supply current, in S0 TJ = 25°C, No load, VS3 = VS5 = 5 V 5 μA
IVLDOIN(S3) VLDOIN supply current, in S3 TJ = 25°C, No load, VS3 = 0 V, VS5 = 5 V 5 μA
IVLDOINSDN VLDOIN shutdown current TJ = 25°C, No load, VS3 = VS5 = 0 V 5 μA
VREF OUTPUT
IVREF = 30 μA, TJ = 25°C 1.8000
VVREF Output voltage V
0 μA ≤ IVREF <300 μA, TJ = –55°C to 125°C 1.7820 1.8180
IVREFOCL Current limit VVREF = 1.7 V 0.4 0.8 mA
VTTREF OUTPUT
VVTTREF Output voltage VVDDQSNS/2 V
|IVTTREF| <100 μA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V 49.2% 50.8%
VVTTREF Output voltage tolerance to VVDDQ
|IVTTREF| <10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V 49% 51%
IVTTREFOCLSRC Source current limit VVDDQSNS = 1.8 V, VVTTREF= 0 V 10 18 mA
IVTTREFOCLSNK Sink current limit VVDDQSNS = 1.8 V, VVTTREF = 1.8 V 10 17 mA
IVTTREFDIS VTTREF discharge current TJ = 25°C, VS3 = VS5 = 0 V, VVTTREF = 0.5 V 0.8 1.3 mA
VTT OUTPUT
VVTT Output voltage VVTTREF V
|IVTT| ≤ 10 mA, 1.2 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF = 0 A –20 20
|IVTT| ≤ 1 A, 1.2 ≤ VVDDQSNS ≤ 1.8 V, IVTTREF = 0 A –30 30
VVTTTOL Output voltage tolerance to VTTREF mV
|IVTT| ≤ 2 A, 1.4 V ≤ VVDDQSNS ≤ 1.8 V, IVTTREF = 0 A –40 40
|IVTT| ≤ 1.5 A, 1.2 V ≤ VVDDQSNS ≤ 1.4 V, IVTTREF = 0 A –40 40
VVDDQSNS = 1.8 V, VVTT = VVTTSNS = 0.7 V,
IVTTOCLSRC Source current limit 2 3
IVTTREF = 0 A
A
VVDDQSNS = 1.8V, VVTT = VVTTSNS = 1.1 V, IVTTREF = 0
IVTTOCLSNK Sink current limit 2 3
A
IVTTLK Leakage current TJ = 25°C , VS3 = 0 V, VS5 = 5 V, VVTT = VVTTREF 5
IVTTSNSBIAS VTTSNS input bias current VS3 = 5 V, VS5 = 5 V, VVTTSNS = VVTTREF –0.5 0.0 0.5 μA
IVTTSNSLK VTTSNS leakage current VS3 = 0 V, VS5 = 5 V, VVTTSNS = VVTTREF –1 0 1
TJ = 25°C, VS3 = VS5 = 0 V, VVDDQSNS = 1.8 V,
IVTTDIS VTT Discharge current 7.8 mA
VVTT = 0.5 V, IVTTREF = 0 A
VDDQ OUTPUT
VVDDQSNS VDDQ sense voltage VREFIN
VDDQSNS regulation voltage
VVDDQSNSTOL TJ = 25°C –3 3 mV
tolerance to REFIN
IVDDQSNS VDDQSNS input current VVDDQSNS = 1.8 V 39 μA
IREFIN REFIN input current VREFIN = 1.8 V –0.1 0.0 0.1 μA
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled
IVDDQDIS VDDQ discharge current 12 mA
down to GND through 47 kΩ (Non-tracking)
VS3 = VS5 = 0 V, VVDDQSNS = 0.5 V, MODE pin pulled
IVLDOINDIS VLDOIN discharge current 1.2 A
down to GND through 100 kΩ (Non-tracking)
SWITCH MODE POWER SUPPLY (SMPS) FREQUENCY
VIN = 5 V, VVDDQSNS = 1.8 V, RMODE = 100 kΩ 300
ƒSW VDDQ switching frequency kHz
VIN = 5 V, VVDDQSNS = 1.8 V, RMODE = 200 kΩ 400
tON(min) Minimum on time DRVH rising to falling (1) 60
ns
tOFF(min) Minimum off time DRVH falling to rising 200 320 450

(1) Ensured by design. Not production tested.

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Electrical Characteristics (continued)

TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
VDDQ MOSFET DRIVER
Source, IDRVH = –50 mA 1.6 3.0
RDRVH DRVH resistance
Sink, IDRVH = 50 mA 0.6 1.5
Ω
Source, IDRVL = –50 mA 0.9 2.0
RDRVL DRVL resistance
Sink, IDRVL = 50 mA 0.5 1.2
DRVH-off to DRVL-on 10
tDEAD Dead time ns
DRVL-off to DRVH-on 20
INTERNAL BOOT STRAP SW
VFBST Forward voltage VV5IN-VBST, TJ = 25°C, IF = 10 mA 0.1 0.2 V
IVBSTLK VBST leakage current TJ = 25°C, VVBST = 33 V, VSW = 28 V 0.01 1.5 μA
LOGIC THRESHOLD
IMODE MODE source current 14 15 16 μA
MODE 0 580 600 620
MODE 1 829 854 879
VTHMODE MODE threshold voltage mV
MODE 2 1202 1232 1262
MODE 3 1760 1800 1840
VIL S3/S5 low-level voltage 0.5
VIH S3/S5 high-level voltage 1.8 V
VIHYST S3/S5 hysteresis voltage 0.25
VILK S3/S5 input leak current –1 0 1 μA
SOFT START
Internal soft-start time, CVREF = 0.1 μF,
tSS VDDQ soft-start time 1.1 ms
S5 rising to VVDDQSNS > 0.99 × VREFIN
PGOOD COMPARATOR
PGOOD in from higher 106% 108% 110%
PGOOD in from lower 90% 92% 94%
VTHPG VDDQ PGOOD threshold
PGOOD out to higher 114% 116% 118%
PGOOD out to lower 82% 84% 86%
IPG PGOOD sink current VPGOOD = 0.5 V 3 5.9 mA
Delay for PGOOD in 0.8 1 1.2 ms
tPGDLY PGOOD delay time
Delay for PGOOD out, with 100 mV over drive 330 ns
tPGSSDLY PGOOD start-up delay CVREF = 0.1 μF, S5 rising to PGOOD rising 2.5 ms
PROTECTIONS
ITRIP TRIP source current TJ = 25°C, VTRIP = 0.4 V 9 10 11 μA
TRIP source current temperature
TCITRIP 4700 ppm/°C
coefficient (1)
VTRIP VTRIP voltage range 0.2 3 V
VTRIP = 3.0 V 360 375 390
VOCL Current limit threshold VTRIP = 1.6 V 190 200 210 mV
VTRIP = 0.2 V 20 25 30
VTRIP = 3.0 V –390 –375 –360
VOCLN Negative current limit threshold VTRIP = 1.6 V –210 –200 –190 mV
VTRIP = 0.2 V –30 –25 –20
VZC Zero cross detection offset 0 mV
Wake-up 4.2 4.4 4.5
VUVLO V5IN UVLO threshold voltage V
Shutdown 3.7 3.9 4.1
VOVP VDDQ OVP threshold voltage OVP detect voltage 118% 120% 122%
tOVPDLY VDDQ OVP propagation delay With 100 mV over drive 430 ns
VUVP VDDQ UVP threshold voltage UVP detect voltage 66% 68% 70%
tUVPDLY VDDQ UVP delay 1 ms

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Electrical Characteristics (continued)

TJ = –55°C to 125°C, VV5IN = 5 V, VLDOIN is connected to VDDQ output, VMODE = 0 V, VS3 = VS5 = 5 V (unless otherwise
noted)
PARAMETER TEST CONDITION MIN TYP MAX UNIT
tUVPENDLY VDDQ UVP enable delay 1.2 ms
VOOB OOB threshold voltage 108%
THERMAL SHUTDOWN
Shutdown temperature (1) 140
TSDN Thermal shutdown threshold °C
Hysteresis (1) 10

1M
Electromigration fail mode

100k
E s tim a te d L ife ( h o u r s )

10k

1k

100
80 90 100 110 120 130 140 150 160
Continuous Junction Temperature (°C)
D008

(1) See data sheet for absolute maximum and minimum recommended operating conditions.
(2) Silicon operating life design goal is 10 years at 105°C junction temperature (does not include package interconnect
life).
(3) Enhanced plastic product disclaimer applies.

Figure 1. TPS51216-EP Derating Chart

7.6 Typical Characteristics

1000 10
V5IN Shutdown Current (µA)

800 8
V5IN Suppy Current (µA)

600 6

400 4

200 2

0 0
-55 -25 5 35 65 95 125 -55 -25 5 35 65 95 125
Junction Temperature (°C) D001
Junction Temperature (°C) D002
Figure 2. V5IN Supply Current vs Junction Temperature Figure 3. V5IN Shutdown Current vs Junction Temperature

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Typical Characteristics (continued)

10 16

14
VLDOIN Suppy Current (µA)

TRIP Source Current (µA)

12
6
10
4
8

2
6

0 4
-55 -25 5 35 65 95 125 -55 -25 5 35 65 95 125
Junction Temperature (°C) D003
Junction Temperature (°C) D004
Figure 4. VLDOIN Supply Current vs Junction Temperature Figure 5. Current Sense Current vs Junction Temperature
150% 15
UVP
140%

VDDQSNS Discharge Current (mA)

OVP
130% 12
OVP/UVP Threshold

120%
110% 9
100%
90% 6
80%
70% 3
60%
50% 0
-55 -25 5 35 65 95 125 -55 -25 5 35 65 95 125
Junction Temperature (°C) D005
Junction Temperature (°C) D006
Figure 6. OVP/UVP Threshold vs Junction Temperature Figure 7. VDDQSNS Discharge Current vs Junction
Temperature
10 800
RMODE = 100 kΩ VVDDQ = 1.20 V
IVDDQ = 10 A VVDDQ = 1.35 V
700 VVDDQ = 1.50 V
VTT Discharge Current (mA)

8
Switching Frequency (kHz)

600
6
500
4
400

2
300

0 200
-55 -25 5 35 65 95 125 6 8 10 12 14 16 18 20 22
Junction Temperature (°C) D007
Input Voltage (V)
Figure 8. VTT Discharge Current vs Junction Temperature Figure 9. Switching Frequency vs Input Voltage

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Typical Characteristics (continued)

800 800
RMODE = 200 kΩ VVDDQ = 1.20 V RMODE = 100 kΩ VVDDQ = 1.20 V
IVDDQ = 10 A VVDDQ = 1.35 V 700 VIN = 12 V VVDDQ = 1.35 V
700 VVDDQ = 1.50 V VVDDQ = 1.50 V
Switching Frequency (kHz)

Switching Frequency (kHz)

600
600
500

500 400

300
400
200
300
100

200 0
6 8 10 12 14 16 18 20 22 0 2 4 6 8 10 12 14 16 18 20
Input Voltage (V) VDDQ Output Current (A)
Figure 10. Switching Frequency vs Input Voltage Figure 11. Switching Frequency vs Load Current
800 1.55
RMODE = 200 kΩ VVDDQ = 1.20 V RMODE = 200 kΩ
700 VIN = 12 V VVDDQ = 1.35 V 1.54 VIN = 12 V
VVDDQ = 1.50 V 1.53
Switching Frequency (kHz)

VDDQ Output Voltage (V)

600
1.52
500 1.51
400 1.50

300 1.49
1.48
200
1.47
100 1.46
0 1.45
0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20
VDDQ Output Current (A) VDDQ Output Current (A)
Figure 12. Switching Frequency vs Load Current Figure 13. Load Regulation
1.55 0.770
RMODE = 200 kΩ IVDDQ = 0 A
1.54 IVDDQ = 20 A 0.765
1.53
VDDQ Output Voltage (V)

0.760
VTTREF Voltage (V)

1.52
1.51 0.755

1.50 0.750
1.49 0.745
1.48
0.740
1.47
1.46 0.735
VVDDQ = 1.5 V
1.45 0.730
6 8 10 12 14 16 18 20 22 −10 −5 0 5 10
Input Voltage (V) VTTREF Current (mA)
Figure 14. Line Regulation Figure 15. VTTREF Load Regulation

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Typical Characteristics (continued)

0.695 0.620

0.690 0.615
0.685
0.610
VTTREF Voltage (V)

VTTREF Voltage (V)

0.680
0.605
0.675
0.600
0.670
0.595
0.665
0.590
0.660

0.655 0.585
VVDDQ = 1.35 V VVDDQ = 1.2 V
0.650 0.580
−10 −5 0 5 10 −10 −5 0 5 10
VTTREF Current (mA) VTTREF Current (mA)
Figure 16. VTTREF Load Regulation Figure 17. VTTREF Load Regulation
0.790 0.715

0.780 0.705

0.770 0.695
VTT Voltage (V)

VTT Voltage (V)

0.760 0.685

0.750 0.675

0.740 0.665

0.730 0.655

0.720 0.645
VVDDQ = 1.5 V VVDDQ = 1.35 V
0.710 0.635
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 −2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0
VTT Current (V) VTT Current (V)
Figure 18. VTT Load Regulation Figure 19. VTT Load Regulation
0.640 100

0.630 90
80
0.620
70
VTT Voltage (V)

Efficiency (%)

0.610 60
0.600 50

0.590 40
30
0.580
20 VIN = 20 V
0.570 VVDDQ = 1.5 V VIN = 12 V
10
VVDDQ = 1.2 V RMODE = 200 kΩ VIN = 8 V
0.560 0
−2.0 −1.5 −1.0 −0.5 0.0 0.5 1.0 1.5 2.0 0.001 0.01 0.1 1 10 100
VTT Current (V) VDDQ Output Current (A)
Figure 20. VTT Load Regulation Figure 21. Efficiency

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Typical Characteristics (continued)

Figure 22. 1.5-V Load Transient Response Figure 23. VTT Load Transient Response

Figure 24. 1.5-V Startup Waveforms Figure 25. 1.5-V Startup Waveforms (0.5-V Pre-Biased)

Figure 26. 1.5-V Soft-Stop Waveforms (Tracking Discharge) Figure 27. 1.5-V Soft-Stop Waveforms (Non-Tracking
Discharge)

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Typical Characteristics (continued)

80 180 80 180

60 135 60 135

40 90 40 90

20 45 20 45
Gain (dB)

Gain (dB)
Phase (°)

Phase (°)
0 0 0 0

−20 −45 −20 −45

−40 −90 −40 −90

−60 Gain −135 −60 Gain −135

IVTT = −1 A Phase IVTT = 1 A Phase
−80 −180 −80 −180
10000 100000 1000000 10000000 10000 100000 1000000 10000000
Frequency (Hz) Frequency (Hz)
Figure 28. VTT Bode Plot (Sink) Figure 29. VTT Bode Plot (Source)

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8 Detailed Description
8.1 Overview
TPS51216-EP provides complete Power Supply Solution for DDR2, DDR3 and DDR3L memory system.

8.2 Functional Block Diagram

+ UV VREFIN +8/16 % + 20 PGOOD

VREFIN –32%

Delay
+ OV +
VREFIN +20% VREFIN –8/16 %

15 mA
REFIN 8 UVP Control Logic
On-Time
OVP Discharge Type 19 MODE
VREF 6 Reference Selection
PWM
+
Soft-Start + 15 VBST

VDDQSNS 9 14 DRVH

10 mA 13 SW
8R

TRIP 18 + OC XCON
+
tON
S5 16 R
7R One-
Shot
S3 17
NOC
+
GND 7 12 V5IN
R
+ 11 DRVL
ZC

VDDQ VTT Discharge

Discharge V5OK VTTREF Discharge

10 PGND
VTTREF 5
+ 2 VLDOIN

+
4.4 V/3.9 V
+
+
3 VTT

VTTSNS 1

+
4 VTTGND
TPS51216
UDG-10135

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8.3 Feature Description

8.3.1 VDDQ Switch Mode Power Supply Control
TPS51216-EP supports D-CAP mode which does not require complex external compensation networks and is
suitable for designs with small external components counts. The D-CAP mode provides fast transient response
with appropriate amount of equivalent series resistance (ESR) on the output capacitors. An adaptive on-time
control scheme is used to achieve pseudo-constant frequency. The TPS51216-EP adjusts the on-time (tON) to be
inversely proportional to the input voltage (VIN) and proportional to the output voltage (VDDQ). This makes a
switching frequency fairy constant over the variation of input voltage at the steady state condition.

8.3.2 VREF and REFIN, VDDQ Output Voltage

The part provides a 1.8-V, ±0.8% accurate, voltage reference from VREF. This output has a 300-μA (max)
current capability to drive the REFIN input voltage through a voltage divider circuit. A capacitor with a value of
0.1-μF or larger should be attached close to the VREF terminal.
The VDDQ switch-mode power supply (SMPS) output voltage is defined by REFIN voltage, within the range
between 0.7 V and 1.8 V, programmed by the resister-divider connected between VREF and GND. (See External
Components Selection.) A few nano farads of capacitance from REFIN to GND is recommended for stable
operation.

8.3.3 Soft-Start and Powergood

TPS51216-EP provides integrated VDDQ soft-start functions to suppress in-rush current at start-up. The soft-
start is achieved by controlling internal reference voltage ramping up. Figure 30 shows the start-up waveforms.
The switching regulator waits for 400μs after S5 assertion. The MODE pin voltage is read in this period. A typical
VDDQ ramp up duration is 700μs.
TPS51216-EP has a powergood open-drain output that indicates the VDDQ voltage is within the target range.
The target voltage window and transition delay times of the PGOOD comparator are ±8% (typ) and 1-ms delay
for assertion (low to high), and ±16% (typ) and 330-ns delay for de-assertion (high to low) during running. The
PGOOD comparator is enabled 1.1 ms after VREF is raised high and the start-up delay is 2.5 ms. Note that the
time constant which is composed of the REFIN capacitor and a resistor divider needs to be short enough to
reach the target value before PGOOD comparator enabled.

S5

VREF

VDDQ

PGOOD

400 ms 700 ms 1.4 ms

UDG-10137

Figure 30. Typical Start-up Waveforms

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Feature Description (continued)

8.3.4 Power State Control
The TPS51216-EP has two input pins, S3 and S5, to provide simple control scheme of power state. All of VDDQ,
VTTREF and VTT are turned on at S0 state (S3 = S5 = high). In S3 state (S3 = low, S5 = high), VDDQ and
VTTREF voltages are kept on while VTT is turned off and left at high impedance state (high-Z). The VTT output
floats and does not sink or source current in this state. In S4/S5 states (S3=S5=low), all of the three outputs are
turned off and discharged to GND according to the discharge mode selected by MODE pin. Each state code
represents as follow; S0 = full ON, S3 = suspend to RAM (STR), S4 = suspend to disk (STD), S5 = soft OFF.
(See Table 1)

Table 1. S3/S5 Power State Control

STATE S3 S5 VREF VDDQ VTTREF VTT
S0 HI HI ON ON ON ON
S3 LO HI ON ON ON OFF (high-Z)
S4/S5 LO LO OFF OFF (discharge) OFF (discharge) OFF (discharge)

8.3.5 Discharge Control

In S4/S5 state, VDDQ, VTT, and VTTREF outputs are discharged based on the respective discharge mode
selected above. The tracking discharge mode discharges VDDQ output through the internal VTT regulator
transistors enabling quick discharge operation. The VTT output maintains tracking of the VTTREF voltage in this
mode. (Refer to Figure 26.) After 4 ms of tracking discharge operation, the mode changes to non-tracking
discharge. The VDDQ output must be connected to the VLDOIN pin in this mode. The non-tracking mode
discharges the VDDQ and VTT pins using internal MOSFETs that are connected to corresponding output
terminals. The non-tracking discharge is slow compared with the tracking discharge due to the lower current
capability of these MOSFETs. (Refer to Figure 27.)

8.3.6 VTT Overcurrent Protection

The LDO has an internally fixed constant overcurrent limiting of 3-A (typ) for both sink and source operation.

8.3.7 V5IN Undervoltage Lockout (UVLO) Protection

TPS51216-EP has a 5-V supply UVLO protection threshold. When the V5IN voltage is lower than UVLO
threshold voltage, typically 3.93 V, VDDQ, VTT, and VTTREF are shut off. This is a non-latch protection.

8.3.8 Thermal Shutdown

TPS51216-EP includes an internal temperature monitor. If the temperature exceeds the threshold value, 140°C
(typical), VDDQ, VTT and VTTREF are shut off. The thermal shutdown state of VDDQ is open, VTT and
VTTREF are high impedance (high-Z) respectively, and the discharge functions are disabled. This is a non-latch
protection and the operation is restarted with soft-start sequence when the device temperature is reduced by
10°C (typical).

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8.4 Device Functional Modes

8.4.1 MODE Pin Configuration
The TPS51216-EP reads the MODE pin voltage when the S5 signal is raised high and stores the status in a
register. A 15-μA current is sourced from the MODE pin during this time to read the voltage across the resistor
connected between the pin and GND. Table 2 shows resistor values, corresponding switching frequency, and
discharge mode configurations.

Table 2. MODE Selection

RESISTANCE BETWEEN SWITCHING
MODE NO. DISCHARGE MODE
MODE AND GND (kΩ) FREQUENCY (kHz)
3 200 400
Tracking
2 100 300
1 68 300
Non-tracking
0 47 400

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

TPS51216-EP is highly integrated synchronous step-down buck solution. The device is used to convert a higher
DC-DC voltage to lower DC output voltage to provide VDDQ and VTT for various DDR memory power solutions.

9.1.1 D-CAP Mode

Figure 31 shows a simplified model of D-CAP mode architecture.

VIN

VDDQSNS
DRVH High-Side
9 MOSFET
14
PWM Lx
REFIN + VDDQ
Control
8 Logic
and ESR RLOAD
R1 VREF Driver
6 DRVL Low-Side
+ MOSFET COUT
1.8 V 11
R2

UDG-10136

Figure 31. Simplified D-CAP Model

The VDDQSNS voltage is compared with REFIN voltage. The PWM comparator creates a set signal to turn on
the high-side MOSFET. The gain and speed of the comparator is high enough to maintain the voltage at the
beginning of each on-cycle (or the end of each off-cycle) to be substantially constant. The DC output voltage
monitored at VDDQ may have line regulation due to ripple amplitude that slightly increases as the input voltage
increase. The D-CAP mode offers flexibility on output inductance and capacitance selections and provides ease-
of-use with a low external component count. However, it requires a sufficient amount of output ripple voltage for
stable operation and good jitter performance.
The requirement for loop stability is simple and is described in Equation 1. The 0-dB frequency, ƒ0 defined in
Equation 1, is recommended to be lower than 1/3 of the switching frequency to secure proper phase margin.
1 f
f0 = £ SW
2p ´ ESR ´ COUT 3

where
• ESR is the effective series resistance of the output capacitor
• COUT is the capacitance of the output capacitor
• ƒsw is switching frequency (1)
Jitter is another attribute caused by signal-to-noise ratio of the feedback signal. One of the major factors that
determine jitter performance in D-CAP mode is the down-slope angle of the VDDQSNS ripple voltage. Figure 32
shows, in the same noise condition, a jitter is improved by making the slope angle larger.

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Application Information (continued)

VVDDQSNS
Slope (1)
Jitter

(2)
Slope (2)
Jitter
20 mV

(1)

VREFIN

VREFIN +Noise

tON tOFF UDG-10139

Figure 32. Ripple Voltage Slope and Jitter Performance

For a good jitter performance, use the recommended down slope of approximately 20 mV per switching period as
shown in Figure 32 and Equation 2.
VOUT ´ ESR
³ 20mV
fSW ´ L X

where
• VOUT is the VDDQ output voltage
• LX is the inductance (2)

9.1.2 Light-Load Operation

In auto-skip mode, the TPS51216-EP SMPS control logic automatically reduces its switching frequency to
improve light-load efficiency. To achieve this intelligence, a zero cross detection comparator is used to prevent
negative inductor current by turning off the low-side MOSFET. Equation 3 shows the boundary load condition of
this skip mode and continuous conduction operation.

ILOAD(LL) =
(VIN - VOUT ) ´ VOUT ´ 1
2 ´ LX VIN fSW (3)

9.1.3 VTT and VTTREF

TPS51216-EP integrates two high performance, low-dropout linear regulators, VTT and VTTREF, to provide
complete DDR2/DDR3/DDR3L power solutions. The VTTREF has a 10-mA sink/source current capability, and
tracks ½ of VDDQSNS with ±1% accuracy using an on-chip ½ divider. A 0.22-μF (or larger) ceramic capacitor
must be connected close to the VTTREF terminal for stable operation. The VTT responds quickly to track
VTTREF within ±40 mV at all conditions, and the current capability is 2 A for both sink and source. A 10-μF (or
larger) ceramic capacitor must be connected close to the VTT terminal for stable operation. To achieve tight
regulation with minimum effect of wiring resistance, a remote sensing terminal, VTTSNS, should be connected to
the positive node of the VTT output capacitors as a separate trace from the high-current line to the VTT pin.
(Refer to Layout Guidelines for details.)
When VTT is not required in the design, the following treatments are strongly recommended.
• Connect VLDOIN to VDDQ.

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Application Information (continued)

• Tie VTTSNS to VTT, and remove capacitors from VTT to float.
• Connect VTTGND to GND.
• Select MODE 0 or MODE 1 shown in Table 2 (select non-tracking discharge mode).
• Maintain a 0.22-µF capacitor connected at VTTREF.
• Pull down S3 to GND with 1-kΩ resistance.
VIN

5VIN
TPS51216
PGND
VBST 15
12 V5IN VDDQ

17 S3 DRVH 14

SW 13
1 kW S5 16 S5
DRVL 11
6 VREF PGND 10
PGND PGND
PGOOD 20 Powergood
8 REFIN VDDQSNS 9

VLDOIN 2
7 GND VTT 3

19 MODE VTTSNS 1

18 TRIP VTTGND 4

VTTREF 5
0.22 mF

AGND PGND AGND PGND

UDG-13089

Figure 33. Application Circuit When VTT is not Required

9.1.4 VDDQ Overvoltage and Undervoltage Protection

TPS51216-EP sets the overvoltage protection (OVP) when the VDDQSNS voltage reaches a level 20% (typ)
higher than the REFIN voltage. When an OV event is detected, the controller latches DRVH low and DRVL high.
VTTREF and VTT are turned off and discharged using the non-tracking discharge MOSFETs regardless of the
tracking mode.
The undervoltage protection (UVP) latch is set when the VDDQSNS voltage remains lower than 68% (typ) of the
REFIN voltage for 1 ms or longer. In this fault condition, the controller latches DRVH low and DRVL low and
discharges the VDDQ, VTT, and VTTREF outputs. UVP detection function is enabled after 1.2 ms of SMPS
operation to ensure startup.
To release the OVP and UVP latches, toggle S5 or adjust the V5IN voltage down and up beyond the
undervoltage lockout threshold.

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Application Information (continued)

9.1.5 VDDQ Overcurrent Protection
The VDDQ SMPS has cycle-by-cycle overcurrent limiting protection. The inductor current is monitored during the
off-state using the low-side MOSFET RDS(on) and the controller maintains the off-state while the voltage across
the low-side MOSFET is larger than the overcurrent trip level. The current monitor circuit inputs are PGND and
SW pins so that those should be properly connected to the source and drain terminals of low-side MOSFET. The
overcurrent trip level, VTRIP, is determined by Equation 4.
VTRIP = RTRIP ´ ITRIP

where
• RTRIP is the value of the resistor connected between the TRIP pin and GND
• ITRIP is the current sourced from the TRIP pin. ITRIP is 10 μA typically at room temperature, and has 4700
ppm/°C temperature coefficient to compensate the temperature dependency of the low-side MOSFET RDS(on).
(4)
Because the comparison is done during the off-state, VTRIP sets the valley level of the inductor current. The load
current OCL level, IOCL, can be calculated by considering the inductor ripple current as shown in Equation 5.
æ V ö IIND(ripple ) æ V ö 1 V -V VOUT
IOCL = ç TRIP ÷+ =ç TRIP ÷ + ´ IN OUT
´
ç 8 ´ RDS(on ) ÷ 2 ç 8 ´ RDS(on ) ÷ 2 LX fSW ´ VIN
è ø è ø
where
• IIND(ripple) is inductor ripple current (5)
In an overcurrent condition, the current to the load exceeds the current to the output capacitor, thus the output
voltage tends to fall down. Eventually, it crosses the undervoltage protection threshold and shuts down.

9.2 Typical Application

V5IN
4.5 V to 5.5 V R2 200 kW
R1
100 kW R3 36 kW
S5
S3
C12 AGND VIN
10 mF 21 20 19 18 17 16 8 V to 20 V
C5 C7 C8 C9 C10
PwPad

MODE

S3

S5
PGOOD

TRIP

R6 0.1 mF 10 mF 10 mF 10 mF
0W 0.1 mF
PGND
VTT VBST 15
1 VTTSNS
0.75 V/2 A R7 0 W PGND L1
2 VLDOIN DRVH 14 Q1 0.56 mH
C1 FDMS8680
10 mF U1 VDDQ
3 VTT SW 13
TPS51216RUK 1.5 V/20 A

VTTGND 4 VTTGND V5IN 12 Q2

VDDQSNS

FDMS8670AS
5 VTTREF DRVL 11 Q3
REFIN

PGND

PGND
VREF

C6 C11
GND

FDMS8670AS
1 mF 330 mF

VTTREF 6 7 8 9 10
0.75 V
VDDQ_GND
R4
10 kW

R5 PGND AGND
C2 C3 C4 49 kW
0.22 mF 0.1 mF 10 nF
UDG-10165

Figure 34. DDR3, 400-kHz Application Circuit, Tracking Discharge

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Typical Application (continued)

9.2.1 Design Requirements
See Table 3 for the design parameters.

Table 3. Design Parameters

VIN VDDQ IVDDQ VTT IVTT FSW
8 to 20 V 1.5 V 20 A 0.75 V 2A 400 kHz

9.2.2 Detailed Design Procedure

[Link] List of Materials

Table 4. DDR3, 400-kHz Application Circuit, List of Materials

REFERENCE DESIGNATOR QTY SPECIFICATION MANUFACTURER PART NUMBER
C8, C9, C10 3 10 µF, 25 V Taiyo Yuden TMK325BJ106MM
C11 1 330 µF, 2V, 6 mΩ Panasonic EEFSX0D331XE
L1 1 0.56 µH, 21 A, 1.56 mΩ Panasonic ETQP4LR56WFC
Q1 1 30 V, 35 A, 8.5 mΩ Fairchild FDMS8680
Q2, Q3 2 30 V, 42 A, 3.5 mΩ Fairchild FDMS8670AS

For this example, the bulk output capacitor ESR requirement for D-CAP mode is described in Equation 6,
whichever is greater.
20mV ´ fSW ´ L 3
ESR ³ or ESR ³
VOUT 2p ´ fSW ´ COUT (6)

[Link] External Components Selection

The external components selection is simple in D-CAP mode.
1. Determine the value of R4 and R5.
The output voltage is determined by the value of the voltage-divider resistor, R4 and R5, as shown in
Figure 34. R4 is connected between VREF and REFIN pins, and R5 is connected between the REFIN pin
and GND. Setting R4 as 10-kΩ is a good starting point. Determine R4 using Equation 7.
R1
R2 =
æ ö
ç ÷
ç 1.8 ÷
ç ÷ -1
ç æ IIND(ripple ) ´ ESR ö ÷
ç VOUT - ç ÷÷
ç ç 2 ÷÷
è è øø (7)
2. Choose the inductor.
The inductance value should be determined to yield a ripple current of approximately ¼ to ½ of maximum
output current. Larger ripple current increases output ripple voltage and improves the signal-to-noise ratio
and helps stable operation.

LX =
1
´
(V IN(max ) - VOUT )´ V OUT
=
3
´
(VIN(max ) - VOUT )´ V
OUT

IIND(ripple ) ´ fSW VIN(max ) IO(max ) ´ fSW VIN(max )

(8)
The inductor needs a low direct current resistance (DCR) to achieve good efficiency, as well as enough room
above peak inductor current before saturation. The peak inductor current can be estimated in Equation 9.

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IIND(peak ) =
VTRIP
+
1
´
( )
VIN(max ) - VOUT ´ VOUT
8 ´ RDS(on ) L X ´ fSW VIN(max )
(9)
3. Choose the OCL setting resistance, RTRIP.
Combining Equation 4 and Equation 5, RTRIP can be obtained using Equation 10.
æ æ (V - VOUT ) ö VOUT ö
8 ´ ç IOCL - ç IN ÷ ´ ÷ ´ RDS(on)
è (2 ´ L X ) ø (fSW ´ VIN ) ø
ç ç ÷ ÷
RTRIP = è
ITRIP (10)
4. Choose the output capacitors.
TI recommends organic semiconductor capacitors or specialty polymer capacitors. Determine ESR to meet
small signal stability and recommended ripple voltage. A quick reference is shown in Equation 11 and
Equation 12.
1 f
£ SW
2p ´ ESR ´ COUT 3 (11)
VOUT ´ ESR
³ 20mV
fSW ´ L X (12)

9.2.3 Application Curve

Figure 35. Output Ripple

10 Power Supply Recommendations

TPS51216-EP is designed to operate from input voltage supply range of 8 to 20 V. This supply must be well
regulated. The power supply must be well bypassed for proper electrical performance. See Layout Example for
recommended bypass capacitor placement.

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11 Layout

11.1 Layout Guidelines

Certain issues must be considered before designing a layout using the TPS51216-EP.
• VIN capacitors, VOUT capacitors, and MOSFETs are the power components and should be placed on one
side of the PCB (solder side). Other small signal components should be placed on another side (component
side). At least one inner plane should be inserted, connected to ground, in order to shield and isolate the
small signal traces from noisy power lines.
• All sensitive analog traces and components such as VDDQSNS, VTTSNS, MODE, REFIN, VREF, and TRIP
should be placed away from high-voltage switching nodes such as SW, DRVL, DRVH, or VBST to avoid
coupling. Use internal layers as ground planes and shield feedback trace from power traces and components.
• The DC/DC converter has several high-current loops. The area of these loops should be minimized in order to
suppress generating switching noise.
– The most important loop to minimize the area of is the path from the VIN capacitors through the high and
low-side MOSFETs, and back to the capacitors through ground. Connect the negative node of the VIN
capacitors and the source of the low-side MOSFET at ground as close as possible. (Refer to loop number
1 of Figure 36)
– The second important loop is the path from the low-side MOSFET through inductor and VOUT capacitors,
and back to source of the low-side MOSFET through ground. Connect source of the low-side MOSFET
and negative node of VOUT capacitors at ground as close as possible. (Refer to loop number 2 of
Figure 36)
– The third important loop is of gate driving system for the low-side MOSFET. To turn on the low-side
MOSFET, high current flows from V5IN capacitor through gate driver and the low-side MOSFET, and back
to negative node of the capacitor through ground. To turn off the low-side MOSFET, high current flows
from gate of the low-side MOSFET through the gate driver and PGND, and back to source of the low-side
MOSFET through ground. Connect negative node of V5IN capacitor, source of the low-side MOSFET and
PGND at ground as close as possible. (Refer to loop number 3 of Figure 36)
• Because the TPS51216-EP controls output voltage referring to voltage across VOUT capacitor, VDDQSNS
should be connected to the positive node of VOUT capacitor. In a same manner GND should be connected to
the negative node of VOUT capacitor.
• Connect the overcurrent setting resistors from TRIP pin to ground and make the connections as close as
possible to the device. The trace from TRIP pin to resistor and from resistor to ground should avoid coupling
to a high-voltage switching node.
• Connect the frequency and mode setting resistor from MODE pin to ground, and make the connections as
close as possible to the device. The trace from the MODE pin to the resistor and from the resistor to ground
should avoid coupling to a high-voltage switching node
• Connections from gate drivers to the respective gate of the high-side or the low-side MOSFET should be as
short as possible to reduce stray inductance. Use 0.65 mm (25 mils) or wider trace and vias of at least 0.5
mm (20 mils) diameter along this trace.
• The PCB trace defined as SW node, which connects to the source of the switching MOSFET, the drain of the
rectifying MOSFET and the high-voltage side of the inductor, should be as short and wide as possible.
• VLDOIN should be connected to VDDQ output with short and wide traces. An input bypass capacitor should
be placed as close as possible to the pin with short and wide　connections.
• The output capacitor for VTT should be placed close to the pin with a short and wide connection in order to
　avoid additional ESR and/or ESL of the trace.
• VTTSNS should be connected to the positive node of the VTT output capacitors as a separate trace from the
high-current power line and is strongly recommended to avoid additional ESR and/or ESL. If it is needed to
　sense the voltage at the point of the load, it is recommended to attach the output capacitors at that point.
Also, it is recommended to minimize any additional ESR and/or ESL of ground trace between GND pin and
the output capacitors.
• Consider adding a low pass filter (LPF) at VTTSNS in case the ESR of the VTT output capacitors is larger
than 2 mΩ.
• VDDQSNS can be connected separately from VLDOIN. Remember that this sensing potential is the reference
voltage of VTTREF. Avoid any noise generative lines.
• The negative node of the VTT output capacitors and the VTTREF capacitor should be tied together by

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Layout Guidelines (continued)

avoiding　common impedance to high-current path of the VTT source/sink current.
• GND pin node represents the reference potential for VTTREF and VTT outputs. Connect GND　to negative
nodes of VTT capacitors, VTTREF capacitor and VDDQ capacitors with care to avoid additional ESR and/or
ESL. GND and PGND should be connected together at a single point.
• In order to effectively remove heat from the package, prepare the thermal land and solder to the package
thermal pad. Wide trace of the component-side copper, connected to this thermal land, helps heat spreading.
Numerous vias with a 0.3-mm diameter connected from the thermal land to the internal/solder-side ground
planes should be used to help dissipation.

CAUTION
Do not connect PGND pin directly to this thermal land underneath the package.

11.2 Layout Example

2
VLDOIN TPS51216 VIN
VTT
VTT
3

10 mF VTTGND
VTTGND
4 V5IN #1
12 VOUT
VTTREF
1 mF
5 #2
DRVL
MODE
0.22 mF 11
19
#3
TRIP PGND

18 10
VREF REFIN GND
6 8 7

0.1 mF
10 nF

UDG-10166

Figure 36. DC/DC Converter Ground System

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12 Device and Documentation Support

12.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.2 Trademarks
D-CAP, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

26 Submit Documentation Feedback Copyright © 2015, Texas Instruments Incorporated

Product Folder Links: TPS51216-EP

 PACKAGE OPTION ADDENDUM

[Link] 3-Mar-2016

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

TPS51216MRUKREP ACTIVE WQFN RUK 20 3000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 125 51216M
& no Sb/Br)
V62/16601-01XE ACTIVE WQFN RUK 20 3000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -55 to 125 51216M
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check [Link] for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 3-Mar-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS51216-EP :

• Catalog: TPS51216

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 12-Dec-2015

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS51216MRUKREP WQFN RUK 20 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 12-Dec-2015

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS51216MRUKREP WQFN RUK 20 3000 367.0 367.0 35.0

Pack Materials-Page 2
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