Memory Design
(Introduction, SRAM)
K. R. Viveka
PhD Student,
ECE Dept., IISc
How important are memories today?
1989 – AMD486DX 1999 – Intel Pentium 3 2000 – Intel P4 2001 – Itanium1
2002 – Itanium2 2003 – Pentium M 2006 – Core 2 Duo 2009 – i5 (3rd generation)
Why is Memory Design Exciting ?
• ITRS – Memories will 90% of SoC area
– Large effect
• Large fast SRAM
– improve performance
– Cost area
• Focus to minimize footprint
• Densest circuitry on chip
• Forefront of scaling
– Cutting edge problems to solve
Classification
Memory Array Architecture
SRAM
• Most widely used
• Good to illustrate
– Cell design, decoding, and column circuitry design
• Advantages:
– Denser than Flip-flops
– Compatible with standard CMOS – unlike eDRAM
– Faster than DRAM
– Easier to use than DRAMs
Cell Design
Flip-Flop
• 6 Transistor
• 10 times smaller!
SRAM Cell
Read Operation (1)
• P – Pull Up
• D – Pull Down
• A – Access
Read (2) – Data Stored
0✗ ✓1
✓ ✗
✗- OFF ✓- ON
Read (3) – Precharge, WL, BL - discharge
1 0 1
01
✗
0 ✓1
✓ ✗
Precharge WL - high BL - sense
PRECHARGE
WL - Activation
Note: Read Stability
SRAM Column - Read
SRAM – Write (1)
1 0
1
✗
0 ✓1
✓ ✗
Drive BLs & WL
SRAM – Write (2)
1 0
1 ✓
✗
1
0
Regenerative Action – Positive feedback
SRAM – Write (3)
1 0
1
1✓ ✗0
✗ ✓
Write – done!
Note: Writability
SRAM Column - Write
Summary thus far..
• Importance of memories
• SRAM
– Read & Write
• D1 >> A1 >> P1
• D2 >> A2 >> P2
• Hold:
– Sizing constraints?
How do we quantify this?
• SNM – Static Noise Margin
• Read and Hold: 2 stable states
• Write: 1 stable state
• SNM – Measure of noise
– Read & Hold: stable state is lost
– Write: a 2nd stable state created!
Cell Stability – Hold
• Note: NOT related to Hold-
margin of Flip-flop!
• Measurement setup
• How can we maximize this?
– Symmetric inverters
– Increases with VDD and Vt
Read Margin
• D1 >> A1 (D2 >> A2)
• Again: Increases with VDD and Vt
• WL voltage?
– Increases if WL voltage is reduced (relative to VDD)
Write Margin
• Draw: Circuit Diagram
• A1 >> P1 (A2 >> P2)
• Decreases with VDD
• What about Vt?
– Above Eqn.
• WL Voltage?
– Increases if WL voltage is
increased (relative to VDD)
SNM – Variation, Low supply
Read Write Hold
VDD = 0.9 V
VDD = 0.6 V
Cell Design
• Minimum area
– N1 >> N2 >> P1
– Push DRC
– Share contacts – minimize CBL
– Symmetrical
– Litho-friendly
– Aspect ratio
Takeda, JSSC, Jan 2006
Current State of the art!
• Intel 14nm node – 1.7 Billion bits in 1cm2!
SRAM Macro
Row Circuitry
• N-bit Address
– N-input NAND gate
– Pseudo-NMOS
• WL Load
– 2 tx load per cell
– Long lines
– Narrow lines (high R)
• Layout Issue
– Pitch match SRAM
cell! 2-bit Address Decoder
Decoder (Contd.)
• WL – qualified by
Clock
– Another AND function
– Share transistor
• 1-Hot nature!
– Share sleep tx
– Reduce leakage
Pre-decoders
3 x 16 = 48 NAND2 gates 8 + 16 = 24 NAND2 gates
Hierarchical WLs
Column Circuitry
• Bitline conditioning
– Precharge BL
– BL equalization
• Large signal sensing (a) BL Equalization (b) BL noise
– Full swing reduction
– Hierarchical BLs
• Small signal sensing
– Reduced BL swing
– BL noise reduction
• Sense-amplifier
• Column MUXing
Sense-Amplifier
Timing generation
Replica column for SA timing
Example 16 KB sub-array
Reminder:
• Simulation Query:
– Negative current?