METHODOLOGY AND IMPLEMENTATION OF PWM

This chapter gives the detailed information about the design, methodology and implementation of all
the modules designed for generation of PWM signals. The source code for the same is given in
appendix1.

REGISTER

As shown in the figure 2.1, the inputs are 12-bit address, 16-bit data, read, write, and reset.
Whenever rst is high the output will be zero, this is done to remove all unwanted bits. Hence
when rd is high, wr and rst are low, the register stores the lower 8-bit of data. Among these 8-
bit, the MSB bit that is the 8thbit is used to indicate the direction of the motor. If the direction
bit is ‘1’ it rotates in forward direction and if it is ‘0’ it rotates in reverse direction. The
remaining 7-bit are used as duty cycle for the PWM generation, it can be varied from 1 to
100%.

PWM GENERATION

PWM generation is simple logic based on counters. Here we use two counters, one is used to
monitor the duty cycle and the other is for the time period of PWM signal. The inputs are
duty cycle, clock and the reset. The outputs are pwm and states. There are 3 states of
operation. whenever the rst is high, it will be in state 0 where the pwm=’1’ and both the
counters are initialized to zero, once the rst becomes low it goes to next state of operation.
The next state of operation is state 1 where both the counters start incrementing. If the
counter 2 is greater than or equal to the duty cycle, it goes to next state 2. In state 2, pwm=’0’
and if the counter 1 is greater than or equal to 100, it goes back to state 0 and the process
continues. For every rising edge of the clock, the output changes its state. The flowchart and
the state diagram are given below.

COMMUNICATION SEQUENCE GENERATION

It mainly consist of three modules, clock division module to obtain hall sensor signals, D flip-
flop for delay and finally the pwm(x) signals are generated using communication sequence.
This section gives the detailed explanation of each module.

CLOCK DIVISION

In this module we generate one of the hall sensor signals. We use clock division rule to
generate a signal. Here the clock frequency f is divided into f/6. The inputs to this module are
clock and reset. Rst has same functionality as in any other module. Once the rst is low, we get
the output signal ‘A’ which is ‘1’ for three clock cycles and ‘0’ for next three clock cycles.
This is also done based on the simple logic of counters.

D FLIP FLOP
As seen in figure, the hall sensor signal ‘A’ can be generated using clock division and it can
also be observed that the hall sensor signal ‘B’ is delayed by one clock period from ‘A’.
Similarity hall sensor signals ‘C’ is delayed by one clock period from’ B’. Signal ‘A’ can be
generated as explained in the previous section. To obtain signals ‘B’ and ’C’ we need delay
elements, therefore we use D flip-flops. The input to this module ‘A’, clk and rst. D flip-flops
output the same data as the input with delay; hence we obtain the signal ’B’. In the similar
way by using another D flip flop where input signal is ‘B’, signal ‘C’ can be generated. Thus
we obtain the sequence based on which the different PWM signals will be either ON or OFF.

PWM GENERATION USING COMMUTATION SEQUENCE

The input for this module is three hall sensor signals, the pwm_ in generated for a certain
duty cycle, the direction bit and the reset. Here according to table1 and table2 the
commutation sequence is generated, this determines which two pwm signals should be ON
for that particular hall sensor signals. It can be done by constructing a K-map for table1 and
table2. The pwm(x) signals which is obtained by the K-ap are AND with the previously
generated pwm signal. Thus the final pwm signals for BLDC motors are generated. Further
these signals are given to driver circuit and then to the BLDC motors. Figure below show the
K-map for both forward and reverse direction.

METHODOLOGY AND IMPLEMENTATION OF EDAC

This chapter gives the detailed information about the design, methodology and implementation of all
the modules designed for EDAC. The source code for the same is given in appendix2.

CHECK BIT GENERATION

In this module during memory write cycle, the data along with 6 check bits are generated.
Here the inputs are 16-bit data and write signal. Whenever the wr signal goes low, the 16-bit
data along with 6-check bits are generated. Check bits are generated using equation 1-6, with
reference to table 4.

SYNDROME GENERATION

The syndrome generator produces 6 syndrome- bits from the stored check bits during
memory write cycle and the incoming data check bits. By using XOR operation we can
compare both generated and stored check bits. As we know the XOR operation is when both
the values are same it gives ‘0’ output indicating no error and if both the values are different
it give ‘1’ output indicating error. Based on this comparing all the check bits stored in
memory with the check bits generated by incoming data using XOR operation we obtain the
syndromes bits. Syndrome bits are used to identify the position of the error bit. Hence using
this module we can detect the error.

EDAC UNIT
As explained in previous section syndrome units are used to determine the position of error
bit, this is the input for EDAC module. By using case statement for all the combinations of
syndrome according to table4 we can check for the error in all 16-bit of data. Any single error
in the 16-bit data will change the sense of exactly three bits of the check bits. Any single
error in the check bits changes the sense of only that one bit. Error connection is
accomplished by identifying the bad bit and inverting it. The outputs for this module are
corrected data, its check bits, single error flag (sef) and double error flag (def). In case of
single error, in data and check bit, the sef flag will be set high while the def flag remains low.
The 2-bit error is correctable but it can be identified, both the error flags are set high when
any 2-it error is detected.

SIMULATION AND RESULT ANALSIS OF PWM

This chapter gives the synthesis and simulation results of each module of PWM generation.
The simulation results of both Xilinx and libero softwares are shown. The RTL schematic of
the final top module is also shown.

SIMULATION WAVEFORM OF REGISTER MODULE

When rd is high, wr and rst are low; the register stores the lower 8-bit of data. Among these
8-bit, the MSB bit that is the 8 th bit is used to indicate the direction of the motor. The
remaining 7-bit are used as duty cycle for the PWM generation, it can be varied from 1 to
100%.

SIMULATION WAVEFORM OF PWM

The waveform in figure shows the PWM signal with 50% duty cycle. It also shows the
different states of operation.

SIMULATION WAVEFORM OF CLOCK DIVISION AND D FLIP FLOP

Figure shows the output waveform of clock division, where it is ‘1’ for three clock period and
‘0’ for next three clock periods. Figure shows the output waveform of D flip flop.

SIMULATION WAVEFORM OF TOP MODULE

SYNTHESIS AND SIMULATION USING LIBERO

SIMULATION AND RESULT ANALSIS OF PWM

This chapter gives the synthesis and simulation results of each module of EDAC. The
simulation results of both Xilinx and modelism are shown. The RTL schematic of the final
top module is also shown.

RTL SCHEMATIC
SIMULATION WAVEFORM OF EDAC TOP MODULE

Figure shows the EDAC output fir single bit error. During write cycle the input data along
with check bit are written into the memory. When RD is high syndrome bits are generated
and single bit error is corrected. In fig the double bit error is detected indicating both the flags
ie.,sef and def are set high.