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Verilog Clock Divider Implementation

The document describes the implementation of a clock divider in Verilog. A clock divider takes an input clock and produces an output clock with a frequency that is a fraction of the input frequency. It presents the circuit diagram and output waveforms of a clock divider that divides the frequency by 2 and 4. It also includes the RTL schematic, technology schematic, area report, and conclusion stating that the Verilog code for a clock divider was implemented and simulated successfully.

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18 views6 pages

Verilog Clock Divider Implementation

The document describes the implementation of a clock divider in Verilog. A clock divider takes an input clock and produces an output clock with a frequency that is a fraction of the input frequency. It presents the circuit diagram and output waveforms of a clock divider that divides the frequency by 2 and 4. It also includes the RTL schematic, technology schematic, area report, and conclusion stating that the Verilog code for a clock divider was implemented and simulated successfully.

Uploaded by

uday
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Experiment 10

Aim:- Verilog Implementation of Clock divider


Important Concepts/Theory:-

A clock divider is usually a device takes an input clock that is used to produce an output
clock. The output clock frequency is function of the input clock frequency where the output
clock frequency is the result of the input frequency divided by an integer. It is an electronic
device that is capable of dividing the frequency of a given digital input pulse train by a fixed
integer value, n. It often consists of an n-stage counter, the output frequency at the nth stage
of counting being an nth submultiple of the input frequency.

Clock divider by 2:

Fig.1: Circuit diagram of Clock Divider by 2

Fig.2: Output Waveform of Clock Divider


by 2
Design Analysis: -

Code: -

Clock Divider By N: -

Results: -

Simulation (Waveform)

Fig. 3: Simulated Waveform of Clock Divider by 2


Fig. 4: Simulated Waveform of Clock Divider by 4

Report Results: -

RTL Schematic: -

Fig. 5: RTL Schematic of Clock divider

Tech Schematic: -
Fig. 6: Tech Schematic of Clock divider

Area Report: -

Fig. 7: Area Report of Clock divider

Conclusion:
Verilog HDL code for Clock Divider has been implemented and their simulation with signals
has been tested.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6

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