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Verilog Clock Divider Implementation

The document describes an experiment to implement a clock divider in Verilog. It discusses the concepts of a clock divider, which divides an input clock frequency by an integer to produce an output clock. Code is provided for a clock divider by 2 and a more general clock divider by n. The codes are tested through simulation waveforms and area reports are generated. The experiment aims to learn Verilog implementation of clock dividers through designing, coding, simulating and analyzing clock dividers by 2 and n.

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123 views6 pages

Verilog Clock Divider Implementation

The document describes an experiment to implement a clock divider in Verilog. It discusses the concepts of a clock divider, which divides an input clock frequency by an integer to produce an output clock. Code is provided for a clock divider by 2 and a more general clock divider by n. The codes are tested through simulation waveforms and area reports are generated. The experiment aims to learn Verilog implementation of clock dividers through designing, coding, simulating and analyzing clock dividers by 2 and n.

Uploaded by

uday
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
  • Introduction and Theory
  • Design Analysis
  • Results and Discussions
  • Conclusion

Experiment 10

Aim:- Verilog Implementation of Clock divider


Software Used:-
 HDL Designer (version 2017.1a)
 Precision RTL Synthesis (version 2012b.10)

Important Concepts/Theory:-

A clock divider is usually a device takes an input clock that is used to produce an output
clock. The output clock frequency is function of the input clock frequency where the output
clock frequency is the result of the input frequency divided by an integer. It is an electronic
device that is capable of dividing the frequency of a given digital input pulse train by a fixed
integer value, n. It often consists of an n-stage counter, the output frequency at the nth stage
of counting being an nth submultiple of the input frequency.

Clock divider by 2

Figure 9.2 Output Waveform of Clock


Divider by 2
Figure 9.1 Circuit diagram of Clock
Divider by 2

Design Analysis:-

Clock divider by 2
Codes:-
module clock_divider ( clk ,rst,out_clk );
output reg out_clk;
input clk ;
input rst;
always @(posedge clk)
begin
if (~rst)
out_clk <= 1'b0;
else
out_clk <= ~out_clk;
end
endmodule

Results/Discussion:-
[Link]:

Figure 9.3 Clock Divider by 2 simulation

[Link] Results
[Link] Schematic:

b. Tech Schematic:

Figure 9.4 RTL Schematic of Clock


Divider by 2

Figure 9.5 Tech Schematic of Clock


Divider by 2
c. Area Report

Figure 9.6 Area report of Clock Divider


by 2

Clock divider by n
Codes:-
module clock_divider

#(

parameter WIDTH = 3, // Width of the register required

parameter N = 3// We will divide by 6 for example in this case

(clk,reset, clk_out);

input clk;

input reset;

output clk_out;

reg [WIDTH-1:0] r_reg;

wire [WIDTH-1:0] r_nxt;

reg clk_track;

always @(posedge clk or posedge reset)

begin
if (reset)

begin

r_reg <= 0;

clk_track <= 1'b0;

end

else if (r_nxt == N)

begin

r_reg <= 0;

clk_track <= ~clk_track;

end

else

r_reg <= r_nxt;

end

assign r_nxt = r_reg+1;

assign clk_out = clk_track;

endmodule

Results/Discussion:-
[Link]:

Figure 9.7 Clock Divider by n simulation

[Link] Results b. Tech Schematic:


[Link] Schematic:

Figure 9.8 RTL Schematic of Clock


Divider by n
Figure 9.9 Tech Schematic of Clock
Divider by n

c. Area Report

Figure 9.10 Area report of Clock Divider


by n

Conclusion:
Verilog HDL code for Clock Divider has been implemented and their simulation with signals
has been tested.

Criteria Total Marks Marks Obtained Comments

Concept (A) 2

Implementation (B) 2

Performance (C) 2

Total 6

Experiment 10 Aim:- Verilog Implementation of Clock divider Software Used:-  HDL Designer (version 2017.1a)  Precision RTL
input clk ; input rst; always @(posedge clk) begin if (~rst) out_clk <= 1'b0; else out_clk <= ~out_clk; end endmodu
c. Area Report Figure 9.6 Area report of Clock Divider by 2 Clock divider by n Codes:- module clock_divider #( parameter
if (reset) begin r_reg <= 0; clk_track <= 1'b0; end else if (r_nxt == N) begin r_reg <= 0;
Figure 9.9 Tech Schematic of Clock Divider by n c. Area Report Figure 9.10 Area report of Clock Divider by n Conclusio

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