±
    
SLLS409K − JANUARY 2000 − REVISED MARCH 2004

D RS-232 Bus-Pin ESD Protection Exceeds DB, DW, OR PW PACKAGE

±15 kV Using Human-Body Model (HBM) (TOP VIEW)

D Meets or Exceeds the Requirements of

EN 1 20 FORCEOFF
TIA/EIA-232-F and ITU v.28 Standards
C1+ 2 19 VCC
D Operates With 3-V to 5.5-V VCC Supply V+ 3 18 GND
D Operates Up To 250 kbit/s C1− 4 17 DOUT1
D Two Drivers and Two Receivers C2+ 5 16 RIN1
C2− 6 15 ROUT1
D Low Standby Current . . . 1 µA Typical
V− 7 14 FORCEON
D External Capacitors . . . 4 × 0.1 µF DOUT2 8 13 DIN1
D Accepts 5-V Logic Input With 3.3-V Supply RIN2 9 12 DIN2
D Alternative High-Speed Pin-Compatible ROUT2 10 11 INVALID
Device (1 Mbit/s)
− SNx5C3223
D Applications
− Battery-Powered Systems, PDAs,
Notebooks, Laptops, Palmtop PCs, and
Hand-Held Equipment

description/ordering information
The MAX3223 consists of two line drivers, two line receivers, and a dual charge-pump circuit with ±15-kV ESD
protection pin to pin (serial-port connection pins, including GND). The device meets the requirements of
TIA/EIA-232-F and provides the electrical interface between an asynchronous communication controller and
the serial-port connector. The charge pump and four small external capacitors allow operation from a single
3-V to 5.5-V supply. The device operates at data signaling rates up to 250 kbit/s and a maximum of 30-V/µs
driver output slew rate.

ORDERING INFORMATION
ORDERABLE TOP-SIDE
TA PACKAGE†
PART NUMBER MARKING
Tube of 25 MAX3223CDW
SOIC (DW) MAX3223C
Reel of 2000 MAX3223CDWR
Tube of 70 MAX3223CDB
−0°C to 70°C SSOP (DB) MA3223C
Reel of 2000 MAX3223CDBR
Tube of 70 MAX3223CPW
TSSOP (PW) MA3223C
Reel of 2000 MAX3223CPWR
Tube of 25 MAX3223IDW
SOIC (DW) MAX3223I
Reel of 2000 MAX3223IDWR
Tube of 70 MAX3223IDB
−40°C to 85°C SSOP (DB) MB3223I
Reel of 2000 MAX3223IDBR
Tube of 70 MAX3223IPW
TSSOP (PW) MB3223I
Reel of 2000 MAX3223IPWR
† Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at [Link]/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

    !"#$ % &'!!($ #%  )'*+&#$ ,#$( Copyright  2004, Texas Instruments Incorporated
!,'&$% &!" $ %)(&&#$% )(! $-( $(!"%  (.#% %$!'"($%
%$#,#!, /#!!#$0 !,'&$ )!&(%%1 ,(% $ (&(%%#!+0 &+',(
$(%$1  #++ )#!#"($(!%

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1


 
 


    
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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

description/ordering information (continued)

Flexible control options for power management are available when the serial port is inactive. The
auto-powerdown feature functions when FORCEON is low and FORCEOFF is high. During this mode of
operation, if the device does not sense a valid RS-232 signal, the driver outputs are disabled. If FORCEOFF
is set low and EN is high, both drivers and receivers are shut off, and the supply current is reduced to 1 µA.
Disconnecting the serial port or turning off the peripheral drivers causes auto-powerdown to occur.
Auto-powerdown can be disabled when FORCEON and FORCEOFF are high. With auto-powerdown enabled,
the device is activated automatically when a valid signal is applied to any receiver input. The INVALID output
is used to notify the user if an RS-232 signal is present at any receiver input. INVALID is high (valid data) if any
receiver input voltage is greater than 2.7 V or less than −2.7 V, or has been between −0.3 V and 0.3 V for less
than 30 µs. INVALID is low (invalid data) if the receiver input voltage is between −0.3 V and 0.3 V for more than
30 µs. Refer to Figure 4 for receiver input levels.

Function Tables

EACH DRIVER
INPUTS
OUTPUT
VALID RIN DRIVER STATUS
DIN FORCEON FORCEOFF DOUT
RS-232 LEVEL
X X L X Z Powered off
L H H X H Normal operation with
H H H X L auto-powerdown disabled
L L H Yes H Normal operation with
H L H Yes L auto-powerdown enabled
L L H No Z Powered off by
H L H No Z auto-powerdown feature
H = high level, L = low level, X = irrelevant, Z = high impedance

EACH RECEIVER
INPUTS
OUTPUT
VALID RIN
RIN EN ROUT
RS-232 LEVEL
L L X H
H L X L
X H X Z
Open L No H
H = high level, L = low level, X = irrelevant,
Z = high impedance (off), Open = input
disconnected or connected driver off

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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

logic diagram (positive logic)

13 17
DIN1 DOUT1

12 8
DIN2 DOUT2

20
FORCEOFF 11
14 Auto-powerdown INVALID
FORCEON

1
EN
15 16
ROUT1 RIN1

10 9
ROUT2 RIN2

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Positive output supply voltage range, V+ (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 7 V
Negative output supply voltage range, V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.3 V to −7 V
Supply voltage difference, V+ − V− (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 V
Input voltage range, VI: Driver, FORCEOFF, FORCEON, EN . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to 6 V
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −25 V to 25 V
Output voltage range, VO: Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −13.2 V to 13.2 V
Receiver, INVALID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V
Package thermal impedance, θJA (see Notes 2 and 3): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Operating virtual junction temperature, TJ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. All voltages are with respect to network GND.
2. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable
ambient temperature is PD = (TJ(max) − TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability.
3. The package thermal impedance is calculated in accordance with JESD 51-7.

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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

recommended operating conditions (see Note 4 and Figure 6)

MIN NOM MAX UNIT
VCC = 3.3 V 3 3.3 3.6
Supply voltage V
VCC = 5 V 4.5 5 5.5

DIN, EN, FORCEOFF, VCC = 3.3 V 2

VIH Driver and control high-level input voltage V
FORCEON VCC = 5 V 2.4
VIL Driver and control low-level input voltage DIN, EN, FORCEOFF, FORCEON 0.8 V
Driver and control input voltage DIN, EN, FORCEOFF, FORCEON 0 5.5
VI V
Receiver input voltage −25 25
MAX3223C 0 70
TA Operating free-air temperature °C
MAX3223I −40 85
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 6)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
Input leakage EN, FORCEOFF,
II ±0.01 ±1 µA
current FORCEON
No load,
Auto-powerdown
FORCEOFF and 0.3 1 mA
disabled
FORCEON at VCC
VCC = 3.3 V or 5 V,
ICC Supply current Powered off No load, FORCEOFF at GND 1 10
TA = 25°C
No load, FORCEOFF at VCC, µA
Auto-powerdown
FORCEON at GND, 1 10
enabled
All RIN are open or grounded
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.

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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

DRIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 6)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VOH High-level output voltage DOUT at RL = 3 kΩ to GND 5 5.4 V
VOL Low-level output voltage DOUT at RL = 3 kΩ to GND −5 −5.4 V
IIH High-level input current VI = VCC ±0.01 ±1 µA
IIL Low-level input current VI at GND ±0.01 ±1 µA
VCC = 3.6 V, VO = 0 V ±35 ±60
IOS Short-circuit output current‡ mA
VCC = 5.5 V, VO = 0 V ±35 ±60
ro Output resistance VCC, V+, and V− = 0 V, VO = ±2 V 300 10M Ω
VO = ±12 V, VCC = 3 V to 3.6 V ±25
Ioff Output leakage current FORCEOFF = GND µA
VO = ±10 V, VCC = 4.5 V to 5.5 V ±25
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
‡ Short-circuit durations should be controlled to prevent exceeding the device absolute power-dissipation ratings, and not more than one output
should be shorted at a time.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 6)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
CL = 1000 pF, RL = 3 kΩ,
Maximum data rate 250 kbit/s
One DOUT switching, See Figure 1
CL = 150 pF to 2500 pF, RL = 3 kΩ to 7 kΩ,
tsk(p) Pulse skew§ 100 ns
See Figure 2
Slew rate, transition region VCC = 3.3 V, CL = 150 pF to 1000 pF 6 30
SR(tr) V/µs
(See Figure 1) RL = 3 kΩ to 7 kΩ CL = 150 pF to 2500 pF 4 30
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
§ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.

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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

RECEIVER SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4 and Figure 6)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
VOH High-level output voltage IOH = −1 mA VCC−0.6 VCC−0.1 V
VOL Low-level output voltage IOL = 1.6 mA 0.4 V
VCC = 3.3 V 1.6 2.4
VIT+ Positive-going input threshold voltage V
VCC = 5 V 1.9 2.4
VCC = 3.3 V 0.6 1.1
VIT− Negative-going input threshold voltage V
VCC = 5 V 0.8 1.4
Vhys Input hysteresis (VIT+ − VIT−) 0.5 V
Ioff Output leakage current EN = VCC ±0.05 ±10 µA
ri Input resistance VI = ±3 V to ±25 V 3 5 7 kΩ
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Note 4)
PARAMETER TEST CONDITIONS MIN TYP† MAX UNIT
tPLH Propagation delay time, low- to high-level output CL= 150 pF, See Figure 3 150 ns
tPHL Propagation delay time, high- to low-level output CL= 150 pF, See Figure 3 150 ns
CL= 150 pF, RL = 3 kΩ,
ten Output enable time 200 ns
See Figure 4
CL= 150 pF, RL = 3 kΩ,
tdis Output disable time 200 ns
See Figure 4
tsk(p) Pulse skew‡ See Figure 3 50 ns
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.
‡ Pulse skew is defined as |tPLH − tPHL| of each channel of the same device.
NOTE 4: Test conditions are C1−C4 = 0.1 µF at VCC = 3.3 V ± 0.3 V; C1 = 0.047 µF, C2−C4 = 0.33 µF at VCC = 5 V ± 0.5 V.

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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

AUTO-POWERDOWN SECTION

electrical characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 5)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Receiver input threshold for
VT+(valid) FORCEON = GND, FORCEOFF = VCC 2.7 V
INVALID high-level output voltage
Receiver input threshold for
VT−(valid) FORCEON = GND, FORCEOFF = VCC −2.7 V
INVALID high-level output voltage
Receiver input threshold for
VT(invalid) FORCEON = GND, FORCEOFF = VCC −0.3 0.3 V
INVALID low-level output voltage
IOH = −1 mA, FORCEON = GND,
VOH INVALID high-level output voltage VCC−0.6 V
FORCEOFF = VCC
IOL = 1.6 mA, FORCEON = GND,
VOL INVALID low-level output voltage 0.4 V
FORCEOFF = VCC

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 5)
PARAMETER TYP† UNIT
tvalid Propagation delay time, low- to high-level output 1 µs
tinvalid Propagation delay time, high- to low-level output 30 µs
ten Supply enable time 100 µs
† All typical values are at VCC = 3.3 V or VCC = 5 V, and TA = 25°C.

PARAMETER MEASUREMENT INFORMATION

3V
Input
RS-232 1.5 V 1.5 V
Output 0V
Generator
(see Note B) 50 Ω
CL tTHL tTLH
RL (see Note A)
VOH
3V 3V 3V
Output
FORCEOFF −3 V −3 V VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

SR(tr) + 6V
t or t
THL TLH

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 1. Driver Slew Rate

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SLLS409K − JANUARY 2000 − REVISED MARCH 2004

PARAMETER MEASUREMENT INFORMATION

3V
RS-232 Input 1.5 V 1.5 V
Output 0V
Generator
50 Ω tPHL tPLH
(see Note B) CL
RL (see Note A)
VOH
3V 50% 50%
Output
FORCEOFF VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.

B. The pulse generator has the following characteristics: PRR = 250 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 2. Driver Pulse Skew

EN
3V
0V Input
1.5 V 1.5 V
−3 V
Output
Generator
50 Ω
(see Note B) CL tPHL tPLH
(see Note A) VOH
0V Output 50% 50%
FORCEOFF VOL

TEST CIRCUIT VOLTAGE WAVEFORMS

NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 3. Receiver Propagation Delay Times

3V
VCC Input 1.5 V 1.5 V
GND
FORCEON S1 0V
3 V or 0 V tPHZ tPHZ
RL (S1 at GND) (S1 at GND)

3 V or 0 V Output VOH
Output 50%
CL
EN (see Note A) 0.3 V tPLZ
(S1 at VCC)
Generator 0.3 V
50 Ω
(see Note B) Output 50%
VOL
tPZL
(S1 at VCC)
TEST CIRCUIT VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 4. Receiver Enable and Disable Times

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PARAMETER MEASUREMENT INFORMATION

3V
2.7 V 2.7 V
Receiver 0V
Input 0V

ROUT −2.7 V −2.7 V

−3 V
Generator
50 Ω
(see Note B) tinvalid tvalid

VCC
INVALID 50% VCC 50% VCC
Output 0V

Auto- ten
INVALID
powerdown
CL = 30 pF V+ ≈V+
(see Note A) 0.3 V
Supply VCC
FORCEOFF Voltages 0V
0.3 V
DIN DOUT
FORCEON V− ≈V−

TEST CIRCUIT VOLTAGE WAVEFORMS

Valid RS-232 Level, INVALID High

2.7 V
ÎÎÎÎÎÎÎÎÎÎÎÎ
0.3 V ÎÎÎÎÎÎÎÎÎÎÎÎ Indeterminate

ÎÎÎÎÎÎÎÎÎÎÎÎ
If Signal Remains Within This Region
0V for More Than 30 µs, INVALID Is Low†

ÎÎÎÎÎÎÎÎÎÎÎÎ
−0.3 V

ÎÎÎÎÎÎÎÎÎÎÎÎ
Indeterminate
−2.7 V
Valid RS-232 Level, INVALID High

† Auto-powerdown disables drivers and reduces supply

current to 1 µA.
NOTES: A. CL includes probe and jig capacitance.
B. The pulse generator has the following characteristics: PRR = 5 kbit/s, ZO = 50 Ω, 50% duty cycle, tr ≤ 10 ns, tf ≤ 10 ns.

Figure 5. INVALID Propagation Delay Times and Supply Enabling Time

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APPLICATION INFORMATION

1 Auto- 20
EN FORCEOFF
powerdown

2 19
C1+ VCC
+ CBYPASS
− = 0.1µF
+ 3 18
C1 + V+ GND
− C3 †
−
4 17
C1− DOUT1

5 16
C2+ RIN1
+
C2
−
6 15
C2− ROUT1

5 kΩ
7 14
V− FORCEON
−
C4
+
8 13
DOUT2 DIN1

9 12
RIN2 DIN2

10 11
ROUT2 INVALID

5 kΩ

† C3 can be connected to VCC or GND.

NOTES: A. Resistor values shown are nominal.
B. Nonpolarized ceramic capacitors are acceptable. If polarized tantalum or electrolytic capacitors are used, they should be
connected as shown.

VCC vs CAPACITOR VALUES

VCC C1 C2, C3, C4

3.3 V ± 0.3 V 0.1 µF 0.1 µF

5 V ± 0.5 V 0.047 µF 0.33 µF
3 V to 5.5 V 0.1 µF 0.47 µF

Figure 6. Typical Operating Circuit and Capacitor Values

10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

 PACKAGE OPTION ADDENDUM

[Link] 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

MAX3223CDB ACTIVE SSOP DB 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C

& no Sb/Br)
MAX3223CDBR ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C
& no Sb/Br)
MAX3223CDW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3223C
& no Sb/Br)
MAX3223CDWG4 ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3223C
& no Sb/Br)
MAX3223CDWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MAX3223C
& no Sb/Br)
MAX3223CPW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C
& no Sb/Br)
MAX3223CPWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 MA3223C
& no Sb/Br)
MAX3223IDB ACTIVE SSOP DB 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I
& no Sb/Br)
MAX3223IDBR ACTIVE SSOP DB 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I
& no Sb/Br)
MAX3223IDW ACTIVE SOIC DW 20 25 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3223I
& no Sb/Br)
MAX3223IDWR ACTIVE SOIC DW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MAX3223I
& no Sb/Br)
MAX3223IPW ACTIVE TSSOP PW 20 70 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I
& no Sb/Br)
MAX3223IPWR ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I
& no Sb/Br)
MAX3223IPWRE4 ACTIVE TSSOP PW 20 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 MB3223I
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 24-Aug-2018

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF MAX3223 :

• Enhanced Product: MAX3223-EP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 20-Dec-2018

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
MAX3223CDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
MAX3223CDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
MAX3223IDBR SSOP DB 20 2000 330.0 16.4 8.2 7.5 2.5 12.0 16.0 Q1
MAX3223IDWR SOIC DW 20 2000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1
MAX3223IPWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 20-Dec-2018

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
MAX3223CDBR SSOP DB 20 2000 367.0 367.0 38.0
MAX3223CDWR SOIC DW 20 2000 367.0 367.0 45.0
MAX3223IDBR SSOP DB 20 2000 367.0 367.0 38.0
MAX3223IDWR SOIC DW 20 2000 367.0 367.0 45.0
MAX3223IPWR TSSOP PW 20 2000 367.0 367.0 38.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

[Link]
 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
DB0020A SCALE 2.000
TSSOP - 2 mm max height
SMALL OUTLINE PACKAGE

C
8.2
TYP
A 7.4
0.1 C
PIN 1 INDEX AREA SEATING
18X 0.65 PLANE
20
1

2X
7.5
5.85
6.9
NOTE 3

10
11 0.38
20X
0.22
5.6 0.1 C A B
B
5.0
NOTE 4

2 MAX
(0.15) TYP 0.25
SEE DETAIL A GAGE PLANE

0.95 0.05 MIN

0 -8 0.55

DETAIL A
A 15

TYPICAL

4214851/A 12/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-150.

[Link]
 EXAMPLE BOARD LAYOUT
DB0020A TSSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

1 (R0.05) TYP

20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED)
SOLDER MASK DETAILS
15.000

4214851/A 12/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DB0020A TSSOP - 2 mm max height
SMALL OUTLINE PACKAGE

20X (1.85) SYMM

(R0.05) TYP
1
20X (0.45) 20

SYMM
18X (0.65)

10 11

(7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4214851/A 12/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
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