Topics covered: Summary
1. Pre requisites; thevenin, super position, transistor characteristics, simple ac
amplifier.
2. Diode equation;
Id = Is*{exp(Vd/VT)-1} where VT is kT/q,
Is, the saturation current is about 10^-14 amp.
Diode characteristics; 60mV/decade, 18mV/octave. Current increases
exponentially as voltage is increases.
Diode voltage versus current is best plotted in semilog graph, where V in x axis is
in linear sacle and I in log scale is in Y asix. The plot is a straight line.
Dynamic resistance = .026/Id. At 1mA, it is 26 ohms.
3. Transistor: relationship between Ic, IB and IE
Ic/IB = β
IE = IB*(β+1)
Ic/IE = β/(β+1)
4. Three states:
ON, OFF and linear. In ON state, base emitter is fwd biased
State Base emitter Collector
base
ON FWD FWD
Linear FWD Rev
OFF Rev Rev
5. Three configurations
CE, CB and CC.
6. Equivalent circuit for transistor. Input resistance rπ. As input. Current source with
parallel resistance rc at output. Rc = early voltage VA / Ic, collector current.
7. Fixed bias, dc conditions: In CE, a fixed base current can be used to bias the
transistor. Depending on supply and Rc, the transistor may be in linear region
or ON.
8. Collector current increases by 10% if base emitter voltage is increased by
2.6mV.
9. Min VCB for operation in linear mode is zero volts.
[Link], Input resistance, output resistance, VG for common emitter
gm = Ic/β. rπ= β/gm; rE = 1/gm, rc = VA/Ic. When Ic is 1mA, gm is 38.5mA/volt, and rE is
26 ohms.
Output resistance = Rc||rc where Rc is resistance connected from collector to supply.
Draw circuit!!
[Link] voltage =VA.
Affects current in collector even if base current is kept constant. If VCE is
increased by 10% of VA, collector current increases by 10%.
[Link] degeneration.
When a resistor RE is placed in emitter, and not bypassed, the voltage gain
decreases from Rc/rE to Rc/(rE +RE)
[Link] base characteristics: Rin, VG, Rout:
In common base, input resistance = rE. VG is same as that for CE, except that
there is no reversal. Output res is Rc
[Link] collector characteristics: Rin, VG, Rout
In CC, input resistance is very high = β*(rE+RE).
Output resistance is very low, = rE if Rs is zero. Else it is rE+(Rs/β)
Voltage gain is close to but less than 1.
[Link] sources: Bipolar.
The VBE of a transiode is applied as VBE for output transistor. Due to base
current, ratio is 1/{1+(2/β)}. If β is 50, ratio is 0.96.
[Link] source: beta helper
A transistor (with collector connected to supply) is used to provide base
current for “transdiode” as well as output transistor. Advantage is that ratio is
closer to 1. It is 1/{1+(2/β^2)}. If β is 50, ratio is 0.9984. Draw circuit!!
[Link] current source.
Here a ‘current sense” – a transdiode – senses the current in output transistor
and controls conduction of “transdiode”. Draw circuit!!
[Link] current source
Used to get low current without having to use large resistor. Reduces cost of
IC as cost of IC is higher depending on area, and large resistances require
larger areas. 6k dropping 60mV in emitter reduces ref current of 100ua to
10uA.
Note 6k*10uA = 60mV if Ic = IE.
[Link] amplifier
Two transistors with emitters connected together and returned to negative supply
through a resistance REE = R. Collector of each transistor connected to +ve
supply through R.
Rin = 2*rπ. VG is half of what it is for CE, when output is taken between one
collector and ground.
Common mode gain is Rc/2REE. Common mode rej ratio is REE/rE.
Acm, Adm, Rdm, Rcm, CMRR
[Link] load
The gain of an amplifier depends on load resistance. To get effectively high
resistance without increasing the drop across it, a current source is used. One
can use a bipolar current source as active load. In differential amplifier this is
particularly attractive as two collectors are present, and one can conveniently
connect a transiode in one and the “output” transistor in the other. Remember
to take output from collector connected to “transistor” .
[Link] A amplifier
Has low efficiency. Dissipation is 3 times output power even when output
power is max. Draws current even when ac input is zero.
[Link] B amplifier; advantages
Higher efficiency, of 78% max. Low dissipation when input is near zero.
[Link] B cross over distortion
Due to necessity to overcome threshold of pnp and npn, no output results
when input is 0.6V peak. When input is 1.4V peak, output peak is 0.6V lesser,
with severe distortion, called cross over distortion. Draw circuit, waveforms.
[Link] B: prebias is used to reduce cross over distortion. Base voltage of npn
is held 1.2V higher using two diode drops, with constant current through them.
Draw circuit.
When input is applied to base of pnp. Output is always higher by an offset dc
of 0.6V.
[Link] B efficiency, power dissipation.
If power input is Pin, Power output Po is 78% and power dissipation Pd is
22%.
Current drawn from supply is pulsating. Looks like half wave waveform. If
peak current in load is Ip, current in power supply is halfwave sine with peak
value of Ip. Average of this is Ip/π.
With supply as Ip*RL in ideal case, Power output is (Ip*RL)*(Ip)/2, while Pin =
2*(Ip*RL)*(Ip/π.). Thus efficiency = π/4 = 78%, in ideal case.
Power dissipation is not max when power output is max!! Pd is higher at
output power of 50% rated power. This occurs when peak voltage across load
is 70.7% of supply voltage, in ideal case. Pd at half rated power output is 50%
higher than Pd at rated power output.
Calculate for 8W into 8 ohms. Supply is +/-11.3V. Supply current at 8W output
= .45 amp. Pin = 10.17, of which Po is 8W leaving Pd as 2.17W.
At half rated power, supply current is 0.318amp. Pin = 2*11.3*.318= 7.19W, of
which Po is 4W. Thus Pd is 3.19W. This is 47% higher than 2.17W. This is in
ideal case. In practice the max power can be 30 to 40% higher than Pd at
rated power output.
[Link] of heat sink
When power is dissipated, it has to be taken off to ensure than junction
temperature does not rise to a value higher than max allowed value. Heat
sinks may be required. ѲHS = (ΔT/P)-ѲCA, where ΔT is max junction
temperature minus max ambient. If ѲCA is 4degC/Watt, P= 5W, TJmax = 125
deg, TA max is 65 deg, ѲHS = 12-4 = 8degC/watt. It is good practice to
derate, and take TAmax as 10deg higher and TJ max as 10 deg lesser. In that
case, ѲHS will have to be 4 degC/W or lesser. (A 3degC/W heat sink is bigger
than a 4degC/W heat sink!!)
[Link] B protection: current limiting
741: 3 stages.
First stage – simplified schematic
2nd stage: simplified schematic
Final stage. Simplified schematic.
Calculation of currents in various branches.
Calculation of open loop gain
Equivalent circuit representation of three stages.
Filters: First order: amplitude and phase, step response
Second order, Butterworth: realisation. Gain/phase response.
Step response: overshoot of butterworth second order is 4.2%
Zeta for overshootless response is 1. There will be overshoot is zeta is less than
1.
Zeta for maximally flat response is 0.707. For lesser zeta, there will be a peak in
frequency response.
Third order LP, Butterworth: TF.
Feedback and its effects.
723 and its branch currents.
723: estimation of output resistance, and regulation
General op amp configurations:
Inv amplifier, Input resistance, output resistance and gain
Noninv amplifier, 3 parameters.
Input resistance of non inv amplifier,
Diff amplifier, with large input res and high gain
Inv and non inv Schmitt trigger
Precision rectifier, ac to dc conversion. Form factor
Average of half wave recified, full wave rectified.
Filtering of output to get low ripple
Log amplifier
Analog multiplier:
Gilbert’s cell
Transducers: RTD, and thermocouple
Cold junction compensation: Required in thermocouples as it is convenient to
keep cold junction at ambient temperature. Errors are then corrected by
measuring the cold junction temperature (- this can be done using a solid state
temp sensor-) and adding that to temperature interpreted from thermocouple.
RTD has no “cold junction compensation” requirement!!
3 wire RTD: Eliminates need for recalibration when cable to RTD is changed.
RTD linearization: RTD is nonlinear and gives 0.4% error in 0 to 200 degC range.
A two slope amplifier can bring this down to 0.1% error. Instead of a fixed gain of
2000/75.8, one can have two slopes, viz 100/38.5 from 0 to 100 degC and
100/37.3 from 100 degC to 200 degC. Note that 37.3 = 75.8-38.5
LVDT, signal conditioning.
Communication topics: RS 232, RS485. Driver requirements, length , data rate.
Signal at receiver
Digital topics: Synchronous and asynchronous flip flops, problem of “racing”.
Combinational and sequential circuits.
Set up time, hold time and propagation delay.
Karnoughs map.