Madhav Institute of Technology & Science, Gwalior (M. P.
)
Department of Electronics Engineering
List of Practicals
1. To Verify the Truth Table of “Basic Logic Gates” (i.e. AND, NAND, NOR, OR, EX-
OR, INVERTER) using IC’s.
2. To construct the Basic Gate using Universal Gate.
3. To Verify the Truth Table of “Half Adder and Full Adder”.
4. To Verify the Truth Table of “Half Subtractor and Full Subtractor”.
5. To Verify the Demorgan’s Theorem.
6. To Verify D – Latch / Flip Flop operation.
7. To Verify R-S Flip Flop operation.
8. To Verify J-K Flip Flop operation.
9. To Verify Parity generator / checker circuit.
Additional Experiments
1. To verify the operation of 4×1 multiplexer using 74LS153 Multiplexer IC.
2. To verify the operation of 3×8 decoder using 74138 decoder IC.
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
Course Objectives:
To understand the concept of Digital design and analyze combinational and sequential logic circuits.
Course Outcomes:
CO 1 Verify the operation of basic logic gates and Demorgan’s theorem using standard combinational
logic.
CO 2 Construct the basic logic gates by using universal logic gates.
CO 3 Develop combinational circuits by using their truth table and verify their operation.
CO 4 Verify the operation of sequential circuits.
CO 5 Develop the ability of working in team / group and learn professional ethics.
CO 6 Handle the instruments such as multimeters, function generator and CRO properly.
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
To Verify the truth table of “Half Adder and Full Adder”.
To Verify the truth table of “Half Adder Subtractor and Full Subtractor”.
To Verify Demorgan’s Theorem
VIVA QUESTIONS
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
Q1. What do you mean by Logic Gates?
Q2. What are the applications of Logic Gates?
Q3. What is Truth Table?
Q4. Why we use basic logic gates?
Q5. Realize the following switching function using a multilevel gate network
Y=A+(B+C’) (DE+F’)
Q6. F = XY+X’Y’+Y’Z
(a) Implement it with AND, OR and NOT gates.
(b) Implement it with only OR and NOT gates.
(c) Implement it with only AND, OR and NOT gates.
VIVA QUESTIONS
Q1. Why it is called Universal Logic gates.
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
Q2. Realise Y = A+BCD’
Q3. Realise Y = (A+C)(A+D’)(A+B+C’) using NOR gates.
Q4. Implement Y = (A+B)’+A+(B+C)’
VIVA QUESTIONS
Q1. Define half adder and full adder.
Q2. Design half adder using NAND gate only.
Q3. Write drawback of half and full adder.
Q4. Design a combinational circuit whose input is a four bit number and at the output we obtain the two’s
complement of the input.
VIVA QUESTIONS
Q1. What are the advantage of half subtractor and full subtractor?
Q2. Which logic gates are used to form a half subtractor circuit?
Q3. Name the IC’s that are required for verifying the truth table of half subtractor.
Q4. Design half subtractor using only basic logic gates.
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
VIVA QUESTIONS
Q1. Prove Demorgan’s Theorem using Boolean algebra
(a) (A+B)’ = A’B’
(b) (AB)’ = A’+B’
Q2. Solve by using Demorgan’s theorem
(a) (AB+BC+CA)’ = A’B’+B’C’+C’A’
(b) {(AB)’+A’+AB}’= 0
VIVA QUESTIONS
Q1. Give reason why D-flip flop is called data latch?
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
Q2. Design D-flip flop from S-R flip flop.
Q3. What is the advantage of D-flip flop over on S-R flip flop?
Q4. Draw the logic diagram of Master-Slave D-flip flop using NAND gates.
VIVA QUESTIONS
Q1. Show the logic diagram of a clocked S-R flip flop with four NAND gates.
Madhav Institute of Technology & Science, Gwalior (M. P.)
Department of Electronics Engineering
Q2. Design S-R to J-K flip flop.
Q3. Explain Master Slave S-R flip flop.
Q4. Explain S-R flip flop using NOR gates.
VIVA QUESTIONS
Q1. Explain the working of Master slave J-K flip flop.
Q2. Draw the circuit of J-K flip flop using NAND gates.
Q3. Explain Race around condition.
VIVA QUESTIONS
Q1. What is parity bit?
Q2. What do you mean by even and odd parity generator?
Q3. What is the difference between parity checker and parity generator?
Q4. Design a 6 bit odd and even parity using IC-74180.