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Huffman Encoder and Decoder FSM Design

Huffman encoding and decoding are based on finite state machines (FSMs). The document describes Huffman encoders and decoders for 4 symbols with assigned codes. It provides details on the FSM implementation including states, inputs, outputs, and transitions between states to encode or decode a serial bit input according to the Huffman codes. Code examples are given for both the Huffman encoder and decoder as FSM implementations.

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Nidhi Goel
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26 views3 pages

Huffman Encoder and Decoder FSM Design

Huffman encoding and decoding are based on finite state machines (FSMs). The document describes Huffman encoders and decoders for 4 symbols with assigned codes. It provides details on the FSM implementation including states, inputs, outputs, and transitions between states to encode or decode a serial bit input according to the Huffman codes. Code examples are given for both the Huffman encoder and decoder as FSM implementations.

Uploaded by

Nidhi Goel
Copyright
© Attribution Non-Commercial (BY-NC)
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

huffman encoder and decoder are based on fsm's.

four symbols s1-00,s2-01,s3-10,s4-11 with prob 0.5,0.25,0.125,0.125 are assumed with


huffman codes 1,01,000,001. the input is 2 bit vector. output is 1 bit at a time. the fsm is self
explanantory in code. s3,s5,s6,s8,s9 are redundant states that the machine has to go to so that
output can be obtained for each case.u hav to assume the codes here.

huffman decoder
input comes serially. if we get a '1', then it is symbol s1 and output1 goes [Link] not, then we
go to next state state1. if we get a '1' now, it means 01 and so we get s2 and output2 goes hig.
else, machine goes in state2. here, if we get a '0' then 000 means s3 and so output3 goes high.
else output4 goes high and maachine goes back to state0.

--huffman encoder
entity huffenc is
port(input:in std_logic_vector(1 downto 0);
      output: out std_logic;
      rst,clk:in std_logic);
end entity;

architecture huffenc of huffenc is


type state is(state0,state1,state2,state3,state4,state5,state6,state7,state8,state9);
signal pstate,nstate:state;
begin
process(clk,rst)
begin
if rst='1' then
pstate<=state0;
elsif clk'event and clk='1' then
pstate<=nstate;
end if;
end process;

process(input,clk)
begin
case pstate is
when state0=>
if input="00" then 
nstate<=state1;
elsif input="01" then
nstate<=state2;
elsif input="10" then
nstate<=state4;
elsif input="11" then
nstate<=state7;
end if;

when state1=>
output<='1';
nstate<=state0;

when state2=>
output<='0';
nstate<=state3;

when state3=>
output<='1';
nstate<=state0;

when state4=>
output<='0';
nstate<=state5;

when state5=>
output<='0';
nstate<=state6;

when state6=>
output<='0';
nstate<=state0;

when state7=>
output<='0';
nstate<=state8;

when state8=>
output<='0';
nstate<=state9;

when state9=>
output<='1';
nstate<=state0;

end case;
end process;
end architecture;

--huffdec
entity huffdec is
port(input:in std_logic;
      output1: out std_logic;
      output2:out std_logic;
      output3:out std_logic;
      output4:out std_logic;
      rst,clk:in std_logic);
end entity;
architecture huffenc of huffenc is
type state is(state0,state1,state2);
signal pstate,nstate:state;
begin
process(clk,rst)
begin
if rst='1' then
pstate<=state0;
elsif clk'event and clk='1' then
pstate<=nstate;
end if;
end process;

process(input,clk)
begin
output1<='0';output2<='0';output3<='0';output4<='0';
case pstate is
when state0=>
if input='1' then 
nstate<=state0;
output1<='1';
else nstate<=state1;
end if;

when state1=>
if input='1' then 
nstate<=state0;
output2<='1';
else nstate<=state2;
end if;

when state2=>
if input='0' then 
output3<='1';
else output4<='1';
end if;
nstate<=state0;

end case;
end process;
end arhitecture;

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