•t'C. 15.

1 Simple PLL 533

Phase
Detector ~--~-..• Vout ( t)

Figure 15.1 Definition of phase detector.

Figure 15.2 Exclusive OR gate as phase detector.

error pulses on both rising and falling edges, other types of PD may respond only to positive
or negative transitions.

Example 1 5 . 1 - - - - - - - - - - - - - - - - - - - - - -
If the output swing of the XOR in Fig. 15.2 is Vo volts, what is the gain of the circuit as a phase
detector? Plot the input-output characteristic of the PD.
Solution
If the phase difference increases from zero to 6.¢ radians, the area under each pulse increases by
Vo ·11¢. Since each period contains two pulses, the average value rises by 2[Vo ·f1¢/(2n)], yielding
a gain of Vo/n. Note that the gain is independent of the input frequency.
To construct the input-output characteristic, we examine the circuit's response to various input
phase differences. As illustrated in Fig. 15.3, the average output voltage rises to [Vo/n] x 1r / 2 = Vo/2
for /1¢ = 1r /2 and Vo for 6.¢ = 1r. For /1¢ > 1r, the average begins to drop, falling to Vo/2 for
/1¢ = 3n /2 and zero for /1¢ = 2n. The characteristic is therefore periodic, exhibiting both negative
and positive gains.

The operation of phase detectors is similar to that of differential amplifiers in that both
sense the difference between the two inputs, generating a proportional output.

15.1.2 Basic PLL Topology

To arrive at the concept of phase locking, let us consider the problem of aligning the output
phase of a VCO with the phase of a reference clock. As illustrated in Fig. 15.4(a), the rising
534 Chap. 15 Phase-Locked Loor

v1
v2
Vout

t 6$RS~ t
2

v1
v2
. . ,. - . . f'
! ' '
• ~ - r

Figure 15.3

VcK

Vvco

6t t
(a)

VcK

Vvco
vcont

t1 t2 t
(b)

Figure 15.4 (a) Two waveforms with a skew, (b) change of VCO frequency to eliminate
the skew.
 ·:ec. 15.1 Simple PLL 535

edges of Vv co are "skewed" by /j.t seconds with respect to VcK , and we wish to eliminate
this error. Assuming that the VCO has a single control input, Vconr• we note that to vary the
phase, we must vary the frequency and allow the integration <P = J(Wo + K vco Vcont) dt to
take place. For example, suppose as shown in Fig. 15.4(b), the VCO frequency is stepped to
a higher value at t = t 1. The circuit then accumulates phase faster, gradually decreasing the
phase error. ~t t = t2, the phase error drops to zero and, if Vcont returns to its original value,
Vvc 0 and Vc K remain aligned. Interestingly, the alignment can be accomplished by stepping
the VCO frequency to a lower value for a certain time interval as well (Problem 15.2). Thus,
phase alignment can be achieved only by a (temporary) frequency change.
The foregoing experiment suggests that the output phase of a VCO can be aligned with
the phase of a reference if (1) the frequency of the VCO is changed momentarily, (2) a
means of comparing the two phases, i.e., a phase detector, is used to determine when the
VCO and reference signals are aligned. The task of aligning the output phase of the VCO
with the phase of the reference is called "phase locking."
From the above observations, we surmise that a PLL simply consists of a PD and a VCO
in a feedback loop [Fig. 15.5(a)]. The PD compares the phases of Vout and V;n, generating
an error that varies the VCO frequency until the phases are aligned, i.e., the loop is locked.

v1"~ vcofV•m ;::~ LPF IVcon~~ vcof;::

(a) (b)

Figure 15.5 (a) Feedback loop comparing input and output phases, (b) simple PLL.

This topology, however, must be modified because (1) as exemplified by the waveforms of
Fig. 15.2, the PD output, Vpv, consists of a de component (desirable) and high-frequency
components (undesirable), and (2) as mentioned in Chapter 14, the control voltage of the
oscillator must remain quiet in the steady state, i.e., the PD output must be filtered. We
therefore interpose a low-pass filter (LPF) between the PD and the VCO [Fig. 15.5(b)],
suppressing the high-frequency components of the PD output and presenting the de level to
the oscillator. This forms the basic PLL topology. For now, we assume the LPF has a gain
of unity at low frequencies (e.g., as in a first-order RC section).
It is important to bear in mind that the feedback loop of Fig. 15 .5(b) compares the phases
of the input and output. Unlike the feedback topologies studied in the previous chapters,
PLLs typically require no knowledge of voltages or currents in their feedback operation. If
the loop gain is large enough, the difference between the input phase, </J;11 , and the output
phase, <Pout, falls to a small value in the steady state, providing phase alignment.
l For subsequent analyses of PLLs, we must define the phase lock condition carefully. If
the loop of Fig. 15.5(b) is locked, we postulate that <Pout - <Pin is constant and preferably
small. We therefore define the loop to be locked if <Pout - </J;11 does not change with time.
536 Chap. 15 Phase-Locked Loo1

An important corollary of this definition is that

d</Jout d</Jin _ O
- - -- -- (1 5.
dt dt
and hence

(J)out = (J)in · (15.2

This is a unique property of PLLs and will be revisited more closely later.
In summary, when locked, a PLL produces an output that has a small phase error witl
respect to the input but exactly the same frequency. The reader may then wonder why
PLL is used at all. A short piece of wire would seem to perform the task even better! W•
answer this question in Section 15.5.

Example 15.2 - - - - - - - - - - - - - - - - - - - - " " " '

Implement a simple PLL in CMOS technology.
Solution
Figure 15.6 illustrates an implementation utilizing an XOR gate as the phase detector. The VCO 'n

...,.-----r- ~DD

I-. -.
Figure 15.6

configured as a negative-Gm LC oscillator whose frequency is tuned by varactor diodes.

PLL Waveforms in Locked Condition In order to familiarize ourselves with th~

behavior of PLLs, we begin with the simplest case: the circuit is locked and we wish t
examine the waveforms at each point around the loop. As illustrated in Fig. 15.7(a), V;
and Vout exhibit a small phase difference but equal frequencies. The PD therefore generate1
pulses as wide as the skew between the input and the output1 and the low-pass filter extracL.
the de component of Vpv, applying the result to the VCO. We assume the LPF has a gair
of unity at low frequencies. The small pulses in VLP F are called "ripple."

1In this example, the PD produces pulses only on the rising transitions.
.oc. 15.1 Simple PLL 537

ffiout

n.o....:' :.,_
'+' ' .
1'

t
(a) (b)

Figure 15.7 (a) Waveforms in a PLL in locked condition, (b) calculation of phase error.

In the waveforms ofFig.15.7(a), two quantities are unknown: </>o and the de level of Vcont·
To determine these values, we construct the VCO and PD characteristics [Fig. 15.7(b)].
If the input and output frequencies are equal to w1, then the required oscillator control
voltage is unique and equal to V1• This voltage must be produced by the phase detector,
demanding a phase error determined by the PD characteristic. More specifically, since
Wout = Wo + Kvco Vcont and Vpv = Kpvf::.¢, we can write
Wt -Wo
Vt = (15.3)
Kvco '
and
Vt
¢o=- (15.4)
Kpv
Wt - Wo
(15.5)
KpvKvco
Equation (15.5) reveals two important points: (1) as the input frequency of the PLL varies,
so does the phase error; (2) to minimize the phase error, K p D K v c 0 must be maximized.

Example 1 5 . 3 - - - - - - - - - - - - - - - - - - - - - -
A PLL incorporates a VCO and a PD having the characteristics shown in Fig. 15.8. Explain what
happens as the input frequency varies in the locked condition.
Solution
The PD characteristic is relatively linear near the origin but exhibits a small-signal gain of zero if
the phase difference equals ±rr /2, at which point the average output is equal to ± Vo. Now suppose
 538 Chap. 15 Phase-Locked Loop·

ffiout

I'

Figure 15.8

the input frequency increases from cvo. requiring a greater control voltage. If the frequency is high
enough (= wx) to mandate Vcont = Vo, then the PD must operate at the peak of its characteristic.
However, the PD gain drops to zero here and the feedback loop fails. Thus, the circuit cannot lock if
Win= wx.

I With the basic understanding of PLLs developed thus far, we now return to Eq. (15.2).
The exact equality of the input and output frequencies of a PLL in the locked condition
is a critical attribute. The significance of this property can be seen from two observations.
First, in many applications, even a very small (deterministic) frequency error may prove
unacceptable. For example, if a data stream is to be processed synchronously by a clocked
system, even a slight difference between the data rate and the clock frequency results in a
"drift,'' creating errors (Fig. 15.9). Second, the equality would not exist if the PLL compared
the input and output frequencies rather than phases. As illustrated in Fig. 15.10(a), a loop
employing a frequency detector (FD) would suffer from a finite difference between w1,
and Wout due to various mismatches and other nonidealities. This can be understood by
an analogy with the unity-gain feedback circuit of Fig. 15.10(b). Even if the op amp's

Data

Clock

t
Figure 15.9 Drift of data with respect to clock in the presence of small frequency error.

v,,[Gj H LPF vco r v. ,

(a) (b)

Figure 15.10 (a) Frequency-locked loop, (b) unity-gain feedback amplifier.

')ec 15.1 Simple PLL 539

open-loop gain is infinity, the input-referred offset voltage leads to a finite error between V;n
and Vaut·
Small Transients in Locked Condition Let us now analyze the response of a PLL
in locked condition to small phase or frequency transients at the input.
Consider a PLL in the locked condition and assume the input and output waveforms can
be expressed as

~n(t) =VA COSW1t (15.6)

Vaur(t) = VB cos(w1t + ¢o), (15.7)

where higher harmonics are neglected and ¢o is the static phase error. Suppose, as shown in
Fig. 15.11, the input experiences a phase step of ¢1att = t1, i.e., ¢;n = w1t + ¢Iu(t- t!). 2
Since the output of the LPF does not change instantaneously, the VCO initially continues to

.
'
l l cl>1n
- '.., rf-
4> __!_
$out
(J) 1 :

.
Vpo ____ ......__.iLILII

ffiout

Figure 15.11 Response of a PLL to a phase step.

oscillate at w1. The growing phase difference between the input and the output then creates
wide pulses at the output of the PO, forcing VLP F to rise gradually. As a result, the VCO
frequency begins to change, attempting to minimize the phase error. Note that the loop is
not locked during the transient because the phase error varies with time.

2
In this example, 4ltn and 4lout denote the total phases of the input and output, respectively.
540 Chap. 15 Phase~Locked Lot 11
..
What happens after the VCO frequency begins to change? If the loop is to return to lot I
W0 u1 must eventually go back to WI, requiring that VLPF and hence ¢out - ¢in also rcttn '
to their original values. Since ¢in has changed by ¢I , the variation in the VCO frequency 1
such that the area under Wout provides an additional phase of ¢I in ¢out :
00

1'
1tl
Woutdt = ¢I · ([Link]

Thus, when the loop settles, the output becomes equal to

Vout(t) = VB cos[wit + ¢o + ¢Iu(t- tJ)]. (1 5,Q)

Consequently, as shown in Fig. 15.11, ¢out gradually "catches up" with ¢in ·
It is important to make two observations. (1) After the loop returns to lock, all of tho
parameters (except for the total input and output phases) assume their original values. That II,
¢in- ¢out• VLPF· and the VCO frequency remain unchanged-an expected result becauso
these three parameters bear a one-to-one relationship and the input frequency has stayed
the same. (2) The control voltage of the oscillator can serve as a suitable test point in tho
analysis of PLLs. While it is difficult to measure the time variations of phase and frequency
in Fig. 15.11, Vcont(= VLPF) can be readily monitored in simulations and measurements.
The reader may wonder whether an input phase step always gives rise to the response
shown in Fig. 15 .11. For example, is it possible for VLP F to ring before settling to its final
value? Such behavior is indeed possible and will be quantified in Section 15.1.3.
Let us now examine the response of PLLs to a small input frequency step 6.w at t = t1
(Fig. 15.12). As with the case of a phase step, the V,CO initially continues to oscillate at

(01

v,n

~in

- (01
. ~

.'
'

'
~out

Vout

Vpo

VLPF

CO out

Figure 15.12 Response of a PLL to a small frequency step.

')ec. 15.1 Simple PLL 541

w1• Thus, the PD generates increasingly wider pulses, and VLPF rises with time. As illout
approaches w1 + t'::l.w, the width of the pulses generated by the PD decreases, eventually
settling to a value that produces a de component equal to (w1 + t'::l.w - w0 ) j K vc 0 . In contrast
to the case of phase step, the response of a PLL to a frequency step entails a permanent
change in both the control voltage and the phase error. If the input frequency is varied
slowly, illout !simply "tracks" Win·
The exact settling behavior of PLLs depends on the various loop parameters and will be
studied in Section 15.1.3. But, to arrive at an important observation, we consider the phase
step response depicted in Fig. 15.13, where Vcont rings before settling to its final value.

Figure 15.13 Example of phase step response.

Consider the state of the loop at t = t2 • At this point, the output frequency is equal to its
final value (because Vcont is equal to its final value) but the loop continues the transient
because the phase error deviates from the required value. Similarly, at t = t3, the phase
error is equal to its final value but the output frequency is not. In other words, for the loop
to settle, both the phase and the frequency must settle to proper values.

Example 1 5 . 4 - - - - - - - - - - - - - - - - - - - - - -
Consider the PLL shown in Fig. 15.14, where an external voltage Vex is added to the output of
the low-pass filter.3 (a) Determine the phase error and VLPF if the loop is locked and Vex = V1.
(b) Suppose Vex steps from V1 to V2 at t = t1. How does the loop respond?
Solution
(a)Iftheloopislocked,wout =Win and Vcont =(Win -wo)/K vco. Thus, VLP F = (w;n·-wo)/ K vco-
VI and~¢= VLPF/Kpv =(Win- wo)/(KpvKvco)- V1 / KPD·
(b) When Vex steps from V1 to V2, Vcont immediately goes from (win - wo)/ Kvco to (Win-
wo)/Kvco + CV2- VJ), changing the VCO frequency to Win- KvcoCVJ- V2). Since VLPF
cannot change instantaneously, the PD begins to generate increasingly wider pulses, raising VLP F
and increasing Wout· When the loop returns to lock, Wout becomes equal to Win and VLPF =(Win-
wo)/ K vco- V2. The phase error also changes to (win- wo)/(K pDK vco)- V2/ K pD· Note that the

3This topology is used for some types of frequency modulation in wireless communication.
 542 Chap. 15 Phase-Locked Loo1•

v,n
v1
Vex
I
Vout

ffiout

I VLPF
. . .. . .. . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +.
-~Jl~~~~::::::::::::~==~~~~~~==~:~-~
t

Figure 15.14

area under Wout during the transient is equal to the change in the output phase and hence the chango
in the phase error:
oo V1- Vz
[ Wourdt = . (15.10) '
11 Kpv

From our study thus far, we conclude that phase-locked loops are "dynamic" systems,
i.e., their response depends on the past values of the input and output. This is to be expected
because the low-pass filter and the VCO introduce poles (and possibly zeros) in the loop
transfer function. Moreover, we note that, so long as the input and the output remain
perfectly periodic (i.e., <Pin = Wint and <Pout = W;nt + </Jo), the loop operates in the steady
state, exhibiting no transient. Thus, the PLL only responds to [Link] the excess phase
of the input or output. For example, in Fig. 15.11, <Pin = w 1t + ¢ 1u(t- t,) and in Fig. 15.12,
<Pin = w,t + tlw · tu(t---:- t,).

15.1.3 Dynamics of Simple PLL

With the qualitative analysis of PLLs in the previous section, we can now study their
transient behavior more rigorously. Assuming the loop is initially locked, we treat the
PLL as a feedback system but recognize that the output quantity in this analysis must be ·
')ec. 15.1 Simple PLL 543

the (excess) phase of the VCO because the "error amplifier" can only compare phases. Our
objective is to determine the transfer function <l>0111 (s )I <l>;n(s) for both open-loop and closed-
loop systems and subsequently study the time-domain response. Note that the dimensions
change from phase to voltage through the PD and from voltage to phase through the VCO.
What does <l>0111 (s)l <l>;n(s) signify? An analogy with more familiar transfer functions
proves useful here. A circuit having a transfer function V0111 (s)IV;n(s) = 11(1 + sl wo) is
considered a low-pass filter because if V;n varies rapidly, Vour cannot fully track the input
variations. Similarly, <l> 0111 (s)l<l>;n(s) reveals how the output phase tracks the input phase if
the latter changes slowly or rapidly.
To visualize the variation of the excess phase with time, consider the wavefonns in
Fig. 15.15. The period varies slowly in Fig. 15.15(a) and rapidly in Fig. 15.15(b). Thus,
y2(t) experiences faster phase variation than does Y2(t).

(a)

v.(t) l11R:Puru1nJl::Pc r
(b)

Figure 15.15 Slow and fast variation of the excess phase.

Let us construct a linear model of the PLL, assuming a first-order low-pass filter for
simplicity. The PD output contains a de component equal to K p v (<Pout - ¢; n) as well as high-
frequency components. Since the latter are suppressed by the LPF, we simply model the PD
by a subtracter whose output is "amplified" by Kpv. Illustrated in Fig. 15.16, the overall
PLL model consists of the phase subtracter, the LPF transfer function 1I (1 +sI wLP F),

PD LPF vco

Kvco
s
:..................................... .. :

Figure 15.16 Linear model of type I PLL.

where WLPF denotes the -3-dB bandwidth, and the VCO transferfunction Kvcols. Here,
<l>;n and <Pour denote the excess phases of the input and output waveforms, respectively. For
example, if the total input phase experiences a step change, ¢ 1u(t), then <l>;n(s) = ¢J/s.
544 Chap. 15 Phase-Locked Loo1'

The open-loop transfer function is given by

<l> out
H(s)lopen = ~(s)lopen (15.111
"'1n
1 Kvco
= Kpv. s (15.1.' 1
1+- s
WLPF

revealing one pole at s = -WLPF and another at s = 0. Note that the loop gain is equaltu
H(s)lopen because of the unity feedback factor. Since the loop gain contains a pole at th~
origin, the system is called "type I."
Before computing the closed-loop transfer function, let us make an important observu
tion. What is the loop gain if s is very small, i.e., if the input excess phase varies very slowly? ,
Owing to the pole at the origin, the loop gain goes to infinity as s approaches zero, a point
of contrast to the feedback circuits studied in Chapters 8 and 10. Thus, the phase-locked
loop (under closed-loop, locked condition) ensures that the change in <Pout is exactly equal
to the change in </J;n as s goes to zero. This result predicts two interesting properties or
PLLs. First, if the input excess phase varies very slowly, the output excess phase ''tracks"
it. (After all, <Pout is "locked" to </J;n.) Second, if the transients in </J;n have decayed (anothor 1
case corresponding to s ~ 0), then the change in <Pout is precisely equal to the change in
<Pin· This is indeed true in the example depicted in Fig. 15.11.
From (15.12), we can write the closed-loop transfer function as:

KpvKvco
H(s)lciosed = --=-
2- - - - - - -
(15.13)
s
- - +s + KpvKvco
WLPF

For the sake of brevity, we hereafter denote H(s)lclosed simply by H(s) or <l>ourf<l>;n . A~
expected, if s ~ 0, H (s) ~ 1 because of the infinite loop gain.
In order to analyze H (s) further, we derive a relationship that allows a more intuitive
understanding of the system. Recall that the instantaneous frequency of a waveform is equal
to the time derivative of the phase: w = d¢1dt. Since the frequency and the phase are related
by a linear operator, the transfer function of (15.13) applies to variations in the input and
output frequencies as well:

(15.1 4)

For example, this result predicts that if W;n changes very slowly (s ~ 0), then W0111 tracks
Wi 11 , again an expected result because the loop is assumed locked. Equation (15.14) also
indicates that if W;n changes abruptly but the system is given enough time to settle (s ~ 0),
then the change in Wout equals that in W; 11 (as illustrated in the example of Fig. 15.12).
The above observation aids the analysis in two directions. First, some transient responses
of the closed-loop system may be simpler to visualize in terms of changes in the frequency
quantities rather than phase quantities. Second, since a change in w0111 must be accompanied
Sec. 15.1 Simple PLL 545

by a change in Vcant, we have

Vcont
H ( s) = Kvco · -(s). (15.15)
Win

That is, monitoring the response of Vcant to variations in Win indeed yields the response of
the closed-loop system.
The second-order transfer function of (15.13) suggests that the step response of the type I
system can be overdamped, critically damped, or underdamped. To derive the condition for
each case, we rewrite the denominator in a familiar form used in control theory, s2 +2{ w11 s +
w~, where { is the "damping ratio" and w11 is the "natural frequency." That is,

(15.16)

where

(15.17)

1 WLPF
{=- (15.18)
2 KpDKvco

The two poles of the closed-loop system are given by

s1,2 = -{wn ± J({ 2- 1)w; (15.19)

= (-{ ± J{2 - 1)wn. (15.20)

Thus, if { > 1, both poles are real, the system is overdamped, and the transient response
contains two exponentials with time constants 1Is 1 and 1Is2• On the other hand, if { < 1,
the poles are complex and the response to an input frequency step Win = Llwu(t) is equal
to

Wauc(t) = 11 - e-tw.t[cos(wn/1 - { 2 t) + {
)1- {2
sin(w11 )1 - { 2 t)]) Llwu(t) (15.21)
1· ,---
= [1 - e-twnt sin(wnJ1 - { 2 t + ())]Llwu(t), (15.22)
)1- {2

where Waut denotes the change in the output frequency and() = sin- 1 )1- {2 • Thus, as
shown in Fig. 15.17, the step response contains a sinusoidal component with a frequency
w11 )1 - ~ 2 that decays with a time constant ({w11 ) - 1 . Note that the system exhibits the
same response if a phase step is applied to the input and the output phase is observed.
The settling speed of PLLs is of great concern in most applications. Equation (15.22)
indicates that the exponential decay determines how fast the output approaches its final
546 Chap. 15 Phase-Locked Loo,

(J) out

Figure 15.17 Underdamped response

t of PLL to a frequency step.

value, implying that ~wn must be maximized. For the type I PLL under study here, (15.17)
and (15.18) yield

(15.23)

This result reveals a critical trade-off between the settling speed and the ripple on the VCO
control line: the lower WLP F, the greater the suppression of the high-frequency components
produced by the PD but the longer the settling time constant.

Example 1 5 . 5 - - - - - - - - - - - - - - - - - - - - - -
A cellular telephone incorporates a 900-MHz phase-locked loop to generate the carrier frequencies.
If WLP F = 2Jr x (20kHz) and the output frequency is to be changed from 901 MHz to 901.2 MHz,
how long does the PLL output frequency take to settle within 100 Hz of its final value?
Solution
Since the step size is 200 kHz, we have

(15.24)

Thus,
e-tw. t, sin(w G t + () ) = _200
n V1 - ~ ~ s
1_00_H_z
kHz . (15.25)

In the worst case, the sinusoid is equal to unity and

(15.26)
That is,
7.6
ts = - (15.27)
~ Wn

15.2
= (15.28)
WLPF

= 0.1 2 ms. (15.29)

Sec. ~5.1 Simple PLL 547

~ :0.2

t
Figure 15.18 Underdamped response of a second-order
system for various values of ~.

In addition to the product ~ Wn, the value of ~ itself is also important. lllustrated in
Fig. 15.18 for several values of ~ and a constant cvn, the step response exhibits severe
ringing for ~ < 0.5. In view of process and temperature variation of the loop parameters,
~ is usually chosen to be greater than J2;2 or even 1 to avoid excessive ringing.4
The choice of~ entails other trade-offs as well. First, (15.18) implies that as WLP F is
reduced to minimize the ripple on the control voltage, the stability degrades. Second, (15.5)
and (15.18) indicate that both the phase error and~ are inversely proportional to KpvKvco;
lowering the phase error inevitably makes the system less stable. In summary, the type I
PLL suffers from trade-offs between the settling speed, the ripple on the control voltage
(i.e., the quality of the output signal), the phase error, and the stability.
The stability behavior of PLLs can also be analyzed graphically, providing more insight.
Recall from Chapter 10 that the Bode plots of the magnitude and phase of the loop gain
readily yield the phase margin. Let us utilize (15.12) to construct such plots. As shown in
Fig. 15.19, the loop gain begins from infinity at cv = 0 and falls at a rate of 20 dB/dec for
cv < WLP F and at a rate of 40 dB/dec thereafter. The phase begins at -90° and asymptotically
reaches -180°.
What happens if a higher KpvKvco is chosen so as to minimize ¢our - tPin? Since
the entire gain plot in Fig. 15.19 is shifted up, the gain crossover moves to the right, thus
degrading the phase margin. This is consistent with the dependence of~ upon KpvK vco .
As observed thus far, KpDKvco impacts many important parameters of PLLs. This
quantity is sometimes called the loop gain (even though it is not dimensionless) due to the
resemblance of A¢ = (cvout- evo)/(KpDKvco) to the error equation in a feedback system.
The stability behavior of type I PLLs can also be analyzed by the locus of their poles in
the complex plane as the parameter KpvKvco varies (Fig. 15.20). With KpvKvco = 0,

4
s s
The value of may also yield peaking in the transfer function. Thus, some applications require a of 5 to 10
to avoid peaking in the presence of higher order poles.
548 Chap. 15 Phase-Locked l <'L'I

201og IH open I

I'

ro LPF ro (log scale)

ro (log scale)
0-4-_ _ ___._ _ _ _....._
0
-900 ~------
-135 ··················
-180° ......................~
..
!!'Po.- -

/..!!_open

Figure 15.19 Bode plots of type I PLL.

j(O

Figure 15.20 Root locus of type I

PLL.

the loop is open, ~ = oo, and the two poles are given by s1 = -WLPF and s2 = 0. A ~
K PDK vco increases (i.e., the feedback becomes stronger),~ drops and the two poles, given
by s1,2 = (-~ ± ../~ 2 - l)wn, move toward each other on the real axis. For~ = 1 (i.e.,
KpDKvco = WLPF/4), s1 = sz = -~wn = -WLPF/2. As KPDKvco increases further,
the two poles become complex, with a real part equal to -~wn = -WLPF/2, moving in
parallel with the jw axis.
We recognize from Fig. 15.20 that, as s 1 and s2 move away from the real axis, the system
becomes less stable. In fact, the reader can prove ~hat cos cp = ~ (Problem 15.8), concluding
that as cp approaches 90°, ~ drops to zero.
Another transfer function that reveals the settling behavior of PLLs is that of the error at
the output of the phase subtractor in Fig. 15.16. Defined as He(s ) = (¢in - cl>our)/c/>i 11 , this
transfer function can be obtained by noting that cl>out! ¢in = H (s) and, from (15.13),

He(s) = 1- H(s) (15.30)

s 2 + 2~WnS
(15.31)
s 2 + 2~ WnS + Wn .
Sec. 15.2 Charge-Pump Plls 549

As expected, He (s) ~ 0 if s ~ 0 because the output tracks the i11put when the input varies
very slowly or the transient has settled.

Example 1 5 . 6 - - - - - - - - - - - - - - - - - - - - - - -
Suppose a type I PLL experiences a frequency step b.w at t = 0. Calculate the change in the phase
error.
Solution
The Laplace transfonn of the frequency step equals b.w1s. Since He(s) relates the phase error to the
input phase, we write <l>;n(s) = (!lwjs)js = [Link] 2 . Thus, the Laplace transfonn of the phase error is

<l>e(s) = He(s) · -b.w

s2
(15.32)

s2 + 2~ WnS !lw
(15.33)
= s2 + 2~WnS + w; . --;2 ·

From the final value theorem,

<Pe(t = oo) = s--+0

lim s<l>e(s) (15.34)

2s
= -/l(J) (15.35)

(15.36)
- KpvKvco '

which agrees with (15.5).

15.2 Charge-Pump PLLs

While type I PLLs have been realized widely in discrete fonn, their shortcomings often
prohibit usage in high-performance integrated circuits. In addition to the trade-offs between
s, w LP F, and the phase error, type I PLLs suffer from another critical drawback: limited
acquisition range.

15.2.1 Problem of Lock Acquisition

Suppose when a PLL circuit is turned on, its oscillator operates at a frequency far from the
input frequency, i.e., the loop is not locked. Under what conditions does the loop "acquire"
lock? The transition of the loop from unlocked to locked condition is a very nonlinear
phenomenon because the phase detector senses unequal frequencies. The problem of lock
acquisition in type I PLLs has been studied extensively [1, 2], but we state without proof
550 Chap. 15 Phase-Locked Loop:.

that the "acquisition range"5 is on the order of WLPF· that is, the loop locks only if th('
difference between Win and Wour is less than roughly w LP F. 6
The problem of lock acquisition further tightens the trade-offs in type I PLLs. If wLP F is
reduced to suppress the ripple on the control voltage, the acquisition range decreases. Note
that even if the input frequency has a precisely controlled value, a wide acquisition range
is often necessary because the VCO center frequency may vary considerably with process
and temperature. In most of today's applications, the acquisition range of the simple PLL
studied thus far proves inadequate.
In order to remedy the acquisition problem, modem PLLs incorporate frequency detec-
tion in addition to phase detection. Called "aided acquisition" and illustrated in Fig. 15.21,
the idea is to compare Win and Wout by means of a frequency detector, generate a de com-

...
·····-·········· ·················
!:.... .... .........................................
Phase Feedback
. ...
~
l
Vout
.,__ _ _-1 vco ....--1
······-·········---.·················,
: Frequency Feedback :
:.................. ..... ~ ................... :
Figure 15.21 Addition of frequency
detection to increase the acquisition
range.

ponent VLPF2 proportional to Win - Wout. and apply the result to the VCO in a negative-
feedback loop. At the beginning, the FD drives Wout toward Win while the PD output remains
"quiet." When lwout - Win I is sufficiently small, the phase-locked loop takes over, acquiring
lock. Such a scheme increases the acquisition range to the tuning range of the VC0. 7

15.2.2 Phase/Frequency Detector and Charge Pump

For periodic signals, it is possible to merge the two loops of Fig. 15.21 by devising a circuit
that can detect both phase and frequency differences. Called a phase/frequency detector
(PFD) and illustrated conceptually in Fig. 15.22, the circuit employs sequential logic to
create three states and respond to the rising (or falling) edges of the two inputs. If initially
QA = Qs = 0, then arising transition on A leads to QA = 1, Q8 = 0. The circuit remains

5Acquisition range, tracking range, lock range, capture range, and pull-in range are often used to describe the
behavior of PLLs in the presence of input or VCO frequency variation. For our purposes, the acquisition range,
the capture range, and the pull-in range are the same. The tracking range refers to the input frequency range across
which a locked PLL can track the input. With the addition of frequency detection, the acquisition range becomes
equal to the tracking range (for periodic signals). ·
6This is a very rough estimate. In practice, the acquisition range may be several times narrower or wider. It is

also assumed that the tuning range of the VCO is large enough not to limit the acquisition range.
7
This may not be true if the input is not periodic.
Sec. 15.2 Charge-Pump PLLs 551

A QA

B Os

$A #$s 00A# 00 s
A A

B B

aAJ n n n QA
Os Os

t t
(a) (b)

Figure 15.22 Conceptual operation of aPFD.

in this state until B goes high, at which point QA returns to zero. The behavior is similar
for the B input. '
In Fig. 15.22(a), the two inputs have equal frequencies but A leads B. The output QA
continues to produce pulses whose width is proportional to ¢A - ¢ 8 while Q 8 remains at
zero. In Fig. 15.22(b), A has a higher frequency than Band QA generates pulses while Q 8
does not. By symmetry, if A lags B or has a lower frequency than B, then Q8 produces
pulses and QA remains quiet. Thus, the de contents of Q A and Q8 provide information
about ¢A - ¢ B or wA - wB. The outputs QA and Q8 are called the "UP" and "DOWN"
pulses, respectively.

Example 15.7 -----------~---------

Explain whether a master-slave D flipflop can operate as a phase detector or a frequency detector.
Assume the flipflop provides differential outputs.
Solution
As shown in Fig. 15.23(a), we first apply inputs having equal frequencies and a finite phase difference,
assuming the output changes on the rising edge of the clock input. If A leads B, then Vout remains at a
logical ONE indefinitely because the flipflop continues to sample the high levels of A. Conversely, if
A lags B, then Vout remains low. Plotted in Fig. 15 .23(b), the input-output characteristic of the circuit
displays a very high gain at A¢ = 0, ±n, · · · and a zero gain at other values of A¢. The D flipflop
is sometimes called a "bang-bang" phase detector to emphasize that the average value of Vout jumps
from - V1 to +V1 as A¢ varies from slightly below zero to slightly above zero.
 552 Chap. 15 Phase-Locked Lo< 11

Now let us assume unequal frequencies for A and B. If the flipflop is to behave u
a frequency detector, then the average value of V0 u1 must exhibit different polarities lor
WA > w8 and WA < w8 . However, as illustrated in Fig. 15.23(c), the average value is ZC i o
in both cases.
The circuit of Fig. 15.22 can be realized in various forms. Figure 15.24(a) shows u
simple impJementation consisting of two edge-triggered, resettable D ftipftops with thoh
D inputs tied to a logical ONE. The inputs of interest, A and B, serve as the clocks of th
flipftops. If QA = Q8 = 0 and A goes high, QA rises. If this event is followed by a risin~
transition on B, Q8 goes high and the AND gate resets both fiipflops. In other words, QA
and Q 8 are simultaneously high for a short time but the difference between their averago
values still represents the input phase or frequency difference correctly. Each flipflop can bo
implemented as shown in Fig. 15.24(b), where two RS latches are cross-coupled. Latch J
and Latch 2 respond to the rising edges of CK and Reset, respectively.

A D Q

8 CK Q

----------····+ v1
---------····-V1
t t
(a)

A
Time Average
of Vout 8

Vout

-1t 0 1t Ll$ A

Vout

t
(b) (c)

Figure 15.23 (a) D flipflop as a phase detector, (b) input/output characteristic, (c) response of D flipflop to unequal input
frequencies.
Sec. 15.2 Charge-Pump PLLs 553

VDD r'"'" ..... .. ................. ....... •

CK~:-~ Latch 1
D A
Q QA
CK
I' 8
Reset
QA
..
CK .
Q Os ..:
D Os
I I I I Latch
.
I

21•. .. ..................... ..... ···'. Reset

VDD t

(a) (b)

Figure 15.24 (a) Implementation of PFD, (b) implementation of D flipflop.

Example 1 5 . 8 - - - - - - - - - - - - - - - - - - - - - - - -
Determine the width of the narrow reset pulses that appear in the Qs waveform in Fig. 15.24(a).
Solution
Figure 15.25(a) illustrates the overall PFD at the gate level. If the circuit begins with A= 1, QA = 1,
and Qs = 0, a rising edge on B forces Q8 to go low and, one gate delay later, QB to go high. As

Os
Oa
A 8

Reset

E
.·~
t · I I I I ;t
E • -:· : / 1
:====~~
•=t'. ,.,.:.:.:
t' I

QA
·..
.. . .:i
I :

\~t:.:· /

(a)
F

F _ __.·=r (b)

Figure 15.25
554 Chap. 15 Phase-Locked LtuJI•

shown in Fig. 15.25(b), this transition propagates to Reset, E, E, QA, Reset, F, F, and Qn. ll11•
the width of the pulse on Q B is approximately equal to 10 gate delays. 8

It is instructive to plot the input-output characteristic of the above PFD. Defining th•
output as; the difference between the average values of QA and Q8 when WA = wo llllll
neglecting the effect of the narrow reset pulses, we note that the output varies symmetricall
as IL\¢1 begins from zero (Fig. 15.26). For L\¢ = ±360°, Vout reaches its maximum 01
minimum and subsequently changes sign.

Vout

Figure 15.26 Input-output characteristic of the three-

state PFD.

How is the PFD of Fig. 15.24(a) utilized in a phase-locked loop? Since the difference
between the average values of QA and Q8 is of interest, the two outputs can be low-pass
filtered and sensed differentially (Fig. 15.27). However, a more common approach is to
interpose a "charge pump" (CP) between the PFD and the loop filter.

D
Q
A CK

Reset
I-. Vout

B CK
Q
0

I-.
Figure 15.27 PFD followed by low-pass filters.

A charge pump consists of two switched current sources that pump charge into or out of
the loop filter according to two logical inputs. Figure 15.28 illustrates a charge pump driven
by a PFD and driving a capacitor. The circuit has three states. If QA = Q8 = 0, then S1

8
This is a rough approximation because the NAND gate, the inverter, and the NOR gates have different delays
and fanouts.
0ec. 15.2 Charge-Pump Plls 555

Voo
A
/1
D QA B
A CK Q

Reset Vout

ICp
;:.- -.
B CK Q
D Os
,
[Link] ...../,._..J,-
_..r--''
. t

Figure 15.28 PFD with charge pump.

and S2 are off and Vout remains constant. If QA is high and QB is low, then I 1 charges C p.
Conversely, if QA is low and Q 8 is high, then h discharges Cp. Thus, if, for example, A
leads B, then QA continues to produce pulses and Vout rises steadily. Called UP and DOWN
currents, respectively, I 1 and h are nominally equal.

Example 1 5 . 9 - - - - - - - - - - - - - - - - - - - - -
What is the effect of the narrow pulses that appear in the QB waveform in Fig. 15.28?
Solution
Since QA and QB are simultaneously high for a finite period (approximately 10 gate delays from
Example 15.8), the current supplied by the charge pump to Cp is affected. In fact, if h = h the
current through S1 simply flows through S2 during the narrow reset pulse, leaving no current to charge
Cp. Thus, as shown in Fig. 15.29, Vout remains constant after Qs goes high.
556 Chap. 15 Phase-Locked Loo, ,

The circuit of Fig. 15.28 has an interesting property. If A , say, leads B by a finite amOLIIII
QA produces pulses indefinitely, allowing the charge pump to inject h into C p and forcinJ
Vout to rise steadily. In other words, for a finite input error, the output eventually goes 111
+oo or -oo, i.e., the "gain" of the circuit is infinity. The consequences of infinite gain <111
described below.

15.2.3 Basic Charge-Pump PLL

Let us now construct a PLL using the circuit of Fig. 15.28. Shown in Fig. 15.30 and callecl
a charge-pump PLL, such an implementation senses the transitions at the input and output,

Voo
/1
D QA
Vin
CK Q
~In
Win Vcont Vout
Reset vco
~out
Wout
CK
-.
f:.-
Q
D Os

.
Figure 15.30 Simple charge-pump PLL.

detects phase or frequency differences, and activates the charge pump accordingly. When
the loop is turned on, Wout may be far from W;n, and the PFD and the charge pump vary the
control voltage such that Wout approaches Win. When the input and output frequencies arc
sufficiently close, the PFD operates as a phase detector, performing phase lock. The loop
locks when the phase difference drops to zero and the charge pump remains relatively idle.
As observed above, the gain of the PFD/CP combination is infinite, i.e., a nonzero
(deterministic) difference between ¢in and <Pout leads to indefinite charge buildup on C p .
What is the consequence of this attribute in a charge-pump PLL? When the loop ofFig. 15.30
is locked, Vcont is finite. Therefore, the input phase error must be exactly zero. 9 This is in
contrast to the behavior of the type I PLL, in which the [Link] is finite and a function
of the output frequency.
To gain more insight into the operation of the PLL shown in Fig. 15.30, let us ignore
the narrow reset pulses on QA and Q8 and assume that after <Pout - ¢in drops to zero,
the PFD simply produces QA = Qs = 0. The charge pump thus remains idle and Cp
sustains a constant control voltage. Does this mean that the PFD and the CP are no longer
needed?! If Vconr remains constant for a long time, the VCO frequency and phase begin to

9As explained in Section 15.3.1, mismatches still yield a finite phase error.
:-lee. 15.2 Charge-Pump PLLs 557

drift. In particular, the noise sources in the VCO create random variations in the oscillation
frequency that can result in a large accumulation of phase error. The PFD then detects
the phase difference, producing a corrective pulse on QA or Q 8 that adjusts the VCO
frequency through the charge pump and the filter. This is why we stated earlier that the
PLL responds only to the excess phase of waveforms. We also note that, since in Fig. 15.30
phase comp3!ison is performed in every cycle, the VCO phase and frequency cannot drift
substantially.
Dynamics of CPPLL In order to quantify the behavior of charge-pump PLLs, we must
develop a linear model for the combination of the PFD, the charge pump, and the low-pass
filter, thereby obtaining the transfer function. We therefore raise two questions: (1) Is the
PFD/CPILPF combination in Fig. 15.28 a linear system? (2) If so, how can its transfer
function be computed?
To answer the first question, we test the system for linearity. For example, as illustrated
in Fig. 15.31(a), we double the input phase difference and see if Vout exactly doubles.

A A

B B
.....:~
~$ I
I
i I
Vout
_, I i Vout
J
t t
(a)

.. ·····/··
,·······
......

Vout ········/
::7
t
(b)

Figure 15.31 (a) Test of linearity of PFD/CPILPF combination, (b) ramp approximation of the
response.

Interestingly, the fiat sections of Vour double but not the ramp sections. After all, the current
charging or discharging Cp is constant, yielding a constant slope for the ramp-an effect
similar to slewing in op amps. Thus, the system is not linear in the strict sense. To overcome
this quandary, we approximate the output waveform by a ramp [Fig. 15.31(b)], arriving at a
linear relationship between Vour and fl.¢. In a sense, we approximate a discrete-time system
by a continuous-time model.
To answer the second question, we recall that the transfer function is the Laplace trans-
form of the impulse response, requiring that we apply a phase difference impulse and
 558 Chap. 15 Phase-Locked Loop·

compute V0111 in the time domain. Since a phase difference impulse is difficult to visualizt
we apply a phase difference step, obtain Vaut, and differentiate the result with respect to timl'
Let us assume the input period is T; 11 and the charge pump provides a current of ±lp 11 1
the capacitor. As shown in Fig. 15.32, we begin with a zero phase difference and, at t = 0
step the phase of B by ¢ 0 , i.e., /1¢ = ¢0u(t). As a result, QA or QB continues to producl

..
:
I ~ .J
~
: ,.~--.!'~'~~~

I
Vout ••• :• """··y /p
......... ........ th
-----~itt······· - - '!'0
.: 21t Cp
0 t

Figure 15.32 Step response of PFD/CPILPF combination.

pulses that are ¢0 T;11 1(2rr) seconds wide, raising the output voltage by (lp I Cp )¢oT;nl(2rr)
in every period.10 Approximated by a ramp, V0111 thus exhibits a slope of (IpIC p)¢ol(2rr)
and can be expressed as
lp
Vout(t) = - - t · ¢ou(t). (15.37)
2rrCp
The impulse response is therefore given by
lp
h(t) = --u(t), (15.38)
2rrCp
yielding the transfer function
Vow (s) = --.!.!__ . ! . (15.39)
/1¢ 2rrCp s

Consequently, the PFD/CP/LPF combination contains a pole at the origin, a point of contrast
to the PD/LPF circuit used in the type I PLL. In analogy with the expression K vc0 Is, we
call /p 1(2rrCp) the "gain" of the PFD and denote it by KPFD ·

Example 1 5 . 1 0 - - - - - - - - - - - - - - - - - - - - -
Suppose the output quantity of interest in the circuit of Fig. 15.28 is the current injected by the charge
pump into the capacitor. Determine the transfer function from!::.¢ to this current, / 0111 •

10 We neglect the effect of the narrow reset pulses that appear in the other output.
·I>C. 15.2 Charge-Pump PLLs 559

Solution
Since V0 u1(s ) =lout!(Cps), we have
l out Ip
- (s)= - . (15.40)
~¢ 2Jl'

.
I'

Let us now construct a linear model of charge-pump PLLs. Shown in Fig. 15.33, the
model gives an open-loop transfer function

<~>out (s)l = _!!___ K vco (15.41)

"'
'Vin
open 2rr Cp s 2 •

Since the loop gain has two poles at the origin, this topology is called a "type IT" PLL. The
closed-loop transfer function, denoted by H(s) for the sake of brevity, is thus equal to
lpKvco
H(s) = 2rrCp . (15.42)
s2 + /pKvco
2rrCp
This result is alarming because the closed-loop system contains two imaginary poles at
s1.2 = ± j .JI p Kvco I (2rr Cp) and is therefore unstable. The instability arises because
the loop gain has only two poles at the origin, (i.e., two ideal integrators). As shown in
Fig. 15.34(a), each integrator contributes a constant phase shift of 90°, allowing the system
to oscillate at the gain crossover frequency.

PFD/CP/LPF VCO
...... ...... ........................... ............
• 0
0 I
0 0
I

lp 1 Kvco
o
27t Cp s lI
s
0 0
... . . . . . . . . ...................... ..................... ...
0 0

Figure 15.33 Linear model of simple charge-pump PLL.

In order to stabilize the system, we must modify the phase characteristic such that
the phase shift is less than 180° at the gain crossover. As shown in Fig. 15.34(b), this is
accomplished by introducing a zero in the loop gain, i.e., by adding a·resistor in series with
the loop filter capacitor (Fig. 15.35). Using the result of Example 15.10, the reader can
prove (Problem 15.11) that the PFD/CPILPF now has a transfer function

- (s) = -l p ( Rp +1-) .
Vout (15.43)
6.¢ 2rr Cps
It follows that the PLL open-loop transfer function is equal to
<I> out lp( 1 ) K VCO
~ (s) l open = -
'V zn 27r
Rp + -C
pS
- -,
S
(15.44)
560 Chap. 15 Phase-Locked Loop:

201ag IH open I 201ag IHopen I

lagro logro
lagro lagro
0 - + - - - - - - -..... 0 - + - - - - - - -.....
-90° ......................... .
0
-135
-180°1--------- -180°....___
~pen ~pen
(a) (b)

Figure 15.34 (a) Loop gain characteristics of simple charge-pump PLL, (b) addition of zero.

Voo
/1
D QA
v,n CK Q

Reset vco Vout

Rp
CK Q s2
D QB
~ /2 ICp
':'

':'

Figure 15.35 Addition of zero to charge-pump PLL.

and hence

lpKvco (RpCps + 1) .
H(s) = 2rrCp (15.45)
lp [p
s2 + -KvcoRps + --Kvco
2rr 2rrCp

The closed-loop system contains a zero at Sz = -1/(RpC p ). Using the same notation as
that for the type I PLL, we have

lpKvco
(15.46)
2rrCp
Sec. 15.2 Charge-Pump PLLs 561

Rp IpCpKvco
~=- . (15.47)
2 2Jr
As expected, if Rp = 0, then~ = 0. With complex poles, the decay time constant is given
by 1 /(~wn) = 4rrj(RpipKvco).
Stability Issues The stability behavior of type II PLLs is quite different from that of
type IPLLs. We begin the analysis with the Bode plots of the loop gain [Eq. (15.44)]. Shown
in Fig. 15.36, these plots suggest that if IpKvco decreases, the gain crossover frequency

201ogiHopen I

logro
logro
0-+----~---~------..
0 ' •

..
-90 ·············-~·······!.:..:~··;.:.:.··~·- -

-180°1---- Figure 15.36 Stability degradation

of charge-pump PLL as lpKvco
I.!!..Jpen decreases.
moves toward the origin, degrading the phase margin. Predicted by (15.47), this trend is in
sharp contrast to that expressed by (15.18) and illustrated in Fig. 15.19.
It is also possible to construct the root locus of the closed-loop system in the complex
plane. For I p K vco = 0 (e.g., I p = 0), the loo is o en and both poles lie at the origin. For
IpK vco > 0, we have, s1,2 = -~Wn ± Wn ~ 2 - 1, and, since~ ex: J /pK vco, the poles
are complex if Ip Kvc0 is small. The reader can prove (Problem 15.14) that as I p Kvc 0
increases, s1 and s2 move on a circle centered at a = -1/(RpCp) with a radius 1/ (RpC p)
(Fig. 15.37). The poles return to the real axis at~ = 1, assuming a value of -2/ (RpC p ).
For ~ > 1, the poles remain real, one approaching - 1I (Rp Cp) and the other going to - oo
as I p K vc0 -+ +oo. Since for complex St and s2, ~ = cos <P, we observe that as I p K vco
exceeds zero, the system becomes more stable.

Figure 15.37 Root locus of type II

PLL.
 562 Chap. 15 Phase-Locked Loo1•

The compensated type II PLL of Fig. 15.35 suffers from a critical drawback. Since tl u
charge pump drives the series combination of R p and Cp, each time a current is injected ilth
the loop filter, the control voltage experiences a large jump. Even in the locked conditiou
the mismatches between / 1 and h and the charge injection and clock feedthrough of .~ 1
and S2 introduce voltage jumps in Vcont· The resulting ripple severely disturbs the VC< l
corruptipg the output phase. To relax this issue, a second capacitor is usually added 111
parallel'with Rp and Cp (Fig. 15.38), suppressing the initial step. The loop filter now is of

D QA
V1no----1 CK Q 1----t---T

Reset .,__.,__+--I vco

I
-.
Figure 15.38 Addition of C2 to reduce ripple on the control line.

second order, yielding a third-order PLL and creating stability difficulties [4]. Nonetheless,
if C2 is about one-fifth to one-tenth of Cp, the closed-loop time and frequency responses
remain relatively unchanged.
Equation (15.47) implies that the loop becomes more stable as Rp increases. In reality,
as Rp becomes very large, the stability degrades again. This effect is not predicted by
the foregoing derivations because we have approximated the discrete-time system by n
continuous-time loop. A more accurate analysis is given in [2], but simulations are often
necessary to determine the stability bounds of CPPLLs.

15.3 Nonideal Effects in Plls

15.3.1 PFD/CP Nonideallties
Several imperfections in the PFD/CP circuit lead to high ripple on the control voltage even
when the loop is locked. As mentioned earlier, the ripple modulates the VCO frequency,
producing a waveform that is no longer periodic. In this section, we study these nonidealities.
The PFD implementation of Fig. 15.24(a) generates narrow, coincident pulses on both
QA and QB even when the input phase difference is zero. As illustrated in Fig. 15.39, if'
A and B rise simultaneously, so do QA and Q 8 , thereby activating the reset. That is, even
when the PLL is locked, QA and Q8 simultaneously tum on the charge pump for a finite
period Tp ~ lOTv, where Tv denotes the gate delay (Example 15.8).
Sec 15.3 Nonideal Effects in PLLs 563

QA rcrp I I I
Os
I I I I Figure 15.39 Coincident pulses
generated by PFD with zero phase
t difference.

What are the consequences of the reset pulses on QA and QB? To understand why these
pulses are desirable, we consider a hypothetical PFD that produces no pulses for a zero
input phase difference [Fig. 15.40(a)]. How does such a PFD respond to a small phase
error? As shown in Fig. 15.40(b), the circuit generates very narrow pulses on QA or QB.

A A

B B

t t
(a) (b)

Figure 15.40 Output waveforms of a hypothetical PD with (a) zero input phase difference, and
(b) a small input phase difference.

However, owing to the finite risetime and falltime resulting from the capacitance seen at
these nodes, the pulse may not find enough time to reach a logical high level, failing to tum
on the charge pump switches. In other words, if the input phase difference, 6.¢, falls below
a certain value ¢0, then the output voltage of the PFD/CPILPF combination is no longer a
function of 6.¢. Since, as depicted in Fig. 15.41, for 16.¢1 < ¢0 the charge pump injects

Charge Pump
Current +/p

~0

Figure 15.41 Dead zone in the charge

-/p
pump current.
564 Chap. 15 Phase-Locked Loo1'

no current, Eq. (15 .41) implies that the loop gain drops to zero and the output phase is llPI
locked. We say the PFD/CP circuit suffers from a dead zone equal to ±¢o around .6.¢ = 0
The dead zone is highly undesirable because it allows the VCO to accumulate as mud t
random phase error as ¢0 with respect to the input while receiving no corrective feedbac~.
Thus, as illustrated in Fig. 15.42, the zero crossing points of the VCO output experienc•,
substanti~l random variations, an effect called "jitter."

Input

VCO Output

t
Figure 15.42 Jitter resulting from the dead zone.

Interestingly, the coincident pulses on QA and Q 8 can eliminate the dead zone. This is
because, for .6.¢ = 0, the pulses always turn on the charge pump if they are sufficiently wide,
Consequently, as shown in Fig. 15.43, an infinitesimal increment in the phase difference

t t

Figure 15.43 Response of actual PD to a small input phase difference.

results in a proportional increase in the net current produced by the charge pump. In other
words, the dead zone vanishes if Tp is long enough to allow QA and Q 8 to reach a valid
logical level and turn on the switches in the charge pump.
While eliminating the dead zone, the reset pulses on QA and Q8 introduce other dif-
ficulties . Let us first implement the charge pump using MOS transistors [Fig. 15.44(a)].
Here, M1 and M2 operate as current sources and M3 and M4 as switches. The output QA is
inverted so that when it goes high, M4 turns on.
The first issue in the circuit of Fig. 15.44(a) stems from the delay difference between
QA and Q8 in turning on their respective switches. As shown in Fig. 15.44(b), the net
current injected by the charge pump into the loop filter jumps to +Ip and -Ip, disturbing
the oscillator control voltage periodically even if the loop is locked. To suppress this effect,
 566 Chap. 15 Phase-Locked Loop·.

QA l . . . . ._ __.
Gall Jj
I 03 Jr------....____
llo41 _j
Net Net
Current _Jt.mlli• L - - - Current

t
(a) (b)

Figure 15.45 Effect of UP and DOWN current mismatch.

I charge injection mismatch between M3 and M4 further increases both the phase error and
the ripple.
The third issue in the circuit of Fig. 15.44(c) originates from the finite capacitance seen
at the drains of the current sources. Suppose, as illustrated in Fig. 15.46(a), S1 and S2 are
off, allowing M1 to discharge X to ground and M2 to charge Y to VDD· At the next phase
comparison instant, both S1 and S2 turn on, Vx rises, Vr falls, and Vx ~ Vr ~ Vcont if the
voltage drop across S1 and S2 is neglected [Fig. 15.46(b)]. If the phase error is zero and

Vy
Vout

(a) (b)

Figure 15.46 Charge sharing between Cp and capacitances at X and Y.

IDl = II D2i, does Vconr remain constant after the switches turn on? Even if Cx = Cy, the
change in Vx is not equal to that in Vy. For example, if Vcont is relatively high, Vx changes
by a large amount and Vr by a small amount. The difference between the two changes must
therefore be supplied by Cp, leading to a jump in Vcont.
The above charge sharing phenomenon can be suppressed by "bootstrapping." Illustrated
in Fig. 15.47 [3], the idea is to "pin" Vx and Vy to Vcom after phase comparison is finished.
When sl and s2 turn off, s3and s4 tum on, allowing the unity-gain amplifier to hold nodes
Sec. 15.3 Nonideal Effects in PLLs 567

Figure 15.47 Bootstrapping X and Y

-. to minimize charge sharing.

X and Y at a potential equal to Vcont. Note that the amplifier need not provide much current
because It ~ h. At the next phase comparison instant, S1 and S2 tum on, S3 and S4 tum off,
and Vx and Vy begin with a value equal to Vcont· Thus, no charge sharing occurs between
Cp and the capacitances at X. and Y.

15.3.2 Jitter in Plls

The response of phase-locked loops to jitter is of extreme importance in most applications.
We first describe the concepts of jitter and the rate of change of jitter.
As shown in Fig. 15.48, a strictly periodic waveform, x1(t), contains zero crossings that
are evenly spaced in time. Now consider the nearly periodic signal x2(t), whose period

Te
x 1 (t) ~ ..,.
D D D D CLD ...
_J o 11
tl
tl
o~
I I
I I
J
o~u. Lt
II
I I
I I I
tl
If

' '
'' '''
' '
t

Total
Phase
t
Excess
Phase
t

Figure 15.48 Ideal and jittery waveforms.

568 Chap. 15 Phase-Locked Loop·

experiences small changes, deviating the zero crossings from their ideal points. We say tht
latter waveform suffers from jitter. 11 Plotting the total phase, ¢ 101 , and the excess phase
<Pex, of the two waveforms, we observe that jitter manifests itself as variation of the exces~
phase with time. In fact, ignoring the harmonics above the fundamental, we can write
x1(t) = A cos wt and x2(t) = A cos[wt + ¢ 11 (!)], where ¢11 (t) models the variation of the
period. 1 ~
The rate at which the jitter varies is also important. Consider the two jittery wavefonns
depicted in Fig. 15.49. The first signal, y1(t), experiences "slow jitter" because its instan·
taneous frequency varies slowly from one period to the next. The second signal, Y2(t),

Y1 (t)
nJlnnnnr

_jQLJDULJLr
Excess
Phase

Figure 15.49 Illustration of slow and fast jitter.

experiences "fast jitter." The rate of change is also evident from the excess phase plots of
the two waveforms.
Two jitter phenomena in phase-locked loops are of great interest: (a) the input exhibits
jitter, and (b) the VCO produces jitter. Let us study each case, assuming the input and output
waveforms are expressed as Xin(t) =A cos[wt + </Jin(t)] and XourU) =A cos[wt +<Pour(t)].
The transfer functions derived for type I and type II PLLs have a low-pass characteristic,
suggesting that if ifJin(t) varies rapidly, then <Pour(t) does not fully track the variations. In
other words, slow jitter at the input propagates to the output unattenuated but fast jitter does
not. We say the PLL low-pass filters </Jin(t).
Now suppose the input is strictly periodic but the VCO suffers from jitter. Viewing jitter
as random phase variations, we construct the model depicted in Fig. 15.50, where the input
excess phase is set to zero [i.e., x; 11 (t) =A cos wt] and a random component <l>vco is added
to the output of the VCO to represent its jitter. The reader can show that the transfer function
from <l>vco to <~>out for a type II PLL is equal to
2
<l>ow (s) = s (15.48)
<l>vco s 2 + 2~ WnS + w;
11 Jitter isquantified by several different mathematical definitions, e.g., as in [5].
12 The quantity ¢n(t) (or more commonly its spectrum) is called the "phase noise." In this book, we assume
the jitter is uniquely represented by ¢n (t).
Sec. 15.4 Delay-Locked Loops 569

PFD/CP/LPF VCO

/p 1 Kvco
-(-+Rp)
21t Cps s
I'

' ........ ..............-..-.. .-..-..-..-..-...-..-.........l

Figure 15.50 Effect of VCO jitter.

Interestingly, the characteristic has a high-pass nature, indicating that slow jitter compo-
nents generated by the VCO are suppressed but fast jitter components are not. This can
be understood with the aid of Fig. 15.50: If <Pvco(t) changes slowly (e.g., the oscillation
period drifts with temperature), then the comparison with ¢in = 0 (i.e., a perfectly periodic
signal) generates a slowly varying error that propagates through the LPF and adjusts the
VCO frequency, thereby counteracting the change in <Pvco. On the other hand, if <Pvco
varies rapidly, (e.g., high-frequency noise modulates the oscillation period), then the error
produced by the phase detector is heavily attenuated by the poles in the loop, failing to
correct for the change.
Figure 15.51 conceptually summarizes the response ofPLLs to inputjitter and VCO jitter.
Depending on the application and the environment, one or both sources may be significant,
requiring an optimum choice of the loop bandwidth.

$out
$vco

Rate of Change Rate of Change

of$in of $vco

Figure 15.51 Transfer functions of jitter from input and VCO to the output.

15.4 Delay-Locked Loops

A variant of PLLs that has become popular in the past ten years is the delay-locked
loop. To arrive at the concept, let us begin with an example. Suppose an application re-
quires four clock phases with a precise spacing of !:1 T = 1 ns between consecutive edges
[Fig. 15.52(a)]. How should these phases be generated? We can use a two-stage differential
ring oscillator13 to produce the four phases, but how do we guarantee that !:1 T = 1 ns

13 As explained in Chapter 14, a simple two-stage CMOS ring oscillator may not oscillate. This example is
merely for illustration purposes.
570 Chap. 15 Phase-Locked Loop~

CK 1 j
CK2 i'
'

........: L..t-:
1 ns
t
(a) (b)

Figure 15.52 (a) Clock phases with edge-to-edge delay of 1ns, (b) use of a phase-locked ring oscillator to generate
the clock phases.

despite process and temperature variations? This requires that the oscillator be locked to a
250-MHz reference so that the output period is exactly equal to 4 ns [Fig. 15.52(b)].
An alternative approach to generating the clock phases of Fig. 15.52(a) is to apply the
input clock to four delay stages in a cascade. lllustrated in Fig. 15.53(a), this technique
nonetheless does not produce a well-defined edge spacing because the delay of each stage

CK in o.--.----f

CKin

(a) (b)

Figure 15.53 (a) Generation of clock edges by delay stages, (b) simple delay-locked loop .

.varies with process and temperature. Now consider the circuit shown in Fig. 15.53(b), where
the phase difference between CK in and C K4 is sensed by a phase detector, a proportional
average voltage, Vconh is generated, and the delay of the stages is adjusted with negative
feedback. For a large loop gain, the phase difference between CKin and C K4 is small, that
is, the four stages delay the clock by almost exactly one period, thereby establishing precise
edge spacing. 14 This topology is called a delay-locked loop to emphasize that it incorporates
a voltage-controlled delay line (VCDL) rather than a VCO. In practice, a charge pump is

14The total delay through the four stages may be equal to two or more periods. We return to this issue later.
Sec. 15.4 Delay-Locked Loops 571

interposed between the PD and the LPF to achieve an infinite loop gain. Each delay stage
may be based on one of the ring oscillator stages described in Chapter 14.
The reader may wonder about the advantages of DLLs over PLLs. First, delay lines are
generally less susceptible to noise than oscillators are because corrupted zero crossings
of a waveform disappear at the end of a delay line whereas they are recirculated in an
oscillator, th~reby experiencing more corruption. Second, in the VCDL of Fig. 15.53(b), a
change in the control voltage immediately changes the delay, that is, the transfer function
<l>ou1(s)/ Vcont(s) is simply equal to the gain of the VCDL, K VCDL· Thus, the feedback
system of Fig. 15.53(b) has the same order as the LPF and its stability and settling issues
are more relaxed than those of a PLL.

Example 1 5 . 1 1 - - - - - - - - - - - - - - - - - - - -
Determine the closed-loop transfer function of the DLL shown in Fig. 15.54.

$1n ~~----------1

PO CP

Figure 15.54

Solution
From Example 15.10, we write the transfer function of the PD/CPILPF combination as

Vcont
- ( s ) =I-
p [ ( 1 ) -1 ]
Rp+- (15.49)
~<I> 2n Cps C2s

lp +1
RpCps
(15.50)
== 2n (RpCpC2s + Cp + C2)s

The closed-loop transfer function is thus equal to

lpKvcDL (RpCps + 1)
~I ~
<l>in (s)lclosed = RpCpC2s2 + [Cp + C2 + lpKvcnLRpCpj(2rr)]s + lpKvcDL/(2rr).
(15.51)

This transfer function can be used to determine how <Pout settles if ¢in experiences a change. Note
that in practice Rp may not be needed because the loop contains only one pole at the origin.
576 Chap. 15 Phase-Locked Loo1 ,.

We should note that the skew can be suppressed by a delay-locked loop as well. lu
fact, if frequency multiplication is not required, DLLs are preferred because they are Jcsl,
susceptible to noise.

15.5.3 Jitter Reduction

I'

Recall from Section 15.3.2 that PLLs suppress fast jitter components at the input. F01
example, if a 1-GHzjittery signal is applied to a PLL having a bandwidth of 10 MHz, then
input jitter components that vary faster than 10 MHz are attenuated. In a sense, the phase·
locked loop operates as a narrowband filter centered around 1 GHz with a total bandwidtll
of 20 MHz. This is another important and useful property of PLLs.
Many applications must deal with jittery waveforms. Random binary signals expe·
rience jitter because of (a) crosstalk on the chip and in the package (Chapter 18), (b)
package parasitics (Chapter 18), (c) additive electronic noise of devices, etc. Such wave·
forms are typically "retimed" by a low-noise clock so as to reduce the jitter. Illustrated
in Fig. 15.61(a), the idea is to resample the midpoint of each bit by a D flipflop that

[Link]
(a)

D
Q --o
- CK

~
Clock Recovery -
Circuit

(b)

Figure 15.61 (a) Retiming data with D flipflop driven by a

low-noise clock, (b) use of a phase-locked clock recovery circuit
to generate the clock.

is driven by the clock. However, in many applications, the clock may not be available
independently. For example, an optical fiber carries only the random data stream, pro-
viding no separate clock waveform at the receive end. The circuit of Fig. 15.61(a) is
therefore modified as shown in Fig. 15.6l(b), where a "clock recovery circuit" (CRC)
produces the clock from the data. Employing phase locking with a relatively narrow
loop bandwidth, the CRC minimizes the effect of the input jitter on the recovered
clock.
Problems 577

Probiems · · _,_ · ·
Unless otherwise stated, in the following problems, use the device data shown in Table 2.1 and assume
Vvv = 3 V where necessary. Also, assume all transistors are in saturation.

15.1. The Gilbert cell (Chapter 4) operates as an XOR gate with large input swings and as an analog
multiplier with small input swings. Prove that an analog multiplier can be used to detect the
phase difference between two sinusoids. Is the input-output characteristic of such a phase
detector linear?
15.2. Redraw the waveforms of Fig. 15.4(b) if the VCO frequency is lowered at 1 = 11. If the phase
error between Vex and Vvco before I= It is equal to <Po and fvco is lowered from !H to
fL, determine the minimum 12 - t1 that is sufficient for phase alignment.
15.3. Explain why the low-pass filter in Fig. 15.5(b) cannot be replaced by a high-pass filter.
15.4. A PLL using an XOR gate as a phase detector locks with <Pin - <Pout ~ 90° if K pD Kvc o is
large. Explain why?
15.5. Using the characteristic of Fig. 15.3 as an example, explain why the polarity of feedback in a
PLL (without frequency detection) is unimportant. (Hint: prove that the loop locks regardless
of whether the initial phase difference falls in the positive-slope region or the negative-slope
region.)
15.6. Assuming a first-order LPF in Fig. 15.14, determine the transfer function <Paut!if>ex. where
<Pout denotes the excess phase of Vaut.
15.7. A VCO used in a type IPLL exhibits nonlinearity in its input-outputcharacteristic, i.e., Kvco
varies across the tuning range. If the damping ratio must remain between 1 and 1.5, how much
variation can be tolerated in K v co?
15.8. Prove that in the root locus of Fig. 15.20, cos e = ~.
15.9. A type I PLL incorporates a VCO with Kvco = 100 MHzJV, a PD with Kpv = 1 V/rad,
and an LPF with WLP F = 2rr(l MHz). Determine the step response of the PLL.
15.10. Explain why in the charge-pump PLL of Fig. 15.35, the control voltage of the VCO cannot
be connected to the top plate of Cp.
15.11. Prove thatthe transfer function of the PFD/CPILPF circuit in Fig. 15.35 is given by Eq. (15.43).
15.12. As illustrated in Fig. 15.45, mismatches between the UP and DOWN currents translate to
phase offset at the input of a CPPLL. With the aid of the waveforms in Fig. 15.45, calculate
the phase offset in terms of current mismatch.
15.13. For a VCO, we have Wout = wo +Kv co Vcont· The control line experiences a small sinusoidal
ripple, Vcont = Vm coswml. If the VCO is followed by a -7-M circuit, determine the output
spectrum of the divider. Consider two cases: wo/ M > Wm and wo/ M <· Wm.
15.14. Prove that the root locus of a type IT PLL is as shown in Fig. 15.37.
15.15. Determine the transfer function <Pout! <Pex for the circuit of Fig. 15.14 if the PLL is modified
to the architecture of Fig. 15.35.
15.16. When a charge-pump PLL incorporating a PFD is turned on, the VCO frequency may be far
from the input frequency. Explain why the order of the PLL transfer function is lower by one
while the PFD operates as a frequency detector.
578 Chap. 15 Phase-Locked Loop:.

References
1. R. E. Best, Phase-Locked Loops, Second Ed., New York: McGraw-Hill, 1993.
2. F. M. Gardner, Phaselock Techniques, Second Ed., New York: Wiley & Sons, 1979.
3. M. G. Johnson and E. L. Hudson, "A Variable Delay Line PLL for CPU-Coprocessor
Synchronization," IEEE Journal of Solid-State Circuits, vol. 23, pp. 1218-1223, Oct. 1988.
4. F. M:. Gardner, "Charge-Pump Phase-Locked Loops," IEEE Trans. Comm., vol. COM-28,
pp.l849-1858, Nov. 1980.
5. F. Herzel and B. Razavi, "A Study of Oscillator Jitter Due to Supply and Substrate Noise," IEEE
Transactions on Circuits and Systems, Part II, vol.46, pp.56-62, Jan. 1999.
6. W. F. Egan, Frequency Synthesis by Phase Lock, New York: Wiley & Sons, 1981.
7. J. A. Crawford, Frequency Synthesizer Design Handbook, New York: Artech House, 1994.