CMOS Fabrication Inverter Cross-section
CMOS transistors are fabricated on silicon wafer Typically use p-type substrate for nMOS transistor
Lithography process similar to printing press – Requires n-well for body of pMOS transistors
On each step, different materials are deposited or – Several alternatives: SOI, twin-tub, etc.
etched A
Easiest to understand by viewing both top and GND
Y
VDD SiO2
cross-section of wafer in a simplified manufacturing n+ diffusion
process n+ n+ p+ p+
p+ diffusion
polysilicon
n well
p substrate
metal1
nMOS transistor pMOS transistor
CMOS VLSI Design CMOS VLSI Design
Well and Substrate Taps Inverter Mask Set
Substrate must be tied to GND and n-well to VDD Transistors and wires are defined by masks
Metal to lightly-doped semiconductor forms poor Cross-section taken along dashed line
connection called Shottky Diode
Use heavily doped well and substrate contacts / taps
A
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well GND VDD
p substrate
nMOS transistor pMOS transistor
substrate tap well tap
substrate tap well tap
CMOS VLSI Design CMOS VLSI Design
Detailed Mask Views Fabrication Steps
Six masks n well
Start with blank wafer
– n-well Build inverter from the bottom up
– Polysilicon First step will be to form the n-well
Polysilicon
– n+ diffusion – Cover wafer with protective layer of SiO2 (oxide)
– p+ diffusion n+ Diffusion – Remove layer where n-well should be built
– Contact p+ Diffusion
– Implant or diffuse n dopants into exposed wafer
– Metal Contact
– Strip off SiO2
Metal
p substrate
CMOS VLSI Design CMOS VLSI Design
Oxidation Photoresist
Grow SiO2 on top of Si wafer Spin on photoresist
– 900 – 1200 C with H2O or O2 in oxidation furnace – Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
Photoresist
SiO2 SiO2
p substrate p substrate
CMOS VLSI Design CMOS VLSI Design
Lithography Etch
Expose photoresist through n-well mask Etch oxide with hydrofluoric acid (HF)
Strip off exposed photoresist Only attacks oxide where resist has been exposed
Photoresist Photoresist
SiO2 SiO2
p substrate p substrate
CMOS VLSI Design CMOS VLSI Design
Strip Photoresist n-well
Strip off remaining photoresist n-well is formed with diffusion or ion implantation
– Use mixture of acids called piranah etch Diffusion
Necessary so resist doesn’t melt in next step – Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2 SiO2
n well
p substrate
CMOS VLSI Design CMOS VLSI Design
Strip Oxide Polysilicon
Strip off the remaining oxide using HF Deposit very thin layer of gate oxide
Back to bare wafer with n-well – < 20 Å (6-7 atomic layers)
Subsequent steps involve similar series of steps Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well n well
p substrate
p substrate
CMOS VLSI Design CMOS VLSI Design
Polysilicon Patterning Self-Aligned Process
Use same lithography process to pattern polysilicon Use oxide and masking to expose where n+ dopants
should be diffused or implanted
N-diffusion forms nMOS source, drain, and n-well
contact
Polysilicon
Polysilicon
Thin gate oxide
n well n well
p substrate p substrate
CMOS VLSI Design CMOS VLSI Design
N-diffusion N-diffusion
Pattern oxide and form n+ regions Historically dopants were diffused
Self-aligned process where gate blocks diffusion Usually ion implantation today
Polysilicon is better than metal for self-aligned gates But regions are still called diffusion
because it doesn’t melt during later processing
n+ Diffusion
n+ n+ n+
n well n well
p substrate p substrate
CMOS VLSI Design CMOS VLSI Design
N-diffusion P-Diffusion
Strip off oxide to complete patterning step Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
n+ n+ n+ p+ n+ n+ p+ p+ n+
n well n well
p substrate p substrate
CMOS VLSI Design CMOS VLSI Design
Contacts Metallization
Now we need to wire together the devices Sputter on aluminum over whole wafer
Cover chip with thick field oxide Pattern to remove excess metal, leaving wires
Etch oxide where contact cuts are needed
Metal
Contact
Metal
Thick field oxide Thick field oxide
p+ n+ n+ p+ p+ n+ p+ n+ n+ p+ p+ n+
n well n well
p substrate p substrate
CMOS VLSI Design CMOS VLSI Design
Layout Simplified Design Rules
Chips are specified with set of masks Conservative rules to get you started
Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
Feature size f = distance between source and drain
– Set by minimum width of polysilicon
Normalize for feature size when describing design
rules
Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
CMOS VLSI Design CMOS VLSI Design
Inverter Layout Summary
Transistor dimensions specified as Width / Length MOS Transistors are stack of gate, oxide, silicon
– Minimum size is 4l / 2l, sometimes called 1 unit Can be viewed as electrically controlled switches
– For 0.6 mm process, W=1.2 mm, L=0.6 mm Build logic gates out of switches
Draw masks to specify layout of transistors
Now you know everything necessary to start
designing schematics and layout for a simple chip!
CMOS VLSI Design CMOS VLSI Design