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LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015

LT1054 Switched-Capacitor Voltage Converters With Regulators

1 Features 3 Description
•
1 Output Current, 100 mA The LT1054 device is a bipolar, switched-capacitor
voltage converter with regulator. It provides higher
• Low Loss, 1.1 V at 100 mA output current and significantly lower voltage losses
• Operating Range, 3.5 V to 15 V than previously available converters. An adaptive-
• Reference and Error Amplifier for Regulation switch drive scheme optimizes efficiency over a wide
• External Shutdown range of output currents.
• External Oscillator Synchronization Total voltage drop at 100-mA output current typically
is 1.1 V. This applies to the full supply-voltage range
• Devices Can Be Paralleled
of 3.5 V to 15 V. Quiescent current typically is 2.5
• Pin-to-Pin Compatible With the LTC1044/7660 mA.

2 Applications The LT1054 also provides regulation, a feature

previously not available in switched-capacitor voltage
• Industrial Communications (RS232) converters. By adding an external resistive divider, a
• Data Acquisition Supply regulated output can be obtained. This output is
regulated against changes in both input voltage and
• Voltage Inverters
output current. The LT1054 can also shut down by
• Voltage Regulators grounding the feedback terminal. Supply current in
• Negative Voltage Doublers shutdown typically is 100 μA.
• Positive Voltage Doublers The internal oscillator of the LT1054 runs at a
nominal frequency of 25 kHz. The oscillator terminal
can be used to adjust the switching frequency or to
externally synchronize the LT1054.
The LT1054C is characterized for operation over a
free-air temperature range of 0°C to 70°C. The
LT1054I is characterized for operation over a free-air
temperature range of −40°C to 85°C.

Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
PDIP (8) 9.50 mm × 6.35 mm
LT1054
SOIC (16) 10.30 mm × 10.30 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.

Basic Voltage Inverter

1 8
FB/SD VCC VIN
+
2 μF
2 7
CAP+ OSC
LT1054
+ 3 6
10 μF GND VREF

4 5
CAP− VOUT −VOUT
100 μF
+

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015 [Link]

Table of Contents
1 Features .................................................................. 1 7.4 Device Functional Modes........................................ 11
2 Applications ........................................................... 1 8 Application and Implementation ........................ 13
3 Description ............................................................. 1 8.1 Application Information .......................................... 13
4 Revision History..................................................... 2 8.2 Typical Application ................................................. 13
8.3 System Examples ................................................... 16
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4 9 Power Supply Recommendations...................... 23
6.1 Absolute Maximum Ratings ...................................... 4 10 Layout................................................................... 24
6.2 ESD Ratings ............................................................ 4 10.1 Layout Guidelines ................................................. 24
6.3 Recommended Operating Conditions....................... 4 10.2 Layout Example .................................................... 24
6.4 Thermal Information ................................................. 4 11 Device and Documentation Support ................. 25
6.5 Electrical Characteristics........................................... 5 11.1 Community Resources.......................................... 25
6.6 Typical Characteristics .............................................. 6 11.2 Trademarks ........................................................... 25
7 Detailed Description .............................................. 9 11.3 Electrostatic Discharge Caution ............................ 25
7.1 Overview ................................................................... 9 11.4 Glossary ................................................................ 25
7.2 Functional Block Diagram ......................................... 9 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................... 9 Information ........................................................... 25

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (November 2004) to Revision G Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1

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5 Pin Configuration and Functions

P Package
8-Pin PDIP
Top View

FB/SD 1 8 VCC
CAP+ 2 7 OSC
GND 3 6 VREF
CAP− 4 5 VOUT

DW Package
16-Pin SOIC
Top View

NC 1 16 NC
NC 2 15 NC
FB/SD 3 14 VCC
CAP+ 4 13 OSC
GND 5 12 VREF
CAP− 6 11 VOUT
NC 7 10 NC
NC 8 9 NC

NC − No internal connection

Pin Functions
PIN
I/O DESCRIPTION
NAME PDIP SOIC
FB/SD 1 3 Input Shutdown for low Iq operation or error amp input for regulation
CAP+ 2 4 Input Positive side of CIN
GND 3 5 — Ground
CAP- 4 6 Input Negative side of CIN
VOUT 5 11 Output Regulated output voltage
VREF 6 12 Output Internal Reference Voltage
OSC 7 13 Input Oscillator control pin
VCC 8 14 — Supply pin
1, 2, 7, 8, 9,
NC — — No connect (no internal connection)
10, 15, 16

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
VCC Supply voltage (2) 16 V
FB/SD 0 VCC V
VI Input voltage
OSC 0 Vref V
LT1054C 125 °C
TJ Junction temperature (3)
LT1054I 135 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) The absolute maximum supply-voltage rating of 16 V is for unregulated circuits. For regulation-mode circuits with VOUT ≤ 15 V, this
rating may be increased to 20 V.
(3) The devices are functional up to the absolute maximum junction temperature.

6.2 ESD Ratings

VALUE UNIT
(1)
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±500
V(ESD) V
discharge Charged-device model (CDM), per JEDEC specification JESD22-C101 (2) ±3500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage 3.5 15 V
Operating free-air LT1054C 0 70
TA °C
temperature range LT1054I –40 85

6.4 Thermal Information

LT1054
THERMAL METRIC (1) P (PDIP) DW (SOIC) UNIT
8 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 85 57 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

over recommended operating free-air temperature range (unless otherwise noted)
LT1054C, LT1054I
PARAMETER TEST CONDITIONS TA (1) UNIT
MIN TYP (2) MAX
(3)
VO Regulated output voltage VCC = 7 V, TJ = 25°C, RL = 500 Ω 25°C −4.7 −5 −5.2 V
(3)
Input regulation VCC = 7 V to 12 V, RL = 500 Ω Full range 5 25 mV
Output regulation VCC = 7 V, RL = 100 Ω to 500 Ω (3) Full range 10 50 mV
Voltage loss, IO = 10 mA 0.35 0.55
CI = CO = 100-μF tantalum Full range V
VCC − |VO| (4) IO = 100 mA 1.1 1.6
(5)
Output resistance ΔIO = 10 mA to 100 mA See Full range 10 15 Ω
Oscillator frequency VCC = 3.5 V to 15 V Full range 15 25 35 kHz
25°C 2.35 2.5 2.65
Vref Reference voltage I(REF) = 60 μA V
Full range 2.25 2.75
Maximum switch current 25°C 300 4 mA
VCC = 3.5 V 2.5 5
ICC Supply current IO = 0 Full range mA
VCC = 15 V 3 200
Supply current in
V(FB/SD) = 0 V Full range 100 μA
shutdown

(1) Full range is 0°C to 70°C for the LT1054C and −40°C to 85°C for the LT1054I.
(2) All typical values are at TA = 25°C.
(3) All regulation specifications are for a device connected as a positive-to-negative converter/regulator with R1 = 20 kΩ, R2 = 102.5 kΩ,
external capacitor CIN = 10 μF (tantalum), external capacitor COUT = 100 μF (tantalum) and C1 = 0.002 μF (see ).
(4) For voltage-loss tests, the device is connected as a voltage inverter, with terminals 1, 6, and 7 unconnected. The voltage losses may be
higher in other configurations. CIN and COUT are external capacitors.
(5) Output resistance is defined as the slope of the curve (ΔVO versus ΔIO) for output currents of 10 mA to 100 mA. This represents the
linear portion of the curve. The incremental slope of the curve is higher at currents less than 10 mA due to the characteristics of the
switch transistors.

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6.6 Typical Characteristics

Data at high and low temperatures are applicable only within the recommended operating free-air temperature range.
Table 1. Table of Graphs
FIGURE
Shutdown threshold voltage vs Free-air temperature Figure 1
Supply current vs Input voltage Figure 2
Oscillator frequency vs Free-air temperature Figure 3
Supply current in shutdown vs Input voltage Figure 4
Average supply current vs Output current Figure 5
Output voltage loss vs Input capacitance Figure 6
Output voltage loss vs Oscillator frequency (10 µF) Figure 7
Output voltage loss vs Oscillator frequency (100 µF) Figure 8
Regulated output voltage vs Free-air temperature Figure 9
Reference voltage change vs Free-air temperature Figure 10
Voltage loss vs Output current Figure 17

0.6 5
IO = 0

0.5
Shutdown Threshold Voltage − V

I CC − Supply Current − mA 4

0.4
V(FB/SD)
3

0.3

2
0.2

0.1 1

0 0
−50 −25 0 25 50 75 100 0 5 10 15
TA − Free-Air Temperature − °C VCC − Input Voltage − V

Figure 1. Shutdown Threshold Voltage vs Free-Air Figure 2. Supply Current vs Input Voltage
Temperature

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35 120

33
100

Supply Current in Shutdown − μA

31
Oscillator Frequency − kHz

V(FB/SD) = 0
29
VCC = 15 V 80
27

25 60
VCC = 3.5 V
23
40
21

19 20
17

15 0
−50 −25 0 25 50 75 100 0 5 10 15
TA − Free-Air Temperature − °C VCC − Input Voltage − V

Figure 3. Oscillator Frequency vs Free-air Temperature Figure 4. Supply Current in Shutdown vs Input Voltage
140 1.4

120 1.2
IO = 100 mA
Average Supply Current − mA

Output Voltage Loss − V

100 1.0

80 0.8
IO = 50 mA

60 0.6

IO = 10 mA
40 0.4

Inverter Configuration
20 0.2
COUT = 100-μF Tantalum
fOSC = 25 kHz
0 0
0 20 40 60 80 100 0 10 20 30 40 50 60 70 80 90 100
IO − Output Current − mA Input Capacitance − μF

Figure 5. Average Supply Current vs Output Current Figure 6. Output Voltage Loss vs Input Capacitance
2.5 2.5
Inverter Configuration Inverter Configuration
2.25 CIN = 10-μF Tantalum 2.25 CIN = 100-μF Tantalum
COUT = 100-μF Tantalum COUT = 100-μF Tantalum
2 2
Output Voltage Loss − V
Output Voltage Loss − V

1.75 1.75

1.5 1.5
IO = 100 mA
1.25 1.25 IO = 100 mA

1 1
IO = 50 mA
IO = 50 mA
0.75 0.75

0.5 IO = 10 mA
0.5
IO = 10 mA
0.25 0.25
0 0
1 10 100 1 10 100
Oscillator Frequency − kHz Oscillator Frequency − kHz

Figure 7. Output Voltage Loss vs Oscillator Frequency Figure 8. Output Voltage Loss vs Oscillator Frequency

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−4.7 100

−4.8 80

∆V ref − Reference Voltage Change − mV

VO − Regulated Output Voltage − V

−4.9 60

−5 40

−5.1 20

−11.6 0

−11.8 −20
VREF at 0 = 2.500 V
−12 −40

−12.2 −60

−12.4 −80
−12.6 −100
−50 −25 0 25 50 75 100 −50 −25 0 25 50 75 100 125
TA − Free-Air Temperature − °C TA − Free-Air Temperature − °C

Figure 9. Regulated Output Voltage vs Free-air Temperature Figure 10. Reference Voltage Change vs Free-air
Temperature

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7 Detailed Description

7.1 Overview
LT1054 is a "negative voltage generator" or "negative charge pump" that will output a negative voltage that is
proportional to the input voltage (or VCC). With proper supply voltage, VOUT will regulate to an unregulated VOUT
that is approximately –VCC (reduced by a small voltage loss). If a lower absolute voltage is desired, VOUT can be
regulated to that value when proper feedback resistors are applied.
LT1054 regulates up to 100mA with minimal loss and has a shutdown mode that makes this part optimal across
a wide range of applications.

7.2 Functional Block Diagram

VREF VCC
6 8

2.5 V
Ref
R Drive

+ 2
CAP +
1
FB/SD − CIN†
7 Q
OSC OSC 4
Q CAP −

R Drive
Drive
3
GND

COUT†
5
VOUT

Drive

† External capacitors
Pin numbers shown are for the P package.

7.3 Feature Description

7.3.1 Reference and Error Amplifier for Regulation
The feedback/shutdown (FB/SD) terminal has two functions. Pulling FB/SD below the shutdown threshold (≈ 0.45
V) puts the device into shutdown. In shutdown, the reference/regulator is turned off and switching stops. The
switches are set such that both CIN and COUT are discharged through the output load. Quiescent current in
shutdown drops to approximately 100 µA. Any open-collector gate can be used to put the LT1054 into shutdown.
For normal (unregulated) operation, the device will restart when the external gate is shut off. In LT1054 circuits
that use the regulation feature, the external resistor divider can provide enough pulldown to keep the device in
shutdown until the output capacitor (COUT) has fully discharged. For most applications, where the LT1054 is run
intermittently, this does not present a problem because the discharge time of the output capacitor is short
compared to the off time of the device. In applications where the device has to start up before the output
capacitor (COUT) has fully discharged, a restart pulse must be applied to FB/SD of the LT1054. Using the circuit
shown in Figure 11, the restart signal can be either a pulse (tp > 100 µs) or a logic high. Diode coupling the
restart signal into FB/SD allows the output voltage to rise and regulate without overshoot. The resistor divider
R3/R4 shown in Figure 11 should be chosen to provide a signal level at FB/SD of 0.7−1.1 V.
FB/SD also is the inverting input of the LT1054 error amplifier and, as such, can be used to obtain a regulated
output voltage.

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Feature Description (continued)

R3 VIN
2.2μF
1 8 +
FB/SD VCC

2 7
CAP+ OSC
R4 CIN LT1054
+ 3 6 R1
10-μF GND VREF
Tantalum
4 5 R2
CAP− VOUT

Restart Shutdown
VOUT
For example: To get VO = −5 V, referenced to the ground terminal of the LT1054 C1
æ ö æ ö
ç VOUT ÷ ç -5 V ÷ COUT
R2 = R1ç + 1÷ = 20 kW ç + 1÷ = 102.6 kW † 100-μF
çç VREF - 40 mV ÷÷ çç 2.5 V - 40 mV ÷÷ Tantalum
è 2 ø è 2 ø
Where: R1 = 20 kΩ
VREF = 2.5 V Nominal

† Choose the closest 1% value.

Figure 11. Basic Regulation Configuration

7.3.2 External Oscillator Synchronization

This pin can be used to raise or lower the oscillator frequency or to synchronize the device to an external clock.
Internally Pin 7 is connected to the oscillator timing capacitor (Ct ≈ 150pF) which is alternately charged and
discharged by current sources of ±7µA so that the duty cycle is ≈50%. The LT1054 oscillator is designed to run
in the frequency band where switching losses are minimized. However the frequency can be raised, lowered, or
synchronized to an external system clock if necessary.

1 8 C2
FB/SD VCC VIN

2 7
CAP+ OSC
LT1054
+ 3 6
GND VREF
C1
4 5
CAP− VOUT

Figure 12. External-Clock System

The frequency can be lowered by adding an external capacitor (C1, Figure 12) from Pin 7 to ground. This will
increase the charge and discharge times which lowers the oscillator frequency. The frequency can be increased
by adding an external capacitor (C2, Figure 12, in the range of 5pF to 20pF) from Pin 2 to Pin 7. This capacitor
will couple charge into CT at the switch transitions, which will shorten the charge and discharge time, raising the
oscillator frequency. Synchronization can be accomplished by adding an external resistive pull-up from Pin 7 to

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Feature Description (continued)

the reference pin (Pin 6). A 20k pull-up is recommended. An open collector gate or an NPN transistor can then
be used to drive the oscillator pin at the external clock frequency as shown in Figure 12. Pulling up Pin 7 to an
external voltage is not recommended. For circuits that require both frequency synchronization and regulation, an
external reference can be used as the reference point for the top of the R1/R2 divider allowing Pin 6 to be used
as a pullup point for Pin 7.

7.3.3 Output Current and Voltage Loss

The functional block diagram shows that the maximum regulated output voltage is limited by the supply voltage.
For the basic configuration, |VOUT| referenced to the ground terminal of the LT1054 must be less than the total of
the supply voltage minus the voltage loss due to the switches. The voltage loss versus output current due to the
switches can be found in the typical performance curves. Other configurations, such as the negative doubler, can
provide higher voltages at reduced output currents.

7.3.4 Reference Voltage

Reference Output. This pin provides a 2.5V reference point for use in LT1054-based regulator circuits. The
temperature coefficient of the reference voltage has been adjusted so that the temperature coefficient of the
regulated output voltage is close to zero. This requires the reference output to have a positive temperature
coefficient as can be seen in the typical performance curves. This nonzero drift is necessary to offset a drift term
inherent in the internal reference divider and comparator network tied to the feedback pin. The overall result of
these drift terms is a regulated output which has a slight positive temperature coefficient at output voltages below
5V and a slight negative TC at output voltages above 5V. Reference output current should be limited, for
regulator feedback networks, to approximately 60µA. The reference pin will draw ≈100µA when shorted to
ground and will not affect the internal reference/regulator, so that this pin can also be used as a pull-up for
LT1054 circuits that require synchronization.

7.4 Device Functional Modes

7.4.1 Main Operation
A review of a basic switched-capacitor building block is helpful in understanding the operation of the LT1054.
When the switch shown in Figure 13 is in the left position, capacitor C1 charges to the voltage at V1. The total
charge on C1 is q1 = C1*V1. When the switch is moved to the right, C1 is discharged to the voltage at V2. After
this discharge time, the charge on C1 is q2 = C1*V2. The charge has been transferred from the source V1 to the
output V2. The amount of charge transferred is shown in Equation 1.
Δq = q1 – q2 = C1(V1 – V2) (1)
If the switch is cycled f times per second, the charge transfer per unit time (that is, current) is as shown in
Equation 2.
I = f × L\q = f × C1(1 – V2) (2)
To obtain an equivalent resistance for a switched-capacitor network, this equation can be rewritten in terms of
voltage and impedance equivalence as shown in Equation 3.
V1 - V2 V1 - V2
I= =
(1/ fC1) REQUIV (3)
V1 V2

f
RL

C1 C2

Figure 13. Switched-Capacitor Building Block

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Device Functional Modes (continued)

A new variable, REQUIV, is defined as REQUIV = 1 / (f × C1). The equivalent circuit for the switched-capacitor
network is shown in Figure 14. The LT1054 has the same switching action as the basic switched-capacitor
building block. Even though this simplification does not include finite switch-on resistance and output-voltage
ripple, it provides an insight into how the device operates.
REQUIV
V1 V2

1 C2 RL
R EQUIV
fC1

Figure 14. Switched-Capacitor Equivalent Circuit

These simplified circuits explain voltage loss as a function of oscillator frequency (see Figure 7). As oscillator
frequency is decreased, the output impedance eventually is dominated by the 1 / (f × C1) term, and voltage
losses rise.
Voltage losses also rise as oscillator frequency increases. This is caused by internal switching losses that occur
due to some finite charge being lost on each switching cycle. This charge loss per-unit-cycle, when multiplied by
the switching frequency, becomes a current loss. At high frequency, this loss becomes significant and voltage
losses again rise.
The oscillator of the LT1054 is designed to operate in the frequency band where voltage losses are at a
minimum.

7.4.2 Shutdown
LT1054 can be put into a low quiescent current state by grounding the FB/SD pin. Once FB/SD is pulled low,
current being drawn from the supply will be approximately 100 µA.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The negative voltage converting and regulating ability of the LT1054 make this device optimal across a wide
range of applications. As it is a regulator, there are many general design considerations that must be taken into
account. Below will describe what to consider for using this device as a basic voltage inverter/regulator. This is
the most common application for the LT1054 and the fundamental building block for the applications shown in
System Examples.

8.2 Typical Application

8
FB/SD VCC VIN
+
2 μF
2 7
CAP+ OSC
R1
LT1054
+ 3 6 20 kΩ
10 μF GND VREF

4 5 R2
CAP− VOUT

VOUT
0.002 μF
+ +

100 μF
æ ö
ç VOUT ÷ æ V ö
R2 = R1ç + 1÷ = 20 kW çç OUT + 1÷÷
çç VREF - 40 mV ÷÷ è 1.21 V ø
è 2 ø
Pin numbers shown are for the P package.

Figure 15. Basic Voltage Inverter/Regulator

8.2.1 Design Requirements

For this design example, use the parameters listed in Table 2 as the input parameters.

Table 2. Design Parameters

Design Parameter Example Value
Input Voltage Range 3.5V to 15V
VOUT -5V
IOUT 100mA

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8.2.2 Detailed Design Procedure

When using LT1054 as a basic voltage inverter, determine the following:
• Input Voltage
• Desired output Voltage
• Desired Ripple
• Power Dissipation

[Link] Output Voltage Programming

The error amplifier of the LT1054 drives the PNP switch to control the voltage across the input capacitor (CIN),
which determines the output voltage. When the reference and error amplifier of the LT1054 are used, an external
resistive divider is all that is needed to set the regulated output voltage. shows the basic regulator configuration
and the formula for calculating the appropriate resistor values. R1 should be 20 kΩ or greater because the
reference current is limited to ±100 μA. R2 should be in the range of 100 kΩ to 300 kΩ.

[Link] Capacitor Selection

While the exact values of CIN and COUT are noncritical, good-quality low-ESR capacitors, such as solid tantalum,
are necessary to minimize voltage losses at high currents. For CIN, the effect of the ESR of the capacitor is
multiplied by four, because switch currents are approximately two times higher than output current. Losses occur
on both the charge and discharge cycle, which means that a capacitor with 1 Ω of ESR for CIN has the same
effect as increasing the output impedance of the LT1054 by 4 Ω. This represents a significant increase in the
voltage losses. COUT alternately is charged and discharged at a current approximately equal to the output
current. The ESR of the capacitor causes a step function to occur in the output ripple at the switch transitions.
This step function degrades the output regulation for changes in output load current and should be avoided. A
technique used to gain both low ESR and reasonable cost is to parallel a smaller tantalum capacitor with a large
aluminum electrolytic capacitor.
Frequency compensation is accomplished by adjusting the ratio of CIN to COUT.
For best results, this ratio should be approximately 1:10. Capacitor C1, required for good load regulation, should
be 0.002 μF for all output voltages.

[Link] Output Ripple

The peak-to-peak output ripple is determined by the output capacitor and the output current values. Peak-to-peak
output ripple is approximated as:
I
DV = OUT
2fCOUT
where
• ΔV = peak-to-peak ripple
• fOSC = oscillator frequency (4)
For output capacitors with significant ESR, a second term must be added to account for the voltage step at the
switch transitions. This step is approximately equal to:
(2IOUT)(ESR of COUT) (5)

[Link] Power Dissipation

The power dissipation of any LT1054 circuit must be limited so that the junction temperature of the device does
not exceed the maximum junction-temperature ratings. The total power dissipation is calculated from two
components–the power loss due to voltage drops in the switches, and the power loss due to drive-current losses.
The total power dissipated by the LT1054 is calculated as:
P = (VCC – VOUT ) IOUT + (VCC)(IOUT)(0.2)
where
• both VCC and VOUT are referenced to ground (6)

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The power dissipation is equivalent to that of a linear regulator. Limited power-handling capability of the LT1054
packages causes limited output-current requirements, or steps can be taken to dissipate power external to the
LT1054 for large input or output differentials. This is accomplished by placing a resistor in series with CIN as
shown in Figure 16. A portion of the input voltage is dropped across this resistor without affecting the output
regulation. Since switch current is approximately 2.2 times the output current and the resistor causes a voltage
drop when CIN is both charging and discharging, the resistor chosen is as shown:
Vx
Rx =
4.4 IOUT
where
• VX ≈ VCC − [(LT1054 voltage loss)(1.3) + |VOUT|]
• IOUT = maximum required output current (7)
The factor of 1.3 allows some operating margin for the LT1054.
When using a 12-V to −5-V converter at 100-mA output current, calculate the power dissipation without an
external resistor.
P = (12 V - | -5 V |)(100 mA) + (12 V)(100 mA)(0.2)
P = 700 mW + 240 mW = 940 mW (8)

VIN

1 8
FB/SD VCC

Rx 2 7
CAP+ OSC
LT1054
+ 3 6 R1
CIN GND VREF

4 5 R2
CAP− VOUT

VOUT
C1

COUT
+

Pin numbers shown are for the P package.

Figure 16. Power-Dissipation-Limiting Resistor in Series With CIN

At RθJA of 130°C/W for a commercial plastic device, a junction temperature rise of 122°C occurs. The device
exceeds the maximum junction temperature at an ambient temperature of 25°C. To calculate the power
dissipation with an external resistor (RX), determine how much voltage can be dropped across RX. The maximum
voltage loss of the LT1054 in the standard regulator configuration at 100 mA output current is 1.6 V.
VX = 12 V – [(1.6 V)(1.3) + |–5 V|] = 4.9 V (9)
and
4.9 V
Rx = = 11 W
(4.4)(100 mA) (10)

Copyright © 1990–2015, Texas Instruments Incorporated Submit Documentation Feedback 15

Product Folder Links: LT1054
LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015 [Link]

The resistor reduces the power dissipated by the LT1054 by (4.9 V)(100 mA) = 490 mW. The total power
dissipated by the LT1054 is equal to (940 mW − 490 mW) = 450 mW. The junction-temperature rise is 58°C.
Although commercial devices are functional up to a junction temperature of 125°C, the specifications are tested
to a junction temperature of 100°C. In this example, this means limiting the ambient temperature to 42°C. To
allow higher ambient temperatures, the thermal resistance numbers for the LT1054 packages represent worst-
case numbers, with no heat sinking and still air. Small clip-on heat sinks can be used to lower the thermal
resistance of the LT1054 package. Airflow in some systems helps to lower the thermal resistance. Wide printed
circuit board traces from the LT1054 leads help remove heat from the device. This is especially true for plastic
packages.

8.2.3 Application Curve

2
3.5 V ≤ VCC ≤ 15 V
1.8 Ci = Co = 100 μF

1.6

1.4 TJ = 125°C
Voltage Loss − V

1.2

1 TJ = 25°C

0.8

0.6

0.4
TJ = −55°C
0.2

0
0 10 20 30 40 50 60 70 80 90 100
Output Current − mA

Figure 17. Voltage Loss vs Output Current

8.3 System Examples

10 V
1N4002 100 kΩ
1 VCC 8 100-kΩ
FB/SD
+ Speed Control
5 μF
2 7
CAP+ OSC
LT1054
− + 3 6
10 μF
+ 1N5817 GND VREF
+ −
4 5
CAP− VOUT
Tach Motor

NOTE: Motor-Tach is Canon CKT26-T5-3SAE.

Pin numbers shown are for the P package.

Figure 18. Motor-Speed Servo

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 LT1054
[Link] SLVS033G – FEBRUARY 1990 – REVISED JULY 2015

System Examples (continued)

1 8
FB/SD VCC +

2 7 VOUT
CAP+ OSC
+ LT1054 −
10 μF 3 6
VIN GND VREF
QX
2 μF
+ 4 5
CAP− VOUT
RX
100 μF
+
VIN = −3.5 V to −15 V
VOUT = 2 VIN + (LT1054 Voltage Loss) + (QX Saturation Voltage)
VIN
Pin numbers shown are for the P package.

Figure 19. Negative-Voltage Doubler

VIN
3.5 V to 15 V
1N4001 1N4001
+
+ +
100 μF 10 μF
VOUT
1 8
FB/SD VCC

− +
2 7 2 μF
CAP+ OSC
LT1054
3 6
GND VREF

VIN = 3.5 V to 15 V 4 5
CAP− VOUT
VOUT ≈ 2 VIN − (VL + 2 V Diode)
VL = LT1054 Voltage Loss
Pin numbers shown are for the P package.

Figure 20. Positive-Voltage Doubler

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Product Folder Links: LT1054
LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015 [Link]

System Examples (continued)

VIN
3.5 V to 15 V

+
2.2 μF

1 8 1 8
FB/SD VCC FB/SD VCC
HP5082-2810
2 7 VOUT 2 7 CAP+ of
CAP+ OSC CAP+ OSC
SET LT1054 #1
+ 10 μF LT1054 #1 + 10 μF LT1054 #2
3 6 3 6
GND VREF GND VREF
+ 20 kΩ
10 μF R1
4 5 4 5
CAP− VOUT 40 kΩ + CAP− VOUT
10 μF

10 μF +
1N4002 + 0.002 μF 1N4002 10 μF
+
1N4002 R2 1N4002
500 kΩ
VOUT
IOUT ≅100 mA MAX
1N4002 100 μF
+ VIN = 3.5 V to 15 V
VOUT MAX ≈ −2 VIN + [LT1054 Voltage Loss +2 (VDiode)]
æ ö
ç VO U T ÷ æ V ö
R 2 = R1 ç + 1 ÷ = R1 çç O U T + 1 ÷÷
VR E F è 1.21 V
çç - 40 m V ÷÷ ø
è 2 ø
Pin numbers shown are for the P package.

Figure 21. 100-mA Regulating Negative Doubler

VI
3.5 V to 15 V
1N4001 1N4001
+

+VO +
100 μF
+
10 μF 1 8
− FB/SD VCC
2 7
CAP+ OSC

3 LT1054 6
+ GND VREF
10 μF
100 μF
4 5 +
CAP− VOUT
+ 1N4001
10 μF
1N4001
−

VI = 3.5 V to 15 V 1N4001 100 μF −VO

+VO ≈ 2 VIN − (VL + 2 VDiode) −VO ≈ −2 VI + (VL + 2 VDiode) +
VL = LT1054 Voltage Loss
+
Pin numbers shown are for the P package.

Figure 22. Dual-Output Voltage Doubler

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Product Folder Links: LT1054

 LT1054
[Link] SLVS033G – FEBRUARY 1990 – REVISED JULY 2015

System Examples (continued)

5 μF 12 V
+

1 8 1 8
FB/SD VCC FB/SD VCC
HP5082-2810
10 Ω
2 7 1/2 W 2 7
CAP+ OSC CAP+ OSC
R1 +
LT1054 #1 LT1054 #2
10 Ω 3 6 39.2 kΩ 10 μF 3 6
1/2 W GND VREF 0.002 μF GND VREF
+ 20 kΩ
4 5 R2 4 5
+ CAP− VOUT 200 kΩ CAP− VOUT
10 μF
VO = −5 V
IO = 0-200 mA
200 μF æ ö
+ ç VOUT ÷ æ V ö
R2 = R1ç + 1÷ = R1çç OUT + 1÷÷
V è 1.21 V
çç ÷÷ ø
REF
- 40 mV
è 2 ø
Pin numbers shown are for the P package.

Figure 23. 5-V to ±12-V Converter

5V
10 kΩ

+
Input TTL or 10 kΩ 10 μF
CMOS Low 40 Ω
2N2907 Zero Trim
for On
10 kΩ

Gain Trim
8 5 kΩ
0.022 μF 2 100 kΩ 301 kΩ 5 kΩ 6 A2 1 MΩ
− −
1 1/2 1/2 7
LT1013 LT1013 VOUT
3 100 kΩ 10 kΩ 5
+ 350 Ω +
A1 4
1 μF
200 kΩ

1 8
FB/SD VCC 5V

2 7
CAP+ OSC
+ 3 kΩ
10 μF LT1054 #1 2N2222
3 6
GND VREF
+ 100-μF
Tantalum Adjust Gain Trim For 3 V Out From
4 5 Full-Scale Bridge Output of 24 mV
CAP− VOUT

Pin numbers shown are for the P package.

Figure 24. Strain-Gage Bridge Signal Conditioner

Copyright © 1990–2015, Texas Instruments Incorporated Submit Documentation Feedback 19

Product Folder Links: LT1054
LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015 [Link]

System Examples (continued)

VI
3.5 V to 5.5 V

1 8
20 kΩ FB/SD VCC

2 7
CAP+ OSC
+ LTC1044
1 μF 3 6
1N914 GND VREF
(All)
1 8 4 5
FB/SD VCC CAP− VOUT
+
2 7 5 μF R2
CAP+ OSC 125 kΩ
LT1054 R1
+ 3 6 20 kΩ
10 μF GND VREF +
1 μF
+
0.002 μF R2 +
4 5 100 μF 3 kΩ VO
CAP− VOUT 125 kΩ
−

VI = 3.5 V to 5.5 V
VO = 5 V 2N2219
IO MAX = 50 mA

æ ö 1N914
1N5817
ç VOUT ÷ æ V ö
R2 = R1ç + 1÷ = R1çç OUT + 1÷÷
VREF è 1.21 V
çç - 40 mV ÷÷ ø
è 2 ø
Pin numbers shown are for the P package.

Figure 25. 3.5-V to 5-V Regulator

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Product Folder Links: LT1054

 LT1054
[Link] SLVS033G – FEBRUARY 1990 – REVISED JULY 2015

System Examples (continued)

5 μF 12 V
+

1 8 1 8
FB/SD VCC FB/SD VCC
HP5082-2810
10 Ω
2 7 1/2 W 2 7
CAP+ OSC CAP+ OSC
R1 +
LT1054 #1 LT1054 #2
10 Ω 3 6 39.2 kΩ 10 μF 3 6
1/2 W GND VREF 0.002 μF GND VREF
+ 20 kΩ
4 5 R2 4 5
+ CAP− VOUT 200 kΩ CAP− VOUT
10 μF
VO = −5 V
IO = 0-200 mA
200 μF æ ö
+ ç VOUT ÷ æ V ö
R2 = R1ç + 1÷ = R1çç OUT + 1÷÷
V è 1.21 V
çç ÷÷ ø
REF
- 40 mV
è 2 ø
Pin numbers shown are for the P package.

Figure 26. Regulating 200-mA +12-V to −5-V Converter

15 V
5 μF
+
11

20 kΩ 16 Digital
AD558
Input

2.5 V LT1004-2.5 15
1 8 14 13 12
FB/SD VCC

2 7
CAP+ OSC 20 kΩ
LT1054
+ 3 6
10 μF GND VREF

4 5
CAP− VOUT VO = −VI (Programmed)
100 μF
+

Pin numbers shown are for the P package.

Figure 27. Digitally Programmable Negative Supply

Copyright © 1990–2015, Texas Instruments Incorporated Submit Documentation Feedback 21

Product Folder Links: LT1054
LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015 [Link]

System Examples (continued)

VI = 5 V
2 μF
+

50 kΩ
1N5817 1 8
FB/SD VCC

1N5817 10 μF
VO + 2 7
8V CAP+ OSC
+ LT1054
100 μF 0.03 μF 10 kΩ 3 6
10 kΩ
5.5 kΩ GND VREF

5V 4 5
10 kΩ CAP− VOUT
−
1/2
2.5 kΩ LT1013
+

0.1 μF

Pin numbers shown are for the P package.

Figure 28. Positive Doubler With Regulation (5-V to 8-V Converter)

VI
3.5 V to 15 V
2μF
1 8 +
FB/SD VCC

2 7
CAP+ OSC
LT1054 R1
+ 3 6 60 kΩ
10 μF GND VREF

100 μF
4 5 +
CAP− VOUT
R2 +
+ 1 MΩ 0.002 μF
10 μF 1N4001
1N4001
−VO
VI = 3.5 V to 15 V
VO MAX ≈ 2 VIN + (VL + 2 VDiode) 100 μF
VL = LT1054 Voltage Loss
æ ö
ç VOUT ÷ æ V ö
R2 = R1ç + 1÷ = R1çç OUT + 1÷÷
VREF è 1.21 V
çç - 40 mV ÷÷ ø
è 2 ø
Pin numbers shown are for the P package.

Figure 29. Negative Doubler With Regulator

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Product Folder Links: LT1054

 LT1054
[Link] SLVS033G – FEBRUARY 1990 – REVISED JULY 2015

9 Power Supply Recommendations

The LT1054 alternately charges CIN to the input voltage when CIN is switched in parallel with the input supply and
then transfers charge to COUT when CIN is switched in parallel with COUT. Switching occurs at the oscillator
frequency. During the time that CIN is charging, the peak supply current will be approximately equal to 2.2 times
the output current. During the time that CIN is delivering charge to COUT the supply current drops to approximately
0.2 times the output current. An input supply bypass capacitor will supply part of the peak input current drawn by
the LT1054 and average out the current drawn from the supply. A minimum input supply bypass capacitor of
2µF, preferably tantalum or some other low ESR type is recommended. A larger capacitor may be desirable in
some cases, for example, when the actual input supply is connected to the LT1054 through long leads, or when
the pulse current drawn by the LT1054 might affect other circuitry through supply coupling.
In addition to being the output terminal, VOUT is tied to the substrate of the device. Special care must be taken in
LT1054 circuits to avoid making VOUT positive with respect to any of the other terminals. For circuits with the
output load connected from VCC to VOUT or from some external positive supply voltage to VOUT, an external
transistor must be added (see Figure 30). This transistor prevents VOUT from being pulled above GND during
startup. Any small general-purpose transistor such as a 2N2222 or a 2N2219 device can be used. Resistor R1
should be chosen to provide enough base drive to the external transistor so that it is saturated under nominal
output voltage and maximum output current conditions.

R1 £
( VOUT )b
IOUT (11)
VIN

1 8
FB/SD VCC Load

2 7 VOUT
CAP+ OSC
R1
LT1054
+ 3 6
CIN GND VREF

4 5
CAP− VOUT

COUT
+

Figure 30. Circuit With Load Connected from VCC to VOUT

Copyright © 1990–2015, Texas Instruments Incorporated Submit Documentation Feedback 23

Product Folder Links: LT1054
LT1054
SLVS033G – FEBRUARY 1990 – REVISED JULY 2015 [Link]

10 Layout

10.1 Layout Guidelines

• Try to run the feedback trace as far from the noisy power or clocking traces as possible. In the case that the
OSC pin is not being used, as in Figure 31, the FB trace can be ran on a lower layer under the OSC pin.
When OSC is being utilized by a noisy clocking signal, it is recommended to run the FB trace on a lower layer
through the Vref pin.
– Keep the FB trace to be as direct as possible and somewhat thick. These two sometimes involve a trade-
off, but keeping it away from EMI and other noise sources is the more critical of the two.
• Keep the external capacitor traces short, specifically on the CAP+ and CAP- nodes that have the fastest rise
and fall times.
• Make all of the power (high current) traces as short, direct, and thick as possible. It is good practice on a
standard PCB board to make the traces an absolute minimum of 15 mils (0.381 mm) per Ampere.

10.2 Layout Example

Ground
2.0 PF

FB/SD 1 8 VCC Positive Supply

CAP+ 2 7 OSC R1
Ground
GND 3 6 VREF
10 PF R2
&$3í 4 5 VOUT

0.002 PF

100 PF

Ground

Figure 31. Basic Inverter/Regulator Layout

24 Submit Documentation Feedback Copyright © 1990–2015, Texas Instruments Incorporated

Product Folder Links: LT1054

 LT1054
[Link] SLVS033G – FEBRUARY 1990 – REVISED JULY 2015

11 Device and Documentation Support

11.1 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At [Link], you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.2 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 1990–2015, Texas Instruments Incorporated Submit Documentation Feedback 25

Product Folder Links: LT1054
 PACKAGE OPTION ADDENDUM

[Link] 24-Aug-2018

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

LT1054CDW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LT1054C

& no Sb/Br)
LT1054CDWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LT1054C
& no Sb/Br)
LT1054CDWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LT1054C
& no Sb/Br)
LT1054CDWRE4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LT1054C
& no Sb/Br)
LT1054CDWRG4 ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM 0 to 70 LT1054C
& no Sb/Br)
LT1054CP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 LT1054CP
& no Sb/Br)
LT1054CPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type 0 to 70 LT1054CP
& no Sb/Br)
LT1054IDW ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LT1054I
& no Sb/Br)
LT1054IDWG4 ACTIVE SOIC DW 16 40 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LT1054I
& no Sb/Br)
LT1054IDWR ACTIVE SOIC DW 16 2000 Green (RoHS CU NIPDAU Level-1-260C-UNLIM -40 to 85 LT1054I
& no Sb/Br)
LT1054IP ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 LT1054IP
& no Sb/Br)
LT1054IPE4 ACTIVE PDIP P 8 50 Green (RoHS CU NIPDAU N / A for Pkg Type -40 to 85 LT1054IP
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 24-Aug-2018

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 12-Feb-2019

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
LT1054CDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1
LT1054IDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 12-Feb-2019

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LT1054CDWR SOIC DW 16 2000 350.0 350.0 43.0
LT1054IDWR SOIC DW 16 2000 350.0 350.0 43.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
DW 16 SOIC - 2.65 mm max height
7.5 x 10.3, 1.27 mm pitch SMALL OUTLINE INTEGRATED CIRCUIT

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224780/A

[Link]
 PACKAGE OUTLINE
DW0016A SCALE 1.500
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
14X 1.27
16
1

10.5 2X
10.1 8.89
NOTE 3

8
9
0.51
16X
0.31
7.6
B 0.25 C A B 2.65 MAX
7.4
NOTE 4

0.33
TYP
0.10

SEE DETAIL A
0.25
GAGE PLANE

0.3
0 -8 0.1
1.27
0.40 DETAIL A
(1.4) TYPICAL

4220721/A 07/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.
5. Reference JEDEC registration MS-013.

[Link]
 EXAMPLE BOARD LAYOUT
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP

(9.3)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220721/A 07/2016

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
DW0016A SOIC - 2.65 mm max height
SOIC

16X (2) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

R0.05 TYP
(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220721/A 07/2016

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 IMPORTANT NOTICE AND DISCLAIMER

TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE
DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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