GK Enhanced Controller Schematic

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This document provides a 3 page schematic for a GK enhanced controller with telltale battery. The schematic shows the system block diagram on page 1 including components like the CPU, memory…

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David Diehl

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 1 OF 24

4 3 2 1
REVISIONS
REV ECO DESCRIPTION BY/DATE CHK/DATE
EA - BASED ON 757 044 11 REV A 3OCT05 -
EB - LOTS OF CHANGES - SEE NOTES ON LEFT TWG/30JUL06 -
EC - A FEW MORE CHANGES TWG/29AUG06 -
A 13227 PRODUCTION RELEASE TWG/29AUG06 RBP/21SEP06

BUS CONTROLLER SRAM 4MB

D DEVICE SELECTS .5M X 32 X 2 RTC 1
D
CYCLE TIMING MEMORY CARD

SA [31:0]
ADDR BOOT ROM
LATCH
GAME

960KA PIXEL

CG
MEMORY
BOARD AUDIO MEM
CONNS

DATA DATA SD [31:0]

BUFF/ STEERING
LATCH

CLOCKS &
RESETS

POWER SUPPLIES

POWER 5V,3.3V,1.5V,1.8V, BATTERY

MONITOR 2.5V,5VA,12VA
& WATCHDOG AND CHARGER CG MEMORY SIGNALS
C CGBL0:15 C
CGBK0:15

AUDIO MEMORY BUS

SHT 1 BLOCK DIAGRAM YAA0:23

YD0:7

SHT 2 960 CPU AND 5V TO 3V TRANSLATION SRAM ENABLE

SDRAM
TELL TALE
DOOR SECURITY DOOR STATUS 32/64MB BIT BLITZ 32MB SDRAM
SHT 3 CLOCK GENERATOR CPLD 1M X 32

BATTERY LOW
DSPA0:23
SHT 4 BUS CONTROLLER DSPD16:47

SHT 5 BUS TERMINATORS

AUDIO CPLD
SHT 6 BIT GRAPHICS FPGA R,G,B [7:0]

AUDIO CPLD
SHT 7 GRAPHICS SDRAM
VIDEO DAC
SHT 8 VIDEO DAC AMP
TRUE COLOR DIGITAL AUDIO
DAC
B SHT 9 SRAM AMP
AUDIO OUT L&R B
AUX IN L&R
VOLCTL ADC

DWG_NO
SHT 10 SERIAL FPGA
R,G,B,H&VSYNV MOTHERBOARD
SHT 11 SERIAL TRANSCEIVERS

757 044 11W

M/B

CONNS

SHT 12 SENET DRIVERS

SERIAL PORTS

SHT 13 MEMORY MEZANNINE CONNECTORS

SERIAL FPGA SENET 1 & 2

SHT 14 MOTHERBOARD CONNECTORS

I2C
STATUS LEDS
QUART 1&2
SHT 15 DC-DC CONVERTERS SENET 1&2
I2C 1&2
LEDS
SERIAL VOL CTL

SHT 16 BATTERY BACKUP

OPTION
OPTION CARD RTC 2
CARD
SHT 17 POWER MONITOR/ RESET
CONN

SHT 18 TELL TALE

A SHT 19 RTC A

SHT 20 AUDIO CPLD, SDRAM ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
SHT 21 AUDIO DSP INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
SHT 22 AUDIO ADC OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
SHT 23 AUDIO DAC INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
DWG_SIZE DWG_NO REV_LTR

C 757 044 11W A

SHT 24 OPTION MEZANNINE CONNECTOR DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEO06 NONE SHT 1 OF 24

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 1

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 2 OF 24
4 3 2 1

SD[0:31]
C344 C203 C184 C181 C190 C186
1 1 1 1 1 1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
LAD[0:31]
5/D4,6/C4,9/D4,10/C4,13/D4,20/C4,24/D4
2 2 2 2 2 2
25V 25V 25V 25V 25V 25V

3.3V 3.3V
C195 C329 C178 C232 C183 C187 C144
1 1 1 1 1 1 1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 6.8uF

D 25V
2
25V
2
25V
2
25V
2
25V
2
25V
2 2
16V
3.3V
D

22
35
50

22
35
50
7

7
U89 U93
LAD0 5 52 SD0 LAD16 5 52 SD16

VCC1
VCC2
VCC3
VCC4

VCC1
VCC2
VCC3
VCC4
1A1 1B1 1A1 1B1 C330 C46 C353 C352
LAD1 6 51 SD1 LAD17 6 51 SD17 1 1 1 1
1A2 1B2 1A2 1B2 0.1uF 0.1uF 0.1uF 0.1uF
LAD2 8 49 SD2 LAD18 8 49 SD18
1A3 1B3 1A3 1B3
LAD3 9 48 SD3 LAD19 9 48 SD19 2 2 2 2
1A4 1B4 1A4 1B4 25V 25V 25V 25V
LAD4 10 47 SD4 LAD20 10 47 SD20
1A5 1B5 1A5 1B5
LAD5 12 45 SD5 LAD21 12 45 SD21
1A6 1B6 1A6 1B6
5V LAD6 13 44 SD6 LAD22 13 44 SD22
1A7 1B7 1A7 1B7
LAD7 14 43 SD7 LAD23 14 43 SD23
1A8 1B8 1A8 1B8
5V
LAD8 15 42 SD8 LAD24 15 42 SD24
2A1 2B1 2A1 2B1
LAD9 16 41 SD9 LAD25 16 41 SD25 3.3V
2A2 2B2 2A2 2B2

M11
C10
D12
A14

K12

P14
U87 17 40 17 40

M2
M5
LAD10 SD10 LAD26 SD26

C4
A1

P1
L3
2A3 2B3 2A3 2B3
LAD11 19 38 SD11 LAD27 19 38 SD27
2A4 2B4 2A4 2B4
2 2 2 LAD12 20 37 SD12 LAD28 20 37 SD28
2A5 2B5 2A5 2B5 C409 C419 C73 C415
LAD13 21 36 SD13 LAD29 21 36 SD29 1 1 1 1
2A6 2B6 2A6 2B6 0.1uF 0.1uF 0.1uF 0.1uF
2.2K 2.2K 2.2K LAD14 23 34 SD14 LAD30 23 34 SD30
2A7 2B7 2A7 2B7
R170 R166 R168 LAD15 24 33 SD15 LAD31 24 33 SD31 2 2 2 2
2A8 2B8 2A8 2B8 25V 25V 25V 25V
1 1 1 B12 LAD0
A12 LAD1 56 1 56 1
1OE 1DIR 1OE 1DIR
B10 LAD2 29 28 29 28
2OE 2DIR 2OE 2DIR
RST5 B13 C9 LAD3
12/B4,17/B1,23/B4
CPU_CCLK2 B11 A11 LAD4 2 3 2 3
2/C4,3/C1 1CLKAB 1SAB 1CLKAB 1SAB
LRDYJ G2 A10 LAD5 27 26 27 26
2/B3,2/A4 2CLKAB 2SAB 2CLKAB 2SAB
B9 LAD6 55 54 55 54
1CLKBA 1SBA 1CLKBA 1SBA
LINT0J C14 A9 LAD7 30 31 30 31
2/A4 2CLKBA 2SBA 2CLKBA 2SBA
LINT1 C13 C8 LAD8
2/A4

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
LINT2 A13 A8 LAD9
2/A4
LINT3J C12 B8 LAD10
2/A4
A7 LAD11
B7 LAD12

4
11
18
25
32
39
46
53

4
11
18
25
32
39
46
53
PI74LPT16646A PI74LPT16646A
C7 LAD13
TRANSCEIVER TRANSCEIVER
A6 LAD14
BADAC C3 B6 LAD15
FAILUREJ K2 A5 LAD16
CACHE F3 A4 LAD17 LBUFLOEJ
4/B3
B5 LAD18 LATCHLO
4/B3
A3 LAD19 LBUFDIR
4/B3
C6 LAD20 LATCHHI
4/B3
C 2/A4
LHOLD
LHLDA
C1
D3
B4
B3
LAD21
LAD22
4/B3
LBUFHOEJ
SA[0:31] C
5/C2 4/C2,4/C4,5/D3,9/D3,10/C4,13/D4,20/C4
B1 LAD23
1 B2 LAD24
4/C4,5/D4
R169 C2 LAD25
BSA[0:3]
3.3K E2 LAD26 3.3V 3.3V
E3 LAD27
2 E1 LAD28
F1 LAD29 5V
G1 LAD30
F2 LAD31 3.3V

22
35
50

22
35
50
7

7
U88 U90

14
NC1=D13,D14,E12, LAD0 5 52 BSA0 LAD16 5 52 SA16

VCC1
VCC2
VCC3
VCC4

VCC1
VCC2
VCC3
VCC4
1A1 1B1 1A1 1B1

PWR
OPTION E14,F12,F13 D1 LALEJ 1 LAD1 6 51 BSA1 LAD17 6 51 SA17
1A2 1B2 1A2 1B2 C103 C377 C416 C440
F14,G12,G13,G14, D2 LADSJ 13 750 OHMS LAD2 8 49 BSA2 LAD18 8 49 SA18 1 1 1 1
1A3 1B3 1A3 1B3 0.1uF 0.1uF 0.1uF 0.1uF
CPU_CCLK2 H12,H13,H14 H1 LRDJ 2 LAD3 9 48 BSA3 LAD19 9 48 SA19
1A4 1B4 1A4 1B4
J12,J13,J14,K13, J1 LDTRJ 12 R1 5V LAD4 10 47 SA4 LAD20 10 47 SA20 2 2 2 2
2/C4,3/C1 C189 1A5 1B5 1A5 1B5 25V 25V 25V 25V
1 K14,L2,L13 L1 LAD5 12 45 SA5 LAD21 12 45 SA21
10pF 1A6 1B6 1A6 1B6
L14,M1,M6,M7,M8, H3 3 RP14 LAD6 13 44 SA6 LAD22 13 44 SA22
C188 1A7 1B7 1A7 1B7
2 M14,N2,N3,N4, 11 750 1 LAD7 14 43 SA7 LAD23 14 43 SA23
50V 0.1uF 1A8 1B8 1A8 1B8
M9,M12,M13 4
N10,N11,N12,N13, H2 LBE0J 10 2 LAD8 15 42 SA8 LAD24 15 42 SA24
25V 2A1 2B1 2A1 2B1
N14,P2,P3,P4 G3 LBE1J LAD9 16 41 SA9 LAD25 16 41 SA25
2A2 2B2 2A2 2B2
N5,N6,N7,N8,N9 J2 LBE2J 5 R2 LAD10 17 40 SA10 LAD26 17 40 SA26 3.3V
2A3 2B3 2A3 2B3
P10,P11,P12 K1 LBE3J 9 LAD11 19 38 SA11 LAD27 19 38 SA27
2A4 2B4 2A4 2B4
P5,P6,P7,P8,P9, 6 750 OHMS LAD12 20 37 SA12 LAD28 20 37 SA28
2A5 2B5 2A5 2B5
LRDYJ 8 LAD13 21 36 SA13 LAD29 21 36 SA29
2A6 2B6 2A6 2B6 C338 C333 C371 C331

GND
2/C4,2/A4
LAD14 23 34 SA14 LAD30 23 34 SA30 1 1 1 1
2A7 2B7 2A7 2B7 0.1uF 0.1uF 0.1uF 0.1uF

7
R167 5V LAD15 24 33 SA15 LAD31 24 33 SA31
2A8 2B8 2A8 2B8
1 2 R221 3.3V 3.3V 2 2 2 2
R177 25V 25V 25V 25V
56 1 1 2 56 1 1 2
1OE 1DIR 1OE 1DIR
2.2K 29 28 29 28
2OE 2DIR 2OE 2DIR
REF_U87 80960KA 2.2K 2.2K
A2
B14

E13

K3
L12

P13
C5
C11

M3
M4
M10
N1

BALEJ 2 3 BALEJ 2 3
2/B3,2/B2,4/C1,4/B3,6/C4,24/C3 1CLKAB 1SAB 2/B3,2/B2,4/C1,4/B3,6/C4,24/C3 1CLKAB 1SAB
27 26 27 26
2CLKAB 2SAB 2CLKAB 2SAB
55 54 55 54
1CLKBA 1SBA 1CLKBA 1SBA
30 31 30 31
2CLKBA 2SBA 2CLKBA 2SBA
3.3V

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
1 1 1 1
R180 R220 R175 R176
C167
B 150 150 150 150 1
6.8uF B

4
11
18
25
32
39
46
53

4
11
18
25
32
39
46
53
2 PI74LPT16646A 2 2 PI74LPT16646A 2 2
TRANSCEIVER TRANSCEIVER 16V

DWG_NO
3.3V

C405 C443 C407 C72

1 1 1 1
0.1uF 0.1uF 0.1uF 0.1uF

757 044 11W

2 2 2 2
25V 25V 25V 25V
3.3V

LBE[0:3]J LAD[0:31]
BLE[0:3]J
22
35
50
7

U92 5V 5V 5V
4/B4,5/D4,6/C4,24/A3
LBE0J 5 52 BLE0J
VCC1
VCC2
VCC3
VCC4

1A1 1B1
LBE1J 6 51 BLE1J
1A2 1B2

14
LBE2J 8 49 BLE2J
1A3 1B3

PWR

PWR
LBE3J 9 48 BLE3J LAD0 1 LAD12 1 LAD24 1
1A4 1B4
LALEJ 10 47 R174 10 BALEJ LAD1 13 750 OHMS LAD13 13 750 OHMS LAD25 13 750 OHMS
1A5 1B5 2/B2,2/B2,4/C1,4/B3,6/C4,24/C3
LRDJ 12 45 1 2 BRDJ LAD2 2 LAD14 2 LAD26 2
1A6 1B6 4/C1,4/B3,5/D4,5/C2,5/C1,5/A4,9/C3,9/B3,24/C3
LADSJ 13 44 BADSJ LAD3 12 R1 5V LAD15 12 R1 5V LAD27 12 R1 5V
1A7 1B7 4/C1,4/B3,5/D4,6/C4,24/C3
LDTRJ 14 43 BDTRJ
1A8 1B8 4/B3
LAD4 3 RP15 LAD16 3 RP16 LAD28 3 RP17
C249 C179 C180
LINT0J 15 42 IRQQ2J LAD5 11 750 1 LAD17 11 750 1 LAD29 11 750 1
2/C4 2A1 2B1 10/B3 0.1uF 0.1uF 0.1uF
LINT1 16 41 PADS_INT LAD6 4 LAD18 4 LAD30 4
2/C4 2A2 2B2 4/B3
LINT2 17 40 PS_INT LAD7 10 2 LAD19 10 2 LAD31 10 2
2/C4 2A3 2B3 5/C1 25V 25V 25V
LINT3J 19 38 IRQQ1J
2/C4 2A4 2B4 10/B3
LRDYJ 20 37 RDYJ LAD8 5 R2 LAD20 5 R2 5 R2
2/C4,2/B3 2A5 2B5 4/C1,4/B3,5/B3,6/C4
LHOLD 21 36 BHOLD LAD9 9 LAD21 9 9
2/C4 2A6 2B6 4/B3
23 34 LAD10 6 750 OHMS LAD22 6 750 OHMS 6 750 OHMS
2A7 2B7
24 33 3.3V LAD11 8 LAD23 8 8
2A8 2B8

GND

GND
R173

7
BHLDA 56 1 1 2
4/B3,5/C1 1OE 1DIR
29 28
2OE 2DIR
2.2K
2 3
1CLKAB 1SAB
A 27
55
2CLKAB 2SAB
26
54 A
1CLKBA 1SBA
30 31
2CLKBA 2SBA
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

1 1
R172 R171
150 150
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
4
11
18
25
32
39
46
53

2 PI74LPT16646A 2 9295 PROTOTYPE DRIVE RENO NV 89521

TRANSCEIVER INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 2 OF 24

4 3 2 1

2 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 3 OF 24
4 3 2 1

D D

3.3V 3.3V

1
3.3V
C138 C177
1 1

1
0.1uF 0.1uF
C141
1 2 2
0.1uF 25V 25V
3.3V
2

1
25V
3.3V

20
1
U61

1
2 R68 CPU_CCLK2

VCCA
VCCB
OA0 2/C4,2/C4
3 R66 1 2 BC_CCLK2

16
OA1 4/C1,4/B4,4/B3
U62 CLK2 10 4 R64 1 2 47 SER_CCLK2
INA OA2 10/C4,10/B3
6 R62 1 2 47 CCLK2
OA3 17/C4,17/B4
48 3 4 9 7 R58 1 2 47 OPTBD_CCLK2
OEA OA4 24/B2,24/C3
2 1 2 47 R69
7 CLK1 11 19 47 R67 1 2 BC_CCLK
INB OB0 4/C1,4/A4,4/B3
24 6 18 R65 1 2 GX_CCLK
OB1 6/C4,6/D4
LEGACYJ 5 10 12 17 R63 1 2 22 SER_CCLK
4/B3,10/B3,13/B3,20/C4 OEB OB2 10/C4,10/B3
15 R61 1 2 22 CCLK
OB3 17/C4,17/B4
12 11 13 1 14 1 2 22 OPTBD_CCLK
OB4 24/B2,24/C3

GNDQ
GNDA
GNDB
12 R59 22
3.3V 24 1 150 13 22
MON
L9 14 9
1 2 LEGACY 15 2 1

5
16
8
6/D4,13/B3,18/C4 PI49FCT3805
R60
50
PI3C3126 2.2K

8
3.3VC 2

C146 C252
C 0.1uF
1 1 C145 1
6.8uF 0.1uF C
2 2 16V 2
25V 25V

1
14.7456MEGHz
Y4

16
4
2 U76

VDD1
VDD2
20 1
32XIN 32XOUT
7 2
XTALOUT 32K
6 R133
XTALIN
8 3.5M R136 1 2
XBUF
VID_MODE0 14 10 PIXEL_CLK R135 1 2 GX_PXLCLK
6/C1 S0 CPUCLK 6/D4,6/C1
VID_MODE1 15 12 48MHZ 48MHZGX R134 1 2 22 GX_48MHZ
6/C1 S1 CLKA 6/C4,6/D4
VID_MODE2 17 11 1 2 22 SER_29MHZ
6/C1 S2_SPND CLKB 10/B4,10/B3
3 12MHZ 22
CLKC
3.3VC 19 9 24MHZ 22
VBATT CLKD
18 13 29MHZ

GND
SHTDN_OE CLKF

1 1 1 1 CY2291F

5
R132 R131 R130 R129 CLK_GEN
3.3K 3.3K 3.3K 2.2K
2 2 2 2
3.3V 32906800
32905191

B B

DWG_NO
A 47.9993MHZ

757 044 11W

B 47.9992MHZ
C 11.996MHZ
D 23.9992MHZ
F 29.4912MHZ

VID_MODE 2 1 0
0 0 0 26.672MHZ
0 0 1 25.175MHZ
0 1 0 31.5MHZ
0 1 1 40.0MHZ
1 0 0 49.5MHZ
1 0 1 65.0MHZ
1 0 1 35.0MHZ
1 1 1 33.0MHZ

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 3

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 4 OF 24
4 3 2 1

3.3V 2.5V_BC

C236 C239 C242 C312 C241 C234 C310 C311 C67 C233 C309 C316 C123 C237 C235 C243 C238 C148 C313 C314 C244
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 6.8uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2 2 2 2 2 2 2 2 2 2 2 2 2 16V 2 2 2 2 2 2 2 2
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V

D 3.3V
D
1 1 1 1
R70 R72 R73 R71
4.7K 4.7K 4.7K 4.7K

J10 2 2 2 2
JTAG_TMS JTAG_TMS
6/A2,10/C4
JTAG0_TDI
JTAG_TDO JTAG_TDO
10/C4
JTAG_TCK JTAG_TCK
6/A2,10/C4
JTAG1_TDI
6/A2
3.3V

3.3V 2.5V_BC

3.3V

105
117
130
144
156
170
184
197
208

128
171
186
196
R216

12
26
39
53
65
78
92

28
66
76
91
2.2K U73
10 DB1

VCCO10
VCCO11
VCCO12
VCCO13
VCCO14
VCCO15
VCCO16
VCCO1
VCCO2
VCCO3
VCCO4
VCCO5
VCCO6
VCCO7
VCCO8
VCCO9

VCCINT1
VCCINT2
VCCINT3
VCCINT4
VCCINT5
VCCINT6
VCCINT7
VCCINT8
2 DB1 4/C1
R227 4.7K 2 14 DB2
TMS DB2 4/C1
1 2 159 15 DB3
TDI DB3 4/C1
157 16 DB4
REF_U74 TDO DB4 4/C1
3.3V 3.3V R218 4.7K 207 23 DB5
TCK DB5 4/C1
1 2 29 DB6
DB6 4/C1
52 30 PADS1
C240 M0 PADS1 13/A4,13/B4
1 R217 4.7K 50 33 PADS2
0.1uF M1 PADS2 13/A4,13/B3
8 1 2 54 34 PADS3
XC17S50 M2 PADS3 13/A4,13/B3

8
7
2 DIP U74 35 PADS4
25V PADS4 13/A4,13/B4
155 36

VCC2
VCC1
PADS5
CCLK PADS5 13/A4,13/B4
R215 1 106 37 PADS6
DATA PGM PADS6 13/A4,13/B4
1 2 6 2 104 SA[0:31]
NC CLK DONE DEBUG HEADERS
4 107 3 SA4
CE INIT BSA4 2/C1,4/C4,5/D3,9/D3,10/C4,13/D4,20/C4

GND
0 3 161 4 SA3
OE/RST TP14 WE BSA3
OPTION 160 5 SA2
TP13 CS BSA2
153 8 SA1 J15

5
DIN/D0 BSA1
C TP15
154
DOUT/BUSY DB13
9 DB13
4/C1 4/C2
DB1
DB3
DB2
DB4
4/C2 C
4/C2 4/C2
SA[0:31] 17 RTC1_SRAM_BOEJ DB5 DB6
RTC_SRAM_BOE 5/D1 4/C2 4/C2
SA31 41 18 RTCDOUTJ DB7 DB8
2/C1,4/C2,5/D3,9/D3,10/C4,13/D4,20/C4 A31 RTC_DOUT 19/B3 4/B2 4/B2
SA30 42 21 RTCDILOJ BC_CCLK BC_CCLK2
A30 RTC_DI_LO 19/C3 3/C1,4/A4,4/B3 3/C1,4/B4,4/B3
SA29 43 22 RTCDIHIJ
A29 RTC_DI_HI 19/C3
SA28 45 164 RTC1_CSJ
A28 RTC1SEL 19/C3
SA27 46 166 RTC2_CSJ J14
A27 RTC2CS 10/B4
FPGA_DONE SA26 47 120 BOOTCSJ SRDJ SWR0J
6/A4,10/D4,17/C4 A26 BOOTCS 13/B4 4/B2,5/D2,5/A3,10/C3,13/B3,18/C4,20/C4,24/C3 4/B2,5/B3,5/D2,13/B3,20/C4,24/C3
SA25 48 121 GAMECSJ BRDJ RDYJ
A25 GAMECS 13/B4 2/B3,4/B3,5/D4,5/C2,5/C1,5/A4,9/C3,9/B3,24/C3 2/A3,4/B3,5/B3,6/C4
SA24 49 122 PIXELCSJ BALEJ BADSJ
A24 VBITCS 13/B3 2/B3,2/B2,2/B2,4/B3,6/C4,24/C3 2/A3,4/B3,5/D4,6/C4,24/C3
SA23 57 123 MEMBDCSJ DB9 DB10
A23 MEMBDCS 4/C1,13/B4 4/B2 4/B2
SA22 58 125 AUDIOMEMCSJ PDOEJ RST3
A22 AUDIOMEMCS 13/B4,20/B3 4/B2 17/B1
SA21 59 126 R123 22 MEM_ADD
A21 MEM_ADD 13/B4
SA20 61 127 R124 1 2 22 MDIR
A20 MDIR 13/B3
SA19 62 129 R121 1 2 22 MOEJ J12
A19 MEMOE 13/B4
BSA[0:3] SA18 63 132 R122 1 2 22 MLATCH_DATA DB11 DB12
A18 MLATCH_DATA 13/B3 4/B2 4/B2
SA17 67 133 R54 1 2 22 MEM_DATA DB13 SRAM1CSJ
2/C1,5/D4 A17 MEM_DATA 13/B3 4/C2 4/B2,18/C4
SA16 68 134 1 2 BLITZCSJ DB15 DB16
A16 BLITCS 4/C1 4/B2 4/B2
135 R55 22 MLATCH_ADD SRAM0CSJ SERFPGACSJ
MLATCH_ADD 13/B3 4/B2,18/C3 4/B2,10/B3
BSA3 69 136 1 2 ENET_DETJ MEMBDCSJ BLITZCSJ
A3 ENET_DET 13/C3 4/C2,13/B4 4/C2
BSA2 70 138 DB11
A2 DB11 4/C1
BSA1 71 139 DB12 3.3V
A1 DB12 4/C1
BSA0 73 140 BC_LED6 J13
A0 BC_LED6 14/A4
141 R516 22 SERFPGACSJ GXDB1
SERFPGACS 4/C1,10/B3 6/C1
142 1 2 Q1CSJ GXDB2
Q1CS 10/B3 6/C1
BALEJ 31 146 Q2CSJ SERDB1
2/B3,2/B2,2/B2,4/C1,6/C4,24/C3 ALE Q2CS 10/B3
BRDJ 27 147 SENET1CSJ SERDB2
2/B3,4/C1,5/D4,5/C2,5/C1,5/A4,9/C3,9/B3,24/C3 RD SENET1CS 10/B3
BC_CCLK 182 148 SENET2CSJ SERDB3
3/C1,4/C1,4/A4 CCLK/GCK2 SENET2CS 10/B3
BC_CCLK2 185 BC2MB[1:2]
3/C1,4/C1,4/B4 CCLK2/GCK3
RDYJ 95 151 DB15
2/A3,4/C1,5/B3,6/C4 RDY DB15 4/C1 14/A2
RST3J 74 152 VOLCTLCSJ SERDB4
6/D4,10/C3,13/B3,17/B1,18/D2,20/C4,21/C4,24/B3 RST VOLCTLCS 10/B3,20/A4,20/C4
BLE[0:3]J BADSJ 75 162 BC2MB1 SERDB5 SERDB[1:6]
2/A3,4/C1,5/D4,6/C4,24/C3 ADS BC2MB1
BDTRJ 81 163 BC2MB2 SERDB6
2/B3,5/D4,6/C4,24/A3 2/A3 DTR BC2MB2 10/B4
BLE3J 82 167 WATCHDOGCSJ OPTION
BE3 WATCHDOGCS 17/C4
BLE2J 83 168 AUDIO1CSJ
BE2 AUDIO1CS 20/A4,20/C4
BLE1J 84 172 AUDIO2CSJ
BE1 AUDIO2CS 20/A4,20/C4
BLE0J 86 173 PDOEJ
BE0 PD5OE 4/C1
174 OPTBD1CSJ
OPTBD1CS 24/B3
B GX_HLDAJ 109
OPTBD2CS
175
176
OPTBD2CSJ
DB16
24/B3 B
5/C2 HLDA1 DB16 4/C1
GX_HOLD 87
6/C4 HRQ1
OPTBD_HOLD 88 204 DB7

DWG_NO
24/B3 HRQ2 DB7 4/C1
BHLDA 89 6 DB8
2/A4,5/C1 BHLDA DB8 4/C1
GX_HLDA 90 R51
5/C2,6/C4 HLDA1
OPTBD_HLDA 94 181 1 2 R252 SWR0J
24/B3 HLDA2 SWR0 4/C1,5/B3,5/D2,13/B3,20/C4,24/C3
OPTION BHOLD 96 187 1 2 R50 SRDJ
2/A3 BHRQ SRD 4/C1,5/D2,5/A3,10/C3,13/B3,18/C4,20/C4,24/C3
180 47 ohms 1 2 SWR1J
SWR1 5/B3,10/C3,18/C3

757 044 11W

BC_CCLK2 LEGACYJ 205 47 ohms
3/C3,10/B3,13/B3,20/C4 LEGACY
OPT_BDJ 206 0 ohms
3/C1,4/C1,4/B3 C318 24/B3 OPT_BD
1 192 R48 22 SBE3J
10pF SBE3 9/B1,9/C1,13/C3,24/C3
LBUFDIR R127 22 98 193 R52 1 2 22 SBE2J
2/C3 LBUFDIR SBE2 9/B1,9/C1,13/C3,24/C3
2 LATCHLO R5131 2 22 99 194 R49 1 2 22 SBE1J
50V 2/C3 LATCHLO SBE1 9/B2,9/C2,13/C4,24/C3
LATCHHI R5141 2 22 100 195 R53 1 2 22 SBE0J
2/C3 LATCHHI SBE0 9/B2,9/C2,13/C4,24/C3
LBUFLOEJ R1261 2 22 101 150 R5171 2 22 SRAM1CSJ
2/C3 LBUFLOE SRAM1CS 4/C1,18/C4
LBUFHOEJ R1251 2 22 102 111 R5181 2 22 SRAM0CSJ
2/C3 LBUFHOE SRAM0CS 4/C1,18/C3
DSTEERJ R5151 2 22 108 113 1 2 AUX_AUDIO_CSJ
5/A3 DSTEER AUX_AUDIO_CS 20/A4,20/C4
1 2 114 DB9
DB9 4/C1
PADS_INT 110 115 DB10
2/A3 INT1_OUT DB10 4/C1
119 SRAM_BUFF_OEJ
SRAM_BUFF_OE 9/B4
OPTION OUTCSJ 178
10/B4,20/A4,20/C4 BC2SER0
BC2SER1 179
10/B4 BC2SER1
BC_CCLK NC1=7,13,38,44,55,56,60,97, 199 SER_RDYJ
RDY_IN1 5/B3,10/C3
YAM_RSTJ 188 NC2=112,118,143,149,165,202 200 OPTBD_RDYJ
C317 10/B4,20/A4,20/C4 BC2SER3 RDY_IN2 24/C3
3/C1,4/C1,4/B3 1 BC2GX0 189
10pF BC2BZ0
BC2GX1 191
BC2BZ1
2 BC2GX2 201 20 BC2OPT0
50V BC2BZ2 BC2OPT0
BC2GX3 203 24 BC2OPT1 BC2OPT[0:1]
BC2BZ3 BC2OPT1
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24 24/B3
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

80
GCK0 TP16
77
GCK1 TP17
1
11
19
25
32
40
51
64
72
79
85
93
103
116
124
131
137
145
158
169
177
183
190
198

XC2S50
FPGA
BC2GX[0:3]
6/C1

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 5 OF 24
4 3 2 1

3.3V

14
PWR
1
BADSJ 13 330 OHMS
2/A3,4/C1,4/B3,6/C4,24/C3
BRDJ 2
2/B3,4/C1,4/B3,5/C2,5/C1,5/A4,9/C3,9/B3,24/C3
DTRJ 12 R1 3.3V
24/C3
BLE0J 3 RP11
D BLE1J 11
C199
0.1UF
1
D
BLE[0:3]J BLE2J 4
BLE3J 10 2 5V 5V 3.3V
2/B3,4/B4,6/C4,24/A3 25V
BSA0 5 R2

BSA1 9 3.3V 1 1 1
BSA2 6 680 OHMS R248 R245 R247
BSA3 8 430 430 2.2K

GND

14
7
BSA[0:3] U60 2 2 2

VCC
2/C1,4/C4
2 3 WR5J
A0 OUT0 19/C3
SWR0J 1
4/C1,4/B2,5/B3,13/B3,20/C4,24/C3 OE0
5 6 RD5J
A1 OUT1 19/C3
SRDJ 4
4/C1,4/B2,5/A3,10/C3,13/B3,18/C4,20/C4,24/C3 OE1
RTC1_SRAM_OEJ 12 11 RTC1_SRAM_BOEJ
18/C3,19/C2 A2 OUT2 4/C2
SD[0:31] 13
OE2
SA[0:31] 9 8
2/D1,6/C4,9/D4,10/C4,13/D4,20/C4,24/D4 A3 OUT3

GND
10
2/C1,4/C2,4/C4,9/D3,10/C4,13/D4,20/C4 OE3
3.3V
3.3V

7
1
3.3V R244 R246
74LCX125A

14
1 2 150 3.3V 3.3V

PWR
SA31 1

14
SA30 13 330 OHMS 2.2K 2
C192 C140

PWR
1 SA29 2 3.3V 1 1
0.1UF 0.1UF
13 330 OHMS SA28 12 R1

2 2 2
C200 25V 25V
12 R1 SA27 3 RP13 1 3.3V
0.1UF
3.3V SA26 11
SD0 3 RP5 SA25 4 2
25V

14
SD1 11 SA24 10 U75
C341
4

VCC
SD2 1
0.1UF
SD3 10 SA23 5 R2 LHLDA 2 3 BHLDA
2/C4 A0 OUT0 2/A4,4/B3
2 SA22 9 1
25V OE0
SD4 5 R2 SA21 6 680 OHMS BRDJ 5 6 GX_CPU_RDJ
2/B3,4/C1,4/B3,5/D4,5/C1,5/A4,9/C3,9/B3,24/C3 A1 OUT1 6/C4
SD5 9 SA20 8 GX_HLDA 4
4/B3,6/C4 OE1

GND
SD6 6 680 OHMS 12 11 BRDJ
A2 OUT2 2/B3,4/C1,4/B3,5/D4,5/C2,5/A4,9/C3,9/B3,24/C3

7
SD7 8 GX_HLDAJ 13
4/B3 OE2

GND
9 8 PS_INT
A3 OUT3 2/A3

GND
7
3.3V V13_FAIL_INTJ 10
C 3.3V
17/C1 OE3
C
3.3V R211

7
1 1
ED'S WRITE PROTECT THING

14
1 2 1 R214 R212
74LCX125A

PWR
SA19 1 R213 2.2K 2.2K

PWR
SD8 1 SA18 13 330 OHMS 2.2K 150
SD9 13 330 OHMS SA17 2 3.3V 2 2
SD10 2 SA16 12 R1
2
SD11 12 R1
C197
3.3V SA15 3 RP12 1
0.1UF
SD12 3 RP6 SA14 11
SD13 11 SA13 4 2
C87 25V
SD14 4 1 SA12 10
0.1UF
SD15 10
2 SA11 5 R2
25V
SD16 5 R2 SA10 9
SD17 9 SA9 6 680 OHMS
SD18 6 680 OHMS SA8 8

GND
SD19 8 GND

7
7

3.3V
3.3V
14

14
PWR

SD20 1

PWR
SD21 13 330 OHMS SA7 1
SD22 2 SA6 13 330 OHMS
SD23 12 R1 SA5 2
3.3V SA4 12 R1 3.3V
SD24 3 RP7
SD25 11 SA3 3 RP10
C88 C164
SD26 4 1 SA2 11 1
0.1UF 0.1UF
SD27 10 SA1 4
2 SA0 10 2
25V 25V
SD28 5 R2

SD29 9 5 R2

SD30 6 680 OHMS 9

SD31 8 6 680 OHMS
GND

SER_RDYJ 8
4/A2,10/C3

GND
7

7
B B

DWG_NO
3.3V
R128
RDYJ 1 2
2/A3,4/C1,4/B3,6/C4
330

757 044 11W

3.3V 3.3V

3.3V
1 1
R14 R305
4.7K 330
50
35
22
7

U91 2 2
SD0 52 5 SD16
VCC4
VCC3
VCC2
VCC1

1B1 1A1
SD1 51 6 SD17 SWR0J
1B2 1A2 4/C1,4/B2,5/D2,13/B3,20/C4,24/C3
SD2 49 8 SD18
1B3 1A3
SD3 48 9 SD19 3.3V SWR1J
1B4 1A4 4/B2,10/C3,18/C3
SD4 47 10 SD20
1B5 1A5
SD5 45 12 SD21 1 1
1B6 1A6
SD6 44 13 SD22 R11 R388
1B7 1A7 C361 C396 C421 C342
SD7 43 14 SD23 1 1 1 1 4.7K 750
1B8 1A8 0.1UF 0.1UF 0.1UF 0.1UF
SD8 42 15 SD24 2 2 2 2 2 2
2B1 2A1 25V 25V 25V 25V
SD9 41 16 SD25 OPTION OPTION
2B2 2A2
SD10 40 17 SD26
2B3 2A3
SD11 38 19 SD27
2B4 2A4
SD12 37 20 SD28
2B5 2A5
SD13 36 21 SD29
2B6 2A6
SD14 34 23 SD30
2B7 2A7
SD15 33 24 SD31
2B8 2A8
BRDJ 1 56 SRDJ
2/B3,4/C1,4/B3,5/D4,5/C2,5/C1,9/C3,9/B3,24/C3 1DIR 1OE 4/C1,4/B2,5/D2,10/C3,13/B3,18/C4,20/C4,24/C3
28 29 DSTEERJ
2DIR 2OE 4/B3
A 3
1SAB 1CLKAB
2 1
A
26 27 R109
2SAB 2CLKAB
54 55 1K
1SBA 1CLKBA
31 30
2SBA 2CLKBA 2
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
GND8
GND7
GND6
GND5
GND4
GND3
GND2
GND1

1
R178
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
1 150 9295 PROTOTYPE DRIVE RENO NV 89521
R179 INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R
53
46
39
32
25
18
11
4

PI74LPT16646A 2
150
TRANSCEIVER INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE
2 COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 5 OF 24

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 5

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 6 OF 24
4 3 2 1
1.5V_GX 3.3V_AUX_BZ 3.3V

C263 C266 C280 C254 C286 C276 C287 C275 C259 C285 C227 C265 C224 C225 C226 C268 C271 C296 C295 C294 C50 C283 C354 C269 C277 C290 C274 C273 C256 C380 C357 C292 C382 C401
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01UF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 6.8uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 16V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V

1.5V_GX 3.3V_AUX_BZ 3.3V

C258 C255 C262 C272 C264 C281 C291 C293 C289 C278 C253 C284
1 1 1 1 1 1 1 1 1 1 1 1
C260 C261 C279 C288 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
1 1 1 1
0.01uF 0.01uF 0.01uF 0.01uF
2 2 2 2 2 2 2 2 2 2 2 2
10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V 10V

AB11
AA22
2 2 2 2
10V 10V 10V 10V

M22

M16
G16
G15

AA1

G11
G10

G14
G13
G12

G17
U17

R16

H16

H17

R17

N16

U16
U15
B22

A12

K16

P16
T16
T15

F17

F16
F15

T17

T14
T13
T12

T11
T10
L16

J16

M7
G8
G7

G6
U6

U8
U7

H6
B1

K7
T8
T7

F8
F7

T9
T6
L1

J7
U81

1VCCO_0
2VCCO_0
3VCCO_0
4VCCO_0
5VCCO_0
1VCCO_1
2VCCO_1
3VCCO_1
4VCCO_1
5VCCO_1
1VCCO_2
2VCCO_2
3VCCO_2
4VCCO_2
5VCCO_2
1VCCO_3
2VCCO_3
3VCCO_3
4VCCO_3
5VCCO_3
1VCCO_4
2VCCO_4
3VCCO_4
4VCCO_4
5VCCO_4
1VCCO_5
2VCCO_5
3VCCO_5
4VCCO_5
5VCCO_5
1VCCO_6
2VCCO_6
3VCCO_6
4VCCO_6
5VCCO_6
1VCCO_7
2VCCO_7
3VCCO_7
4VCCO_7
5VCCO_7
VCCINT1
VCCINT2
VCCINT3
VCCINT4
VCCINT5
VCCINT6
VCCINT7
VCCINT8
VCCINT9
VCCINT10
VCCINT11
VCCINT12
VCCINT13
VCCINT14
VCCINT15
VCCINT16

VCCAUX1
VCCAUX2
VCCAUX3
VCCAUX4
VCCAUX5
VCCAUX6
VCCAUX7
VCCAUX8
D D

LEGACY U11 W20 VID_R0

3/C3,13/B3,18/C4 LEGACY VID_R0
GX_48MHZ C11 AA20 VID_R1
3/C1,6/C4 SYSCLK48/GCK6S VID_R1
GX_CCLK Y18 AB19 VID_R2
3/C1,6/C4 BZ_CCLK VID_R2
RST3J W21 V19 VID_R3
4/B3,10/C3,13/B3,17/B1,18/D2,20/C4,21/C4,24/B3 SYS_RST VID_R3
OPTION AB18 VID_R4
VID_R4
SD0 D22 AB17 VID_R5
CPU_AD0 VID_R5
GX_PXLCLK SD1 E21 Y17 VID_R6 VID_R[0:7]
CPU_AD1 VID_R6
SD2 E20 W17 VID_R7
3/C1,6/C1 C222 CPU_AD2 VID_R7 8/C4
1 SD3 B19 Y22 VID_G0
10pF CPU_AD3 VID_G0
SD4 C21 V21 VID_G1
CPU_AD4 VID_G1
2 SD5 E19 V20 VID_G2
50V CPU_AD5 VID_G2
SD6 G21 AA18 VID_G3
CPU_AD6 VID_G3
SD7 C22 AA17 VID_G4
CPU_AD7 VID_G4
SD8 D21 V17 VID_G5
CPU_AD8 VID_G5
SD9 H22 W13 VID_G6 VID_G[0:7]
CPU_AD9 VID_G6
SD10 H20 V12 VID_G7
CPU_AD10 VID_G7 8/C4
SD11 H19 AA13 VID_B0
CPU_AD11 VID_B0
SD12 G22 Y13 VID_B1
CPU_AD12 VID_B1
OPTION SD13 H21 AA12 VID_B2
CPU_AD13 VID_B2
SD14 J18 AB12 VID_B3
CPU_AD14 VID_B3
GX_CCLK SD15 K22 W11 VID_B4
CPU_AD15 VID_B4
SD16 K21 AB10 VID_B5
3/C1,6/D4 C223 CPU_AD16 VID_B5
1 SD17 J17 Y10 VID_B6 VID_B[0:7]
10pF CPU_AD17 VID_B6
SD18 L22 W10 VID_B7
CPU_AD18 VID_B7 8/C4
2 SD19 L21
50V CPU_AD19
SD20 L20
CPU_AD20
SD21 L18 AB13 VID_BLANK
CPU_AD21 VID_BLANK 8/C4
SD22 M20 U12 VID_HSYNC
CPU_AD22 VID_HSYNC 8/C2
SD23 M19 V11 VID_VSYNC
CPU_AD23 VID_VSYNC 8/C2
SD24 N22
CPU_AD24
SD25 N21 W12 R191 47 VID_PCLK_OUT
CPU_AD25 VID_PCLK_OUT 8/C4

2
SD26 L19 Y11 GX_PXLCLK
CPU_AD26 VIDCLK/GCLK6P 3/C1,6/D4
OPTION SD27 M21 U13
CPU_AD27 VID_PCLK_IN TP18
SD28 M18
CPU_AD28
GX_48MHZ SD29 M17 A19 VID_MODE0
CPU_AD29 VID_MODE0 3/C4
SD[0:31] SD30 R21 E22 VID_MODE1
C152 CPU_AD30 VID_MODE1 3/C4
3/C1,6/D4 1 SD31 R19 F18 VID_MODE2
C 10pF
2/D1,5/D4,9/D4,10/C4,13/D4,20/C4,24/D4
CPU_AD31
XC2V500 VID_MODE2 3/C4
C
2 BLE0J P17 BC2GX[0:3]
50V CPU_BE0
BLE1J T21 F12 BC2GX0
CPU_BE1 BC2BZ0 4/A3
BLE[0:3]J BLE2J T22 V13 BC2GX1
CPU_BE2 BC2BZ1
BLE3J R18 AA11 BC2GX2
2/B3,4/B4,5/D4,24/A3
2/B3,2/B2,2/B2,4/C1,4/B3,24/C3
BALEJ Y12
CPU_BE3

ALE/GCLK3S
FPGA BC2BC2
BC2BZ3
BZDB1
V10
L17
BC2GX3
GXDB1
4/B1
GX_CPU_RDJ R22 N17 GXDB2
5/C1 CPU_RD BZDB2 4/B1
BADSJ V22 22 R190
2/A3,4/C1,4/B3,5/D4,24/C3 CPU_ADS
GX_HOLD R20 V7 CG_A0 2 1 22 XCG_A0
4/B3 CPU_HOLD CG_A0 13/C2
GX_HLDA W22 P6 CG_A1 2 1 XCG_A1
4/B3,5/C2 CPU_HLDA CG_A1 13/C2
RDYJ Y21 R3 GX2M0 R88
2/A3,4/C1,4/B3,5/B3 CPU_WAIT SPARE_C
P5 GX2M1
SPARE_D
SDRAM_BA[0:1] SDRAM_BA0 C10 W18 GX2M2 GX2M[0:3]
SDRAM_BA0 SPARE_E
SDRAM_BA1 C2 W6 GX2M3
7/B3 SDRAM_BA1 SPARE_F 13/D2
Y5 90NSJ
90NS 13/C3
SDRAM_A0 E8 W5 VSYNC2SER
SDRAM_A0 VSYNC2SER 10/C1
SDRAM_A1 B6 AA3 22 2 1 CG_DDIR CG_BK[0:15]
SDRAM_A1 CG_DDIR 13/C2
SDRAM_A2 C6 R519
SDRAM_A2 13/D1
SDRAM_A3 E6 N2 CG_BK0
SDRAM_A3 CG_BK0
SDRAM_A4 B5 M2 CG_BK1
SDRAM_A4 CG_BK1
SDRAM_A5 D6 M3 CG_BK2
SDRAM_A5 CG_BK2
SDRAM_A6 A6 M5 CG_BK3
SDRAM_A6 CG_BK3
SDRAM_A7 E7 L3 CG_BK4
SDRAM_A7 CG_BK4
SDRAM_A8 D10 NU1=AA9,AB9,Y9,W9,AB8,AA8,Y8,W8,AA15 K1 CG_BK5
SDRAM_A8 CG_BK5
SDRAM_A9 B11 K4 CG_BK6
SDRAM_A9 CG_BK6
SDRAM_A10 F10 NU2=AB15,U14,V14,W14,Y14,AA14,AB14,AB9 J6 CG_BK7
SDRAM__A10 CG_BK7
SDRAM_A[0:12] SDRAM_A11 E11 AA5 CG_BK8
SDRAM_A11 CG_BK8
SDRAM_A12 B10 NU3=P4,P3,P2,P1,N6,N5,N4,N3 Y1 CG_BK9
7/C3 SDRAM_A12 CG_BK9
W1 CG_BK10
CG_BK10
SDRAM_CS0J F11 NU4=L6,K6,K5,J5,J1,J2,J3,J4 V4 CG_BK11
7/C4 SDRAM_CSO CG_BK11
SDRAM_CS1J A10 V3 CG_BK12
7/C2 SDRAM_CS1 CG_BK12
SDRAM_RASJ D11 NU5=B8,A8,E9,F9,D9,C9,B9,A9 T1 CG_BK13
7/C2 SDRAM_RAS CG_BK13
SDRAM_CASJ B12 K2 CG_BK14
7/C2 SDRAM_CAS CG_BK14
SDRAM_WEJ E12 NU6=A14,B14,C14,D14,A15,B15,C15,D15 R2 CG_BK15
7/C2 SDRAM_WE CG_BK15
SDRAM_DQM0 D13 CG_BL[0:15]
7/C4 SDRAM_DQM0
SDRAM_DQM1 D12 NU7=J19,J20,J21,J22,K17,K18,K19,K20 Y2 CG_BL0
7/B4 SDRAM_DQM1 CG_BL0 13/C1
SDRAM_DQM2 C12 W2 CG_BL1
7/B4 SDRAM_DQM2 CG_BL1
SDRAM_DQM3 F13 NU8=N20,N19,N18,P18,P22,P21,P20,P19 U3 CG_BL2
7/B4 SDRAM_DQM3 CG_BL2
SDRAM_CKE E10 U4 CG_BL3
B 7/C2 SDRAM_CKE CG_BL3
CG_BL4
T2 CG_BL4 B
SDRAM_CLK96 A5 Y4 CG_BL5
7/A4 SDRAM_CLK CG_BL5
SDRAM_CLKFB A11 R4 CG_BL6
7/B4 FBCLK/GCLK4S CG_BL6

DWG_NO
SDRAM_DQ[0:31] R1 CG_BL7
CG_BL7
SDRAM_DQ0 A18 L5 CG_BL8
7/C3 SDRAM_DQ0 CG_BL8
SDRAM_DQ1 B17 L2 CG_BL9
SDRAM_DQ1 CG_BL9
SDRAM_DQ2 D17 M1 CG_BL10
SDRAM_DQ2 CG_BL10
SDRAM_DQ3 E17 M4 CG_BL11
SDRAM_DQ3 CG_BL11
SDRAM_DQ4 E16 N1 CG_BL12

757 044 11W

SDRAM_DQ4 CG_BL12
SDRAM_DQ5 E13 L4 CG_BL13
SDRAM_DQ5 CG_BL13
SDRAM_DQ6 A13 K3 CG_BL14
SDRAM_DQ6 CG_BL14
SDRAM_DQ7 B13 NC1=D7,C7,B7,A7,D8,C8 H1 CG_BL15
SDRAM_DQ7 CG_BL15
3.3V SDRAM_DQ8 C13
SDRAM_DQ8
SDRAM_DQ9 E14 NC2=F14,E15,A16,B16,C16,D16 22 R262
SDRAM_DQ9
R139 4.7K SDRAM_DQ10 A17 H3 CG_ALE 2 1 22 R38 XCG_ALE
SDRAM_DQ10 CG_ALE 13/C2
PROG_B 1 2 SDRAM_DQ11 C18 NC3=F19,F20,F21,F22,G18,H18,G19,G20 AB5 CG_D_LATCH 2 1 22 R80 XCG_D_LATCH
6/A2 SDRAM_DQ11 CG_D_LATCH 13/C2
SDRAM_DQ12 D18 AA4 CG_D_OEJ 22 R57 2 1 XCG_D_OEJ
SDRAM_DQ12 CG_D_OE 13/C2
R152 4.7K SDRAM_DQ13 E18 NC4=T20,T19,U22,U21,U20,U19,T18,U18 U10 CG_FLATCH1_OUT2 1 22 R34 XCG_FLATCH1_OUT
SDRAM_DQ13 CG_FLATCH1_OUT 13/C3
PWRDWN_B 1 2 SDRAM_DQ14 C17 V9 CG_FLATCH2 2 1 XCG_FLATCH2
6/A2 SDRAM_DQ14 CG_FLATCH2 13/C2
SDRAM_DQ15 B18 NC5=V16,V15,W16,Y16,AA16,AB16,W15,Y15 22 R42
SDRAM_DQ15
R138 4.7K SDRAM_DQ16 C1 M6 CG_RDJ 22 R82 2 1 XCG_RDJ
SDRAM_DQ16 CG_RD 13/C2
HSWAP_EN 1 2 SDRAM_DQ17 C5 NC6=U9,V8,AB7,AA7,Y7,W7,AB6,AA6 AB4 CG_FWR0BJ 2 1 22 R56 XCG_FWR0BJ
6/A2 SDRAM_DQ17 CG_FWR0B 13/C2
SDRAM_DQ18 E1 V5 CG_FLATCH1_IN 2 1 XCG_FLATCH1_IN
SDRAM_DQ18 CG_FLATCH1_IN 13/C2
R150 4.7K SDRAM_DQ19 E3 NC7=V2,V1,U2,U1,T5,R5,T4,T3 22 R33
SDRAM_DQ19
M2 1 2 SDRAM_DQ20 A4 U5 CG_BLKRWJ 22 R36 2 1 XCG_BLKRWJ
6/A3 SDRAM_DQ20 CG_BLKRW 13/B2
SDRAM_DQ21 C4 NC8=G3,G4,F1,F2,F3,F4,G5,F5 Y6 CG_VBLK0 2 1 22 R41 XCG_VBLK0
SDRAM_DQ21 CG_BCLK0 13/C2
R193 4.7K SDRAM_DQ22 E5 V6 CG_VBLK1 2 1 22 R84 XCG_VBLK1
SDRAM_DQ22 CG_VBLK1 13/C2
M1 1 2 SDRAM_DQ23 H4 AA10 CG_BLKRW_OR_VBLK1 2 1 XCG_BLKRW_OR_VBLK1
6/A3 SDRAM_DQ23 CG_BLKRW_OR_VBLK1 13/C2
SDRAM_DQ24 H5
SDRAM_DQ24
R151 4.7K SDRAM_DQ25 H2
SDRAM_DQ25
M0 1 2 SDRAM_DQ26 G1
6/A3 SDRAM_DQ26
SDRAM_DQ27 E4
SDRAM_DQ27
SDRAM_DQ28 G2 D1
SDRAM_DQ28 I/O195 TP19
SDRAM_DQ29 E2
SDRAM_DQ29
SDRAM_DQ30 D2
SDRAM_DQ30
PWRDWN_B

SDRAM_DQ31 B4
HSWAP_EN

SDRAM_DQ31
3.3V
PROG_B

GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26
GND27
GND28
GND29
GND30
GND31
GND32
GND33
GND34
GND35
GND36
GND37
GND38
GND39
GND40
GND41
GND42
GND43
GND44
GND45
GND46
GND47
GND48
GND49
GND50
GND51
GND52
VBATT
INIT_B

DONE

RSVD

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9
CCLK

3.3V
DXN

TDO
TMS
DXP

TCK
DIN

TDI

M0
M1
M2

A 1 1 1 1
A
R224 R223 R222 R228
18
19
20

AA19
Y19
V18
AB20
A2
B3
AB21
A20
A21
A3

B20

AB2

AB3

AB22
AB1
AA21
AA2
Y20
Y3

P14
P13
P12
P11
P10
P9

L14
L13
L12
L11
L10
L9
K14
K13
K12
K11
K10
K9

B21
B2
A22
A1
D5

C19
D3
D20

W19
W4

N14
N13
N12
N11
N10
N9
M14
M13
M12
M11
M10
M9

J14
J13
J12
J11
J10
J9
D19
D4
C20
C3
4.7K 4.7K 4.7K 4.7K U78
VCC
VCCO
VCCJ

2 2 2 2 2
DNC1
J16
DNC2
9 ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
5
TMS DNC3
12
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
4 14 M2 9295 PROTOTYPE DRIVE RENO NV 89521
TDI DNC4 6/A4
17
TDO DNC5
15 M1
6/A4
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

6 16 M0
3.3V
TCK DNC6 6/A4 INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE
JTAG_TMS
4/D3,10/C4
3.3V 3
8
CLK D0
1
7 3.3V
JTAG2_TDI
JTAG1_TDI
10/C4
COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
GND

OE/RST CF 4/D3
1
C332
10
CE CEO
13
1
JTAG_TCK
4/D3,10/C4
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
0.1uF
ICNAME R153
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
11

2 ICSUBTYPE 330 PWRDWN_B DWG_SIZE DWG_NO REV_LTR

25V 6/B4
HSWAP_EN INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
2 PROG_B
6/B4
6/B4 C 757 044 11W A
FPGA_DONE DRAWN DATE CHECKED DATE APPROVED DATE SCALE
4/C4,10/D4,17/C4
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 6 OF 24

4 3 2 1

6 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 7 OF 24
4 3 2 1

D 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V D

C449 C299 C300 C151 C34 C447 C326 C327 C126
1 1 1 1 1 1 1 1 1
0.01uF 0.01uF 0.01uF 1uF 6.8uF 0.01uF 0.01uF 0.01uF 1uF
2 2 2 2 2 2 2 2 2
50V 50V 50V 25V 16V 50V 50V 50V 25V

3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V 3.3V

C450 C302 C303 C301 C367 C446 C478 C305

1 1 1 1 1 1 1 1
0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
2 2 2 2 2 2 2 2
50V 50V 50V 50V 50V 50V 50V 50V

SDRAM_A[0:12]
6/B4

SDRAM_DQ[0:31]
6/B4

3.3V 3.3V

14
27

43
49

14
27

43
49
1

3
9

3
9
U79 U64

VDD1
VDD2
VDD3
VDDQ1
VDDQ2
VDDQ3
VDDQ4

VDD1
VDD2
VDD3
VDDQ1
VDDQ2
VDDQ3
VDDQ4
SDRAM_A0 23 2 SDRAM_DQ0 SDRAM_A0 23 2 SDRAM_DQ16
A0 D0 A0 D0
SDRAM_A1 24 4 SDRAM_DQ1 SDRAM_A1 24 4 SDRAM_DQ17
A1 D1 A1 D1
SDRAM_A2 25 5 SDRAM_DQ2 SDRAM_A2 25 5 SDRAM_DQ18
A2 D2 A2 D2
SDRAM_A3 26 7 SDRAM_DQ3 SDRAM_A3 26 7 SDRAM_DQ19
C SDRAM_A4 29
A3
A4
D3
D4
8 SDRAM_DQ4 SDRAM_A4 29
A3
A4
D3
D4
8 SDRAM_DQ20 C
SDRAM_A5 30 10 SDRAM_DQ5 SDRAM_A5 30 10 SDRAM_DQ21
A5 D5 A5 D5
SDRAM_A6 31 11 SDRAM_DQ6 SDRAM_A6 31 11 SDRAM_DQ22
A6 D6 A6 D6
SDRAM_A7 32 13 SDRAM_DQ7 SDRAM_A7 32 13 SDRAM_DQ23
A7 D7 A7 D7
SDRAM_A8 33 42 SDRAM_DQ8 SDRAM_A8 33 42 SDRAM_DQ24
A8 D8 A8 D8
SDRAM_A9 34 44 SDRAM_DQ9 SDRAM_A9 34 44 SDRAM_DQ25
A9 D9 A9 D9
SDRAM_A10 22 45 SDRAM_DQ10 SDRAM_A10 22 45 SDRAM_DQ26
A10 D10 A10 D10
SDRAM_A11 35 47 SDRAM_DQ11 SDRAM_A11 35 47 SDRAM_DQ27
A11 D11 A11 D11
SDRAM_A12 36 48 SDRAM_DQ12 SDRAM_A12 36 48 SDRAM_DQ28
A12 D12 A12 D12
50 SDRAM_DQ13 50 SDRAM_DQ29
D13 D13
SDRAM_BA0 20 51 SDRAM_DQ14 SDRAM_BA0 20 51 SDRAM_DQ30
BA0 D14 BA0 D14
SDRAM_BA1 21 53 SDRAM_DQ15 SDRAM_BA1 21 53 SDRAM_DQ31
BA1 D15 BA1 D15
SDRAM0_CLK96 38 SDRAM1_CLK96 38
7/A3 CLK CLK
SDRAM_CKE 37 40 SDRAM_CKE 37 40
6/B4 CKE NC CKE NC
SDRAM_WEJ 16 SDRAM_WEJ 16
6/B4 WE WE
SDRAM_CS0J 19 SDRAM_CS1J 19
6/B4 CS# CS#
SDRAM_CASJ 17 SDRAM_CASJ 17
6/B4 CAS# CAS#
SDRAM_RASJ 18 SDRAM_RASJ 18
6/B4 RAS# RAS#

VSSQ1
VSSQ2
VSSQ3
VSSQ4

VSSQ1
VSSQ2
VSSQ3
VSSQ4
15 15

VSS1
VSS2
VSS3

VSS1
VSS2
VSS3
SDRAM_DQM0 SDRAM_DQ2
6/B4 DQML DQML
SDRAM_DQM1 39 SDRAM_DQ3 39
6/B4 DQMH DQMH
MT48LC16M16A2 MT48LC16M16A2

28
41
54
6
12
46
52

28
41
54
6
12
46
52
DRAM DRAM
16MX16 16MX16

SDRAM_DQM3
6/B4
SDRAM_DQM2
6/B4

SDRAM_CS1J
6/B4

SDRAM1_CLK96
7/A3
SDRAM_BA[0:1]

B 6/C4 B

DWG_NO
757 044 11W
R140
SDRAM_CLKFB 2 1
6/B4
47

PI6CV304
4
VDD GND

OE Y3
R143 2 8 R142
Y2
SDRAM_CLK96 2 1 7 2 1 R137 SDRAM0_CLK96
6/B4 CLK_IN Y1 7/C4
1 5 2 1 SDRAM1_CLK96
Y0 7/C2
47 3 47
U80 47
6

1 1
R230 R229
2.2K 2.2K

3.3V 2 2

R141
1 2

A 5.1
C297 C298 A
1 1
0.1uF 0.01uF
2 2
25V 50V
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 7

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 8 OF 24
4 3 2 1

D D

OPTION

3.3V 5V
DACPWR
L10 50 OHMS L11 50 OHMS
1 2 1 2
C160 C201 C163 C170 C171 C172 C185 C169
1 1 1 1 1 1 1 1 DACPWR DACPWR DACPWR
6.8uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 6.8uF
2 2 2 2 2 2 2 2 V1_B
16V 25V 25V 25V 25V 25V 25V 16V 14/A1
3 3 3
CR32 CR27 CR30 V1_R
14/A1
1N914 1N914 1N914
V1_G
14/A1
VID_R[0:7]
1 1 1 L12 50 OHMS
6/D1

17
34
35
36
U97 V1BLUE 1 2 L14 50 OHMS
43 39 1 2 L13 50 OHMS

VDD1
VDD2
VDD3
VDD4
VID_R0 V1RED
R0 IOR
VID_R1 44 38 V1GRN 1 2
R1 IOG
VID_R2 1 37
R2 IOS
VID_G[0:7] VID_R3 2 33 1 3 1 3 1 3
R3 IOB
VID_R4 3 DACPWR R159 CR31 R156 CR28 R157 CR29
6/C1 R4 C173 C175 C174
VID_R5 4 40 C214 1 75 1N914 75 1N914 75 1N914 1 1 1
R5 COMP 10pF 10pF 10pF
VID_R6 5 1 2 R158
R6 2 2 2
VID_R7 6 41 150 2 2 2
R7 VREF 1 1 1 50V 50V 50V
0.1uF 1
VID_B[0:7] VID_G0 7 42 R181 2
G0 RREF
VID_G1 8 25V 3.3K
6/C1 G1
VID_G2 9
G2 2
VID_G3 10
C VID_G4 11
G3
G4 C
VID_G5 12
G5
VID_G6 13 2 LT1004CLP
G6
VID_G7 14 1
G7 C215 U98
R182 1
0.1uF 1.2V
VID_B0 18 2.2K 5V
B0 20A
VID_B1 19 2
B1 2 25V
VID_B2 20 3 OPTION
B2 C161
VID_B3 21 1
B3 0.1uF
VID_B4 22
B4
VID_B5 23 2
B5 25V
VID_B6 24
B6
VID_B7 25
B7
5V
VID_PCLK_OUT 27
6/C1 CLK
16
SYNC

14
VID_BLANK 15 U94
6/C1 BLANK
26

VCC
WHITE
28 VID_HSYNC 1 3 V1_HSYNC

GND1
GND2
GND3
GND4
SLEEP 6/C1 A0 OUT0 14/A1
2
B0
VID_VSYNC 4 6 V1_VSYNC
6/C1 A1 OUT1 14/B1
5

29
30
31
32
1 1 1
TMC3533R2C80 B1
R154 R183 R155 13 11
D/A CONVERTER A2 OUT2
150 150 150 12
B2
10 8
A3 OUT3

GND
2 2 2 9
B3
74ACT32

7
1 1
R188 R189 OR
10K 2.2K 1
3.3V R192
2 2 150
2

B B

DWG_NO
757 044 11W
A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11 A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 8 OF 24

4 3 2 1

8 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 9 OF 24
4 3 2 1

SRAM3V
L15
VOUT3 1 2
13/B3,16/B1,16/B3,17/C1,19/A3
50 OHMS

C370 C336 C334 C373 C375 C335 C337 C374 C372

1 1 1 1 1 1 1 1 1
1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
2 2 2 2 2 2 2 2 2
25V 10V 10V 10V 10V 10V 10V 10V 10V

D D
SRAMD[0:31]

SA[0:31]
2/C1,4/C2,4/C4,5/D3,10/C4,13/D4,20/C4
SRAM3V SRAM3V

SD[0:31] SA[21] SA[21]

D6
E1

E1
3.3V U43 U44
2/D1,5/D4,6/C4,10/C4,13/D4,20/C4,24/D4
SA2 A3 B6 SRAMD0 SA2 A3 B6 SRAMD16

VDD1
VDD2

VDD1
VDD2
A0 D1 A0 D1
SA3 A4 C5 SRAMD1 SA3 A4 C5 SRAMD17
A1 D2 A1 D2
SA4 A5 C6 SRAMD2 SA4 A5 C6 SRAMD18
A2 D3 A2 D3
SA5 B3 D5 SRAMD3 SA5 B3 D5 SRAMD19
A3 D4 A3 D4
SA6 B4 E5 SRAMD4 SA6 B4 E5 SRAMD20

22
35
50
A4 D5 A4 D5

7
U45 SA7 C3 F5 SRAMD5 SA7 C3 F5 SRAMD21
A5 D6 A5 D6
SD15 5 52 SRAMD15 SA8 C4 F6 SRAMD6 SA8 C4 F6 SRAMD22

VCC1
VCC2
VCC3
VCC4
1A1 1B1 A6 D7 A6 D7
SD14 6 51 SRAMD14 SA9 D4 G6 SRAMD7 SA9 D4 G6 SRAMD23
1A2 1B2 A7 D8 A7 D8
SD13 8 49 SRAMD13 SA10 H2 B1 SRAMD8 SA10 H2 B1 SRAMD24
1A3 1B3 A8 D9 A8 D9
SD12 9 48 SRAMD12 SA11 H3 C1 SRAMD9 SA11 H3 C1 SRAMD25
1A4 1B4 A9 D10 A9 D10
SD11 10 47 SRAMD11 SA12 H4 C2 SRAMD10 SA12 H4 C2 SRAMD26
1A5 1B5 A10 D11 A10 D11
SD10 12 45 SRAMD10 SA13 H5 D2 SRAMD11 SA13 H5 D2 SRAMD27
1A6 1B6 A11 D12 A11 D12
SD9 13 44 SRAMD9 3.3V SA14 G3 E2 SRAMD12 SA14 G3 E2 SRAMD28
1A7 1B7 A12 D13 A12 D13
SD8 14 43 SRAMD8 SA15 G4 F2 SRAMD13 SA15 G4 F2 SRAMD29
1A8 1B8 A13 D14 A13 D14
SA16 F3 F1 SRAMD14 SA16 F3 F1 SRAMD30
A14 D15 A14 D15
SD7 15 42 SRAMD7 SA17 F4 G1 SRAMD15 SA17 F4 G1 SRAMD31
2A1 2B1 C213 C247 C206 C207 A15 D16 A15 D16
SD6 16 41 SRAMD6 1 1 1 1 SA18 E4 SA18 E4
2A2 2B2 0.1uF 0.1uF 0.1uF 0.1uF A16 A16
SD5 17 40 SRAMD5 SA19 D3 SA19 D3
2A3 2B3 A17 A17
SD4 19 38 SRAMD4 2 2 2 2 SA20 H1 SA20 H1
2A4 2B4 25V 25V 25V 25V A18 A18
SD3 20 37 SRAMD3
2A5 2B5
SD2 21 36 SRAMD2 SRAM0CEJ B5 SRAM0CEJ B5
2A6 2B6 9/C1,18/D2 CE1 9/C2,18/D2 CE1
SD1 23 34 SRAMD1 SRAM0CE A6 SRAM0CE A6
2A7 2B7 9/C1,18/D2 CE2 9/C2,18/D2 CE2
SD0 24 33 SRAMD0 SRAMOEJ A2 SRAMOEJ A2
2A8 2B8 9/B2,9/B1,9/C1,18/C2 OE 9/B2,9/B1,9/C2,18/C2 OE
SRAMWRJ G5 E3 SRAMWRJ G5 E3
9/B2,9/B1,9/C1,18/C2 R/W OP 9/B2,9/B1,9/C2,18/C2 R/W OP
56 1 BRDJ G2 1 G2
1OE 1DIR 2/B3,4/C1,4/B3,5/D4,5/C2,5/C1,5/A4,9/B3,24/C3 NC1 NC1
29 28 SBE0J A1 H6 R28 SBE2J A1 H6 1
2OE 2DIR 4/B2,9/B2,13/C4,24/C3 LB NC2 4/B2,9/B1,13/C3,24/C3 LB NC2

GND1
GND2

GND1
GND2
SBE1J B2 150 SBE3J B2 R26
4/B2,9/B2,13/C4,24/C3 UB 4/B2,9/B1,13/C3,24/C3 UB
2 3 150
C 27
1CLKAB
2CLKAB
1SAB
2SAB
26 2
C
55 54 1 2

E6
D1

D1
1CLKBA 1SBA TC55VEM316 TC55VEM316
30 31 R290
2CLKBA 2SBA SRAM SRAM
3.3K

GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
1 1
R285 R286 2
150 150

4
11
18
25
32
39
46
53
2 PI74LPT16646A 2
TRANSCEIVER
FOR STANDBY MODE

3.3V

22
35
50
7 U46
SD31 5 52 SRAMD31
VCC1
VCC2
VCC3
VCC4
1A1 1B1
SD30 6 51 SRAMD30 3.3V
1A2 1B2
SD29 8 49 SRAMD29
1A3 1B3
SD28 9 48 SRAMD28
1A4 1B4
SD27 10 47 SRAMD27
1A5 1B5 C78 C82 C211 C246
SD26 12 45 SRAMD26 1 1 1 1 SRAM3V SRAM3V
1A6 1B6 0.1uF 0.1uF 0.1uF 0.1uF
SD25 13 44 SRAMD25
1A7 1B7
SD24 14 43 SRAMD24 2 2 2 2
1A8 1B8 25V 25V 25V 25V
SA[21] SA[21]

D6
E1

E1
SD23 15 42 SRAMD23 U20 U21
2A1 2B1
SD22 16 41 SRAMD22 SA2 A3 B6 SRAMD0 SA2 A3 B6 SRAMD16

VDD1
VDD2

VDD1
VDD2
2A2 2B2 A0 D1 A0 D1
SD21 17 40 SRAMD21 SA3 A4 C5 SRAMD1 SA3 A4 C5 SRAMD17
2A3 2B3 A1 D2 A1 D2
SD20 19 38 SRAMD20 SA4 A5 C6 SRAMD2 SA4 A5 C6 SRAMD18
2A4 2B4 A2 D3 A2 D3
SD19 20 37 SRAMD19 SA5 B3 D5 SRAMD3 SA5 B3 D5 SRAMD19
2A5 2B5 A3 D4 A3 D4
SD18 21 36 SRAMD18 SA6 B4 E5 SRAMD4 SA6 B4 E5 SRAMD20
2A6 2B6 A4 D5 A4 D5
SD17 23 34 SRAMD17 SA7 C3 F5 SRAMD5 SA7 C3 F5 SRAMD21
2A7 2B7 A5 D6 A5 D6
SD16 24 33 SRAMD16 SA8 C4 F6 SRAMD6 SA8 C4 F6 SRAMD22
2A8 2B8 A6 D7 A6 D7
SA9 D4 G6 SRAMD7 SA9 D4 G6 SRAMD23
A7 D8 A7 D8
SRAM_BUFF_OEJ 56 1 BRDJ SA10 H2 B1 SRAMD8 SA10 H2 B1 SRAMD24
4/B2 1OE 1DIR 2/B3,4/C1,4/B3,5/D4,5/C2,5/C1,5/A4,9/C3,24/C3 A8 D9 A8 D9
29 28 SA11 H3 C1 SRAMD9 SA11 H3 C1 SRAMD25
2OE 2DIR A9 D10 A9 D10
SA12 H4 C2 SRAMD10 SA12 H4 C2 SRAMD26
A10 D11 A10 D11
2 3 SA13 H5 D2 SRAMD11 SA13 H5 D2 SRAMD27
B 27
1CLKAB
2CLKAB
1SAB
2SAB
26 SA14 G3
A11
A12
D12
D13
E2 SRAMD12 SA14 G3
A11
A12
D12
D13
E2 SRAMD28 B
55 54 SA15 G4 F2 SRAMD13 SA15 G4 F2 SRAMD29
1CLKBA 1SBA A13 D14 A13 D14
30 31 SA16 F3 F1 SRAMD14 SA16 F3 F1 SRAMD30
2CLKBA 2SBA A14 D15 A14 D15

DWG_NO
SA17 F4 G1 SRAMD15 SA17 F4 G1 SRAMD31
A15 D16 A15 D16
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8

1 SA18 E4 SA18 E4
A16 A16
1 R283 SA19 D3 SA19 D3
A17 A17
R29 150 SA20 H1 SA20 H1
A18 A18
150
4
11
18
25
32
39
46
53

PI74LPT16646A 2 SRAM1CEJ B5 SRAM1CEJ B5

757 044 11W

2 TRANSCEIVER 9/B1,18/C2 CE1 9/B2,18/C2 CE1
SRAM1CE A6 SRAM1CE A6
9/B1,18/D2 CE2 9/B2,18/D2 CE2
SRAMOEJ A2 SRAMOEJ A2
9/B1,9/C1,9/C2,18/C2 OE 9/B2,9/C1,9/C2,18/C2 OE
SRAMWRJ G5 E3 SRAMWRJ G5 E3
9/B1,9/C1,9/C2,18/C2 R/W OP 9/B2,9/C1,9/C2,18/C2 R/W OP
G2 1 G2
NC1 NC1
SBE0J A1 H6 R13 SBE2J A1 H6 1
4/B2,9/C2,13/C4,24/C3 LB NC2 4/B2,9/C1,13/C3,24/C3 LB NC2

GND1
GND2

GND1
GND2
SBE1J B2 150 SBE3J B2 R12
4/B2,9/C2,13/C4,24/C3 UB 4/B2,9/C1,13/C3,24/C3 UB
150
2
1 2

E6
D1

D1
TC55VEM316 TC55VEM316
R363
SRAM SRAM
3.3K
2

FOR STANDBY MODE

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 9

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 10 OF 24
4 3 2 1

2.5V_SER

C418 C95 C99 C53 C412 C420 C83 C417 C89 C91 C90 C96
1 1 1 1 1 1 1 1 1 1 1 1
0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2 2 2 2 2 2 2 2 2 2 2 2
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V

3.3V 2.5V_SER 3.3V

FPGA_DONE
4/C4,6/A4,17/C4

D 3.3V 1
C208
0.1uF
1
C209
0.1uF
1
C210
1
0.1uF
C212
0.1uF
1
C97
0.1uF
1
C105
0.1uF
1
C134
0.1uF
1
C135
0.1uF
1
C121
0.1uF
1
C100
0.1uF
1
C101
0.1uF
1
C98
0.1uF
1
C61
0.1uF
1
C57
1
0.1uF
C60
0.1uF
1
C340
0.1uF
1
C85
D
REF_U83

105
117
130
144
156
170
184
197
208

118
128
143
171
186
196
6.8uF

12
26
39
53
65
78
92

13
28
38
66
76
91
U48 3.3V 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 25V 16V
1
R232
2.2K 8
DIP R16 4.7K
2 1 2 1 1 1 1 1 1 1 1
55 R320 R316 R313 R301 R300 R298 R297 R30
3.3V R17 4.7K 56 10K 10K 10K 10K 10K 10K 10K 10K
3.3V 1 2 3.3V
52 2 2 2 2 2 2 2 2
C76
1 R389 4.7K 50
0.1uF XC17S150
1 2 54 133 BAT_LO_OUT 1
18/C2

8
7
2 U83 134 SRAM_BAT_LO R165
25V 16/B2
161 135 10K

VCC2
VCC1
CCOPENJ
TP11 18/C2
R233 1 106 136 BVOPENJ
DATA 18/C2 2
1 2 6 2 160 138 Q2RXDD
NC CLK TP12 11/B4
4 139 Q2TXDD S1
CE 12/A4

GND
0 3 107 3
OE/RST
OPTION 104 140 Q2IO3C 1
153 141 Q2IO2C 2

5
11/C4
155 142 DDOPENJ
18/C2
154 146 MDOPENJ
TP10 18/C2 SPDT
JTAG_TDO 147 Q2RXDC
4/D3 11/B4 400mA
JTAG2_TDI 157 148 Q2TXDC
6/A2 12/A4
JTAG_TCK 159 3.3V
4/D3,6/A2
JTAG_TMS 207 149 Q2IO3B
4/D3,6/A2 14/A4
2 150 Q2IO2B
14/A4
SD[0:31] 152 VSYNC2SER 1
6/C2
151 Q2IO0B R312
2/D1,5/D4,6/C4,9/D4,13/D4,20/C4,24/D4 11/C2
SD0 3 162 Q2RXDB 10K
11/C4
SD1 4 163 Q2TXDB
12/B4 2
SD2 5
OPTION SD3 6 164
SD4 7 165 Q_IO_RSTJ
12/A4
SER_CCLK2 SD5 8 166 INTERROGATE 3.3V
18/C4
SA[0:31] SD6 9 167 TT_DISABLEJ
3/C1,10/B3 C414 18/C4
1 SD7 10 168 Q2RXDA 1
10pF 2/C1,4/C2,4/C4,5/D3,9/D3,13/D4,20/C4 11/B4
172 Q2TXDA R294
12/A4
SA1 14 10K
C 2
50V
SA2 15 173 Q1IO3D
11/A4 C
SA3 16 174 Q1IO2D 2
11/A4
SA4 17 175 PWR_SAVE
14/B2
SA5 18 176 TTDETJ
18/C1
SA6 20 178 Q1RXDD
14/C4
SA7 21 179 Q1TXDD
14/C4
SA8 22
OPTION SA9 23 180 Q1IO3C TP9
SA10 24 181 Q1IO2C
12/B4
SER_CCLK SA11 27 187 Q1IO1C TP8
SA16 29 188 Q1IO0C
3/C1,10/B3 C93 11/D2
1 SA17 30 189 Q1RXDC
10pF 11/D4
SA18 31 191 Q1TXDC
12/B4
2 SA19 33
50V
192 TT_CTL2
18/C4
34 193 TT_CTL1 3.3V
TP6 18/C4
SRDJ 35 194 Q1IO1B
4/C1,4/B2,5/D2,5/A3,13/B3,18/C4,20/C4,24/C3 TP7
SWR1J 36 195 Q1IO0B
4/B2,5/B3,18/C3 11/D2
199 Q1RXDB 1
11/D4
RST3J 41 200 Q1TXDB R292
4/B3,6/D4,13/B3,17/B1,18/D2,20/C4,21/C4,24/B3 12/C4
SER_RDYJ 42 10K
4/A2,5/B3
OPTION 201 Q1IO3A
12/B4 2
IRQQ2J 43 202 Q1IO2A J18
2/A3 12/B4
SER_29MHZ IRQQ1J 44 203 Q1IO1A
2/A3 1
204 Q1IO0A
3/C1,10/B3 C413 11/D2 2
1 SER_29MHZ 77 205 Q1RXDA
10pF 3/C1,10/B4 11/D4
SER_CCLK2 80 206 Q1TXDA
3/C1,10/C4 12/C4
2 SER_CCLK 182
50V 3/C1,10/C4
185

1 LEGACYJ 84 127 S1_CH1_DO

3/C3,4/B3,13/B3,20/C4 12/D4
R31 126 S1_CH1_DI
11/C4
150 Q1CSJ 62 125 S1_CH2_DO
4/B2 12/D4
Q2CSJ 63 123 S1_ADR
2 4/B2 12/D4
SENET1CSJ 67 122 S1_CLK
4/B2 12/D4
SENET2CSJ 68 121 S1_STB S1_RST
4/B2 12/D4 10/B2,12/C4
69 120 S1_RST
TP1 10/B2,12/C4
TP2
70 119 S1_CLK_256 TP5

4/B2,20/A4,20/C4
VOLCTLCSJ 71 I2C ADDRESS OPTION
SERFPGACSJ 73 1
B 4/C1,4/B2
TP3
74 97 S2_CH1_DO
12/C4
R415 B
98 S2_CH1_DI 2.2K
11/C4
99 S2_CH2_DO 3.3V
12/C4

DWG_NO
OUTCSJ 83 100 S2_ADR 2 R407
4/B3,20/A4,20/C4 12/C4
BC2SER1 86 101 S2_CLK PA0 2 1
4/B3 12/B4 10/B2
RTC2_CSJ 87 102 S2_STB
4/C2 12/C4
YAM_RSTJ 88 110 S2_CH2_DI 2.2K
4/A3,20/A4,20/C4 11/C4
SERDB1 89 R408
SERDB2 90 PA1 2 1

757 044 11W

10/B2
SERDB3 94 47 LED1
14/B4
SERDB4 95 48 LED2 2.2K
14/B4
SERDB5 96 49 LED3 3.3V 3.3V 3.3V R433
14/B4
SERDB[1:6] SERDB6 111 57 LED4 PA2 2 1
14/B4 10/B2
4/B1
112 58 MEM_SSN_OUT 1 U25 1 3.3V 2.2K

8
TP4 13/C2
59 R419 1 R161

VCC
SERMB[1:4] MEM_SSN_IN PA0
13/C2 10/B1 A0
2.2K PA1 2 2.2K R162
14/A2 10/B1 A1 C306
SERMB1 45 115 I2C1_DATA PA2 3 1 JA0 1 2
14/C2 2 10/B1 A2 2 0.1uF 10/A2
SERMB2 60 114 I2C1_CLK 7
14/C2 WP

GND
SERMB3 61 108 6 5 2 2.2K
SCL SDA 25V
SERMB4 132 109 R163

4
JA1 1 2
24FC256 10/A2
EEPROM
PWR_GOOD 37 2.2K
14/A4,17/C2,18/A2 32KX8
1 1
RAA24 129 R417 R117 I2C2_DATA R164
19/B3
RAA25 113 2.2K 2.2K 3.3V 3.3V JA2 1 2
10/A2
RAA26 46
RAA[24:26] 75 VOL_CLK 2 2 2.2K
20/B3

8
81 VOL_LOAD 3.3V 1 U86 3.3V OPTION
20/A2 20/B3
82 VOL_DATA R160 JA0 1

VCC
20/B3 10/B1 A0 REF_U86
2.2K JA1 2
10/B1 A1 C102
JA2 3 1
2 10/A1 A2 0.1uF
6 5 2
SCL SDA 25V
XC2S150 7 8
1
11
19
25
32
40
51
64
72
79
85
93
103
116
124
131
137
145
158
169
177
183
190
198

VSS
FPGA DIP
OPTION

4
EEPROM
A SERIAL DATA A
I2C2_CLK
19/B3

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

10 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 11 OF 24

4 3 2 1

3.3V 3.3V
13V 13V
1 1
R302 13V 1 R296 13V 1
750 R337 750 R333
U51 4.7K U54 4.7K
2 3 4 2 3 4
Q1RXDA 2 R338 2 Q1IO0A 2 R334 2
10/B1 LM339 10/B1 LM339
5 1 2 485_RXD 5 1 2 485_DCD
14/B2 14/B2
12 12
3.3V 576 3.3V 576
3 1 13V 3 1 13V
1 CR22 1 CR24
R303 13V BAT54 1 R304 13V BAT54 1
750 R434 750 R335
U51 4.7K U54 4.7K
D 2 3 6 2 3 6 D
Q1RXDB 1 R435 2 Q1IO0B 1 R336 2
10/C1 LM339 10/C1 LM339
7 1 2 UT_RXD 7 1 2 AC_SIN_IN
14/B2 14/B2
12 12
3.3V 576 3.3V 576
3 1 13V 3 1 13V
1 CR19 1 CR21
R324 13V BAT54 1 R299 13V BAT54 1
750 R327 750 R329
U51 4.7K U54 4.7K
2 3 8 2 3 8
Q1RXDC 14 R328 2 Q1IO0C 14 R330 2
10/C1 LM339 10/C1 LM339
9 1 2 COMM_RXD 9 1 2 COMM_CTS
14/B2 14/B2
12 12
3.3V 576 3.3V 576
3 1 13V 3 1 13V
1 CR25 1 CR26
R314 13V BAT54 1 R315 13V BAT54 1
750 R436 750 R331
U51 4.7K U54 4.7K
2 3 10 2 3 10
Q2RXDB 13 R437 2 Q2IO0B 13 R332 2
10/C1 LM339 10/C1 LM339
11 1 2 SP_FO_RXD 11 1 2 LP_SW
14/B2 14/B2
12 12
3.3V 576 576
3 1 13V 13V 13V 3 1
1 CR20 CR23
R322 13V BAT54 1 1 1 BAT54
750 R442 R504 R505
U36 1.8K 1.8K 1.8K
2 3 4
S1_CH1_DI 2 R443 2 2 2
10/B2 LM339
5 1 2 SEN1_CH1_DI
14/C2
12 4V_REF
11/B2,11/B4
3.3V 576
3 1 13V 13V 13V
1 CR16
R421 13V BAT54 1 1 1
750 R440 R506 R507
U36 1.8K 1.8K 1.8K
2 3 6 13V 13V 13V 13V
C 10/B2
S2_CH1_DI 1
LM339
R441 2 2 2
C
7 1 2 SEN2_CH1_DI
14/C2 C350 C438 C346 C348
12 1 1 1 1
0.1uF 0.1uF 0.1uF 0.1uF
3.3V 576
3 1 13V 13V 13V 2 2 2 2
25V 25V 25V 25V
1 CR17
R418 13V BAT54 1 1 1
750 R438 R508 R509
U36 1.8K 1.8K 1.8K
2 3 8
S2_CH2_DI 14 R439 2 2 2
10/B2 LM339
9 1 2 SEN2_CH2_DI
14/C2
12
3.3V 576
3 1 13V
1 CR18
R420 13V BAT54 1
750 R444 13V
U36 4.7K 13V
2 3 10
Q2IO2C 13 R445 2 13V
10/C1 LM339
11 1 2 JKPT_RST 1 1
14/C2
12 R325 R311
U59 U59
576 24.3K 10K

8
3 1 6 2
CR15 2 7 4V_REF 2 1
LM358 11/B4,11/C2 LM358
BAT54 5 3
C351
1
0.1uF

4
4V_REF 1 OPAMP
11/B2,11/C2
1 2 R310
C108 25V
1 R326 10K
6.8uF
11K
2 2
16V 2

3.3V

C250
1
B 0.1uF B
2
25V

DWG_NO
3.3V

U30 14
VCC

757 044 11W

Q2RXDC 3 2 PROG_RXD
10/C1 OUT0 A0 14/C2
1
OE0
Q2RXDD 6 5 DCS_RXD
10/D1 OUT1 A1 14/B2
4
OE1
Q2RXDA 11 12 NETPLEX_RXD
10/C1 OUT2 A2 14/B2
13
OE2
8 9
OUT3 A3
GND

10
OE3
7

1
U29 R430
74LCX125A
3 150
NC
1 2
GND1 DATA 2
4
GND2
3.3V
DS2401Z
ROM
1
R428
4.7K

Q1IO3D 2
10/C1

Q1IO2D
10/C1

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 11

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 12 OF 24
4 3 2 1

13V
RP3
3.3V 5V 13V 13V 4.7K
C347
1
0.1uF
RP1

10
5
1
2
3
4
6
7
8
9
C137 C69
1 1 4.7K U32

6
2
0.1uF 0.1uF 25V
3.3V 5V 1 8

VS
NC1 NC2

10
5
1
2
3
4
6
7
8
9
2 2
25V 25V
2 7 SEN1_CH1_DO
INA OUTA 14/C2

GND
U34 4 5 SEN1_CH2_DO
INB OUTB 14/C2
13V

VCC
2 3

3
D 10/B2
S1_CH1_DO 1
A0
OE0
OUT0
13V
MIC4426
C345 D
5 6 1
A1 OUT1 0.1uF
S1_CH2_DO 4
10/B2 OE1
12 11 U31

6
2
A2 OUT2 25V
13 1 8

VS
S1_ADR
10/B2 OE2 NC1 NC2
9 8
A3 OUT3

GND
S1_STB 10 2 7 SEN1_ADR
10/B2 OE3 INA OUTA 14/C2

GND
3.3V 4 5 SEN1_STB
INB OUTB 14/C2
13V

3
74LCX125A C139 MIC4426
1 13V
0.1uF C343
3.3V 1
0.1uF
2
25V
U28

6
2
25V

14
U37 1 8

VS
NC1 NC2

VCC
2 3 2 7 SEN1_CLK
A0 OUT0 INA OUTA 14/C2

GND
S1_CLK 1 4 5 SEN_RST
10/B2 OE0 INB OUTB 14/C2,14/C2
5 6 13V
A1 OUT1
4

3
S1_RST
10/B2,10/B2 OE1 MIC4426
12 11 13V
A2 OUT2 C349
Q1TXDA 13 1
10/B1 OE2 0.1uF
9 8
A3 OUT3

GND
Q1TXDB 10 U35

6
2
10/C1 OE3 25V
1 8

VS
NC1 NC2

7
1
R429 2 7 485_TXD
74LCX125A INA OUTA 14/B2

GND
150 4 5 UT_TXD
INB OUTB 14/B2
2

3
MIC4426

13V
RP4
3.3V 5V 13V 13V 4.7K
C442
1
0.1uF
RP2

10
5
1
2
3
4
6
7
8
9
C58 C62
1 1 4.7K U55

6
C 0.1uF
3.3V
0.1uF
5V 1 8
25V
2
C

VS
NC1 NC2

10
5
1
2
3
4
6
7
8
9
2 2
25V 25V
2 7 SEN2_CH1_DO
INA OUTA 14/C2

GND
U53 4 5 SEN2_CH2_DO
INB OUTB 14/C2
13V

VCC
2 3

3
A0 OUT0 MIC4426
S2_CH1_DO 1 13V
10/B2 OE0 C439
5 6 1
A1 OUT1 0.1uF
S2_CH2_DO 4
10/B2 OE1
12 11 U39

6
2
A2 OUT2 25V
13 1 8

VS
S2_ADR
10/B2 OE2 NC1 NC2
9 8
A3 OUT3

GND
S2_STB 10 2 7 SEN2_ADR
10/B2 OE3 INA OUTA 14/C2

GND
3.3V 4 5 SEN2_STB
INB OUTB 14/C2
13V

3
74LCX125A C131 MIC4426
1 13V
0.1uF C437
3.3V 1
0.1uF
2
25V
U38

6
2
25V

14
U50 1 8

VS
NC1 NC2
2
A0 VCC OUT0
3 2
INA OUTA
7 SEN2_CLK
14/C2

GND
S2_CLK 1 4 5 COMM_TXD
10/B2 OE0 INB OUTB 14/B2
5 6 13V
A1 OUT1
4

3
Q1TXDC
10/C1 OE1 MIC4426
12 11 13V
A2 OUT2 C441
Q2TXDB 13 1
10/C1 OE2 0.1uF
3.3V R323 9 8
A3 OUT3
GND

10 U52

6
1 2 2
OE3 25V
1 8

VS
NC1 NC2
3.3K
7

1
R321 2 7 SP_FO_TXD
74LCX125A INA OUTA 14/B2

GND
150 4 5
INB OUTB
2

3
1
MIC4426
R416
150

RST5 2
B 2/C4,17/B1,23/B4
13V B
RP9
3.3V 5V 13V 13V 4.7K
C445

DWG_NO
1
0.1uF
RP8

10
5
1
2
3
4
6
7
8
9
C248 C182
1 1 4.7K U58

6
2
0.1uF 0.1uF 25V
3.3V 5V 1 8

VS
NC1 NC2
10
5
1
2
3
4
6
7
8
9
2 2
25V 25V
2 7 SRESET13J

757 044 11W

INA OUTA 14/B2
14

GND
U57 4 5 485_DTR
INB OUTB 14/B2
13V
VCC

3.3V R317 2 3

3
A0 OUT0 MIC4426
1 2 1 13V
OE0 C444
5 6 1
A1 OUT1 0.1uF
Q1IO2A 3.3K 4
10/B1 OE1
12 11 U56

6
2
A2 OUT2 25V
13 1 8

VS
Q1IO3A
10/B1 OE2 NC1 NC2
9 8
A3 OUT3
GND

Q1IO2C 10 2 7 485_DIR
10/C1 OE3 INA OUTA 14/B2

GND
4 5 COMM_RTS
INB OUTB 14/B2
7

3
1
74LCX125A MIC4426
R318
150 5V
2

1 1 1 1
R424 R422 R427 R426
2.2K 2.2K 2.2K 1K
3.3V
2 2 2 2
14

U33
NETPLEX
VCC

R425 2 3 NETPLEX_TXD
A0 OUT0 14/B2
Q2TXDA 1 2 1
10/C1 OE0
R32 5 6 PROG_TXD
A1 OUT1 14/C2
Q2TXDC 1 2 47 4
10/C1 OE1
R319 12 11 DCS_TXD
A 10/D1
Q2TXDD 1 2 47 13
A2
OE2
OUT2 14/B2
A
R295 9 8 NET_RSTJ
A3 OUT3 14/B2
GND

Q_IO_RSTJ 1 2 47 10
10/C1 OE3
47 3.3V
7

C56
R423
74LCX125A
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
1
22uF
150
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
C133 9295 PROTOTYPE DRIVE RENO NV 89521
2
35V
2
0.1uF
1 INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

2
25V
COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 12 OF 24

4 3 2 1

12 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 13 OF 24
4 3 2 1

XCG_BK[0:15]
SD[0:31]
13/D2
2/D1,5/D4,6/C4,9/D4,10/C4,20/C4,24/D4
XCG_BL[0:15]
13/C2
13V 5V 3.3V

SA[0:31] GX2M[0:3]
D 2/C1,4/C2,4/C4,5/D3,9/D3,10/C4,20/C4 6/C1 D
3.3V

J6 J7 XCG_BK[0:15] CG_BK[0:15]
SA1 SA2
A1 B1 A1 B1 13/D2 6/C1
SA3
C1 D1 C1 D1
R264 22
SA4 XCG_BK0 1 2 R43 22 CG_BK0
A2 B2 A2 B2
SA5 SA6 XCG_BL0 XCG_BK1 1 2 R44 22 CG_BK1
C2 D2 C2 D2
XCG_BK2 R85 22 1 2 CG_BK2
SA7 SA8 XCG_BL4 XCG_BK3 1 2 R45 22 CG_BK3
A3 B3 A3 B3
SA9 XCG_BL1 XCG_BL5 XCG_BK4 1 2 R86 22 CG_BK4
C3 D3 C3 D3
XCG_BK5 R87 22 1 2 CG_BK5
SA10 XCG_BL2 XCG_BL6 XCG_BK6 1 2 R91 22 CG_BK6
A4 B4 A4 B4
SA11 SA12 XCG_BL3 XCG_BL7 XCG_BK7 1 2 R78 22 CG_BK7
C4 D4 C4 D4
XCG_BK8 R37 22 1 2 CG_BK8
SA13 SA14 XCG_A1 XCG_BL8 XCG_BK9 1 2 R79 22 CG_BK9
A5 B5 6/C1 A5 B5
SA15 3.3V GX2M0 XCG_BK7 XCG_BK10 1 2 R307 22 CG_BK10
C5 D5 C5 D5
XCG_BK11 R81 22 1 2 CG_BK11
SA16 GX2M1 XCG_BK6 XCG_BK12 1 2 R39 22 CG_BK12
A6 B6 A6 B6
SA17 SA18 1 XCG_A0 XCG_BK13 1 2 R263 22 CG_BK13
C6 D6 C6 D6 6/C1
R265 XCG_BK14 R40 22 1 2 CG_BK14
SA19 SA20 2.2K GX2M2 XCG_BK5 XCG_BK15 1 2 CG_BK15
A7 B7 A7 B7
SA21 XCG_BK4
C7 D7 2 C7 D7
SA22 90NSJ XCG_BK3
A8 B8 6/C2 A8 B8
SA23 SA24 XCG_BK2
C8 D8 C8 D8
XCG_BL[0:15] CG_BL[0:15]
SA25 SA26 CG_DDIR
A9 B9 6/C1 A9 B9 13/D2 6/B1
SA27 XCG_BK1 GX2M3
C9 D9 C9 D9
R47 22
SA28 XCG_BK0 XCG_BL0 1 2 R309 22 CG_BL0
A10 B10 A10 B10
SA29 SA30 XCG_RDJ XCG_BL1 1 2 R267 22 CG_BL1
C10 D10 6/B1 C10 D10
XCG_BL2 R89 22 1 2 CG_BL2
XCG_BLKRW_OR_VBLK1 R268 22
SA31 SBE3J XCG_BL9 XCG_BL3 1 2 CG_BL3
A11 B11 4/B2,9/B1,9/C1,24/C3 A11 B11 6/A1
SBE2J XCG_BK15 XCG_VBLK1 XCG_BL4 1 2 R308 22 CG_BL4
C11 D11 4/B2,9/B1,9/C1,24/C3 C11 D11 6/A1
XCG_BL5 R90 22 1 2 CG_BL5
SBE1J XCG_BK14 XCG_FWR0BJ XCG_BL6 R46 22 CG_BL6
C 4/B2,9/B2,9/C2,24/C3
4/B2,9/B2,9/C2,24/C3
SBE0J
A12 B12
C12 D12
SA0
A12 B12
C12 D12
XCG_BK13
6/B1
XCG_BL7
1 2
1 2 R266 22 CG_BL7 C
XCG_BL8 R83 22 1 2 CG_BL8
SD31 SD30 XCG_ALE XCG_BK12 XCG_BL9 1 2 R306 22 CG_BL9
A13 B13 6/B1 A13 B13
SD29 XCG_D_LATCH XCG_BK11 XCG_BL10 1 2 R77 22 CG_BL10
C13 D13 6/B1 C13 D13
XCG_BL11 R76 22 1 2 CG_BL11
SD28 XCG_D_OEJ XCG_BK10 XCG_BL12 1 2 R75 22 CG_BL12
A14 B14 6/B1 A14 B14
SD27 SD26 XCG_BK9 XCG_BL13 1 2 R35 22 CG_BL13
C14 D14 C14 D14
3.3V XCG_BL14 R74 22 1 2 CG_BL14
SD25 SD24 MEM_SSN_IN XCG_BK8 XCG_BL15 1 2 CG_BL15
A15 B15 10/B2 A15 B15
SD23 MEM_SSN_OUT XCG_BL10
C15 D15 10/B2 C15 D15
1
SD22 R219 XCG_BL11
A16 B16 A16 B16
SD21 SD20 2.2K XCG_VBLK0 3.3V
C16 D16 C16 D16 6/A1
SD19 SD18 2 XCG_BL12 XCG_BL13
A17 B17 A17 B17
SD17 ENET_DETJ XCG_BL14 1
C17 D17 4/C2 C17 D17
R253
SD16 CG_PWRJ XCG_BL15 2.2K
A18 B18 A18 B18
SD15 SD14 XCG_FLATCH2
C18 D18 C18 D18 6/B1 2
SD13 SD12 XCG_FLATCH1_OUT XCG_FLATCH1_IN
A19 B19 6/B1 A19 B19 6/B1
SD11 YAA26 XCG_BLKRWJ
C19 D19 C19 D19 6/A1
SD10 PWRJ YAA25 YAA24
A20 B20 A20 B20
SD9 SD8 YMOEJ YAA0
C20 D20 20/A4,20/B4 C20 D20
SD7 SD6 YAA1 YAA2
A21 B21 A21 B21
SD5 YAA3 YAA4
C21 D21 C21 D21
SD4 VOUT3 9/D2,16/B1,16/B3,17/C1,19/A3 YAA5 YAA6
A22 B22 A22 B22
SD3 SD2 YAA7 YAA8
C22 D22 C22 D22
SD1 SD0 YAA9 YAA10
A23 B23 A23 B23
MLATCH_ADD YAA11 YAA12
C23 D23 4/C2 C23 D23
BOOTCSJ RST3J YAA13 YAA14
4/C2 A24 B24 4/B3,6/D4,10/C3,17/B1,18/D2,20/C4,21/C4,24/B3 A24 B24
GAMECSJ PIXELCSJ YAA15
4/C2 C24 D24 4/C2 C24 D24
AUDIOMEMCSJ SRDJ YAA16 YAA17
4/C2,20/B3 A25 B25 4/C1,4/B2,5/D2,5/A3,10/C3,18/C4,20/C4,24/C3 A25 B25
SWR0J YAA18 YAA19
B C25 D25 4/C1,4/B2,5/B3,5/D2,20/C4,24/C3 C25 D25 B
MEMBDCSJ YAA20 YAA21
4/C1,4/C2 A26 B26 A26 B26
PADS6 YAA22 YAA23
4/C2,13/A4 C26 D26 C26 D26

DWG_NO
MEM_ADD MLATCH_DATA YD0 YD1
4/C2 A27 B27 4/C2 A27 B27
MEM_DATA YD2 YD3
C27 D27 4/C2 C27 D27
3.3V
MOEJ YD4 YD5
4/C2 A28 B28 A28 B28
PADS5 MDIR YD6 YD7

757 044 11W

4/C2,13/A4 C28 D28 4/C2 C28 D28
1
PADS4 PADS3 R24 DSP_BOOT_CSJ
4/C2,13/A4 A29 B29 4/C2,13/A4 20/B4 A29 B29
PADS2 4.7K 3.3V
C29 D29 4/C2,13/A4 C29 D29
PADS1 2
4/C2,13/A4 A30 B30 A30 B30
LEGACYJ
C30 D30 3/C3,4/B3,10/B3,20/C4 C30 D30

3.3V
5V 3.3V

U42
1 1 1 1 1 1
5

R249 R276 R250 R251 R275 R282 2 4 LEGACY YD[0:7]

3/C3,6/D4,18/C4
2.2K 2.2K 2.2K 2.2K 2.2K 2.2K
20/B4
3

2 2 2 2 2 2
PADS1
4/C2,13/B4
PADS2 YAA[0:26]
4/C2,13/B3
PADS3 3.3V
4/C2,13/B3 20/A2,20/B4
PADS4
4/C2,13/B4
PADS5
4/C2,13/B4 C75
PADS6 1
4/C2,13/B4 0.1uF
2
25V

A A
3.3V 5V 13V

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

C112 C104 C113 C118 C106 C116 C125 C110 C30 ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
1 1 1 1 1 1 1 1 1
6.8uF 6.8uF 6.8uF 6.8uF 6.8uF 6.8uF 6.8uF 6.8uF 6.8uF 9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

2 2 2 2 2 2 2 2 2
16V 16V 16V 16V 16V 16V 16V 16V 16V INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE
COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 13 OF 24

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 13

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 14 OF 24
4 3 2 1

CTL CONNS
13V 13V 5V 3.3V 13V 25V
13V
C31 C107 C71
1 1 1
6.8uF 6.8uF 6.8uF C128
1
DIAG/DOWNLOAD PORT C32
B32 2
16V
2
16V
2
16V
C32
B32
6.8uF
2
A32 A32 16V

C31 C31
B31 B31
AUDIO_R_P
Q1RXDD is an input line to the SFPGA on '044 board, LVTTL levels A31 23/B1 A31
AUDIO_R_N
Q1TXDD is an output line from the SFPGA on '044 board, LVTTL levels, 12mA drive strength C30 23/B1 C30
AUX_L
D B30
A30
22/B3 B30
A30 D
3.3V AUX_R USB_P
C29 22/B4 C29 24/B3
3.3V AUDIO_L_N USB_N
B29 23/C1 B29 24/B3
AUDIO_L_P USB_1
A29 23/C1 A29 24/B3
C512 C508
1 1 AUDIO_DATAP USB_2
0.01UF 0.1UF C28 23/A2 C28 24/B3
10% B28 B28
2 2 AUDIO_CLKP
50V 25V A28 23/A2 A28
C507 1
1 2 R523 AUDIO_DATAN
C27 23/A2 C27
10K
B27 B27
0.1UF AUDIO_CLKN
2 A27 23/A2 A27
C505

15
25V U102 1 2 AUDIO_LRP
C26 23/A2 C26
3 2 AUDIO_LRN 3.3V

VCC
V+ C1+ B26 23/A2 B26
C506 0.1UF A26 A26
1 2 7 4 C509
V- C1-
25V 1 2 J19 TT_5V
C25 C25
0.1UF 5
C2+ GND1 B25 B25
0.1UF MAINDOOR_DETJ
1 A25 18/C4 A25
25V 6
C2- 6
25V TXOUT CARDCAGE_DETJ
2 C24 18/D3 C24
RXINJ 9 8 RXIN BILLVAL_DETJ
ROUT RIN 7 B24 18/D3 B24
DOORVAL_OUT
3 A24 18/C1 A24
11 13 TXINJ
TIN TOUT 8
DROPDOOR_DETJ
4 C23 18/C3 C23
16 1
SHDN EN 9 B23 B23
3.3V JKPT_RST

GND
5 A23 11/B3 A23
1
GND2
R527 U116 DP1 DP2
C22 C22
R528 RS232 150 5 1 1 SEN_RST

14
B22 12/D2,14/C2 B22
Q1RXDD 1 2 TRANSCEIVER 2 4 3 3 SEN1_CLK
10/C1 2 A22 12/D2 A22
2 2
47 OHMS 3 SINGLE SEN1_STB
C21 12/D2 C21
B21 B21
SEN1_CH1_DO
A21 12/D2 A21
SEN1_CH2_DO
C20 12/D2 C20
3.3V SEN1_CH1_DI
B20 11/C3 B20
SEN1_ADR
C 10/C1
Q1TXDD
C504
A20 12/D2 A20
C
1 SEN_RST
0.1UF C19 12/D2,14/C2 C19
B19 B19
2 SEN2_CLK
25V A19 12/B2 A19
SEN2_STB
C18 12/C2 C18
SEN2_CH1_DO
B18 12/C2 B18
SEN2_CH2_DO
A18 12/C2 A18
SEN2_CH1_DI
C17 11/C3 C17
B17 B17
SEN2_ADR
A17 12/C2 A17
SEN2_CH2_DI
C16 11/C3 C16
I2C1_CLK
B16 10/B2 B16
I2C1_DATA
A16 10/B2 A16
PROG_RXD
C15 11/B2 C15
B15 B15
PROG_TXD
A15 12/A2 A15
DCS_RXD
C14 11/B2 C14
DCS_TXD
B14 12/A2 B14
NETPLEX_RXD
A14 11/B2 A14
NETPLEX_TXD 5V
C13 12/A2 C13
B13 B13
A13 A13

C12 SP_FO_TXD 12/B2 C12

SP_FO_RXD
B12 11/C3 B12
UT_RXD
A12 11/D3 A12
UT_TXD
C11 12/C2 C11
3.3V
B11 B11
AC_SIN_IN
A11 11/D1 A11
LP_SW
C10 11/C1 C10
1 1 1 1 1 1 1 1 NET_RSTJ
B10 12/A2 B10
3.3V 3.3V R194 R197 R200 R203 R206 R208 R210 R243 485_RXD
B 100 100 100 100 100 100 100 100
A10 11/D3 A10 B
485_TXD
C196 C122 2 2 2 2 2 2 2 2 C9 12/C2 C9
1 1
0.1uF 0.1uF B9 B9

DWG_NO
485_DTR
A9 12/B2 A9
2 2 2 2 2
25V 25V 2 2 2 2 2
485_DCD
C8 11/D1 C8
DS8 DS7 DS6 DS5 DS4 DS3 DS2 DS1 485_DIR
3.3V B8 12/B2 B8
RED YELLOW YELLOW YELLOW YELLOW YELLOW GREEN GREEN
A8 A8
1

757 044 11W

1 1 1 1 1
1 1 COMM_RXD
C7 11/D3 C7
14

LED1 U70
10/B2 B7 B7
VCC

LED2 COMM_TXD
10/B2 A7 12/B2 A7
LED3 2 3 FAIL
10/B2 A0 OUT0
LED4 1 COMM_CTS
10/B2 OE0 C6 11/D1 C6
5 6 OUT7 COMM_RTS
10/C1 A1 OUT1 B6 12/B2 B6
4
10/C1 OE1 A6 A6
12 11 OUT6
A2 OUT2
13 PWR_SAVE
OE2 C5 10/C1 C5
CHANGE TO LED5,6 9 8 OUT5
A3 OUT3 B5 B5
GND

10 SRESET13J
OE3 A5 12/B2 A5
V1_VSYNC
7

SERMB1
74LCX125A C4 C4 8/C1
SERMB2
3.3V B4 B4
SERMB3 V1_HSYNC
A4 A4 8/C1
SERMB4 SERMB[1:4]
C3 C3
14

U66
B3 10/B4 B3
VCC

A3 A3
2 3 Q2OUT3
A0 OUT0
Q2IO3B 1 V1_B
OE0 C2 C2 8/C1
5 6 Q2OUT2 BC2MB1 V1_G
A1 OUT1 B2 B2 8/C1
Q2IO2B 4 BC2MB2 BC2MB[1:2] V1_R
OE1 A2 A2 8/C1
12 11 PWRGOOD
A2 OUT2 4/B2
13
OE2 C1 C1
9 8 RUNJ
A3 OUT3 B1 B1
GND

3.3V 10
OE3 A1 A1
U68 J5 J17
7

74LCX125A
5

PWR_GOOD 2 4
A 10/A3,17/C2,18/A2
A
3

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

4/B2
BC_LED6
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

14 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 15 OF 24
4 3 2 1

HEATSINK
HS_Q1

13V

1
2
C20 C22 C21
1 1 1 1 2
220uF 220uF 220uF
R501
2 2 2 10
16V 16V 16V
25V 2
TMMBAT42 3.3V @7.5A
2 CR6 2
1 Q1
(LIMITED BY INDUCTOR)
0.1uF IRL3103S
1 1
C499
1 3 3.3V
D R500 1
C498
0.1uF D

1
1K U13 C23
L1
2 2 6 1 2 R4

GND VCC
2 25V CS- BST
1 2 1 2
3 R6 0.1uF 6uH
CS+

PGND
5 1 2 7.5A 0.01
DH C143 C119 C51 C65 C166 C40 C39 C17 C41
7 25V CR5 1 1 1 1 1 1 1 1 1 1

3
FB 470uF 470uF 470uF 470uF 470uF 470uF 470uF 470uF 470uF
1 2.7 MBRB1530CT R498
R499 2 2 2 2 2 2 2 2 2 205

8
4
SC1103 25V 25V 25V 25V 25V 25V 25V 25V 25V

1
1K C501
3.3V 2
1 2
2 10A 25V 2

1
2
0.1uF 0.1uF
1 1
C19
25V R497
124

HS_CR5 2
HEATSINK

C C
13V

C54 C26
1 1 1
22uF 22uF
R18 1 3.3V 2.5V_SER
C27
2 2 4.7K 1 R19 U49
35V 35V 0.001uF
4.7K 8 1
2 IN OUT
C29 2
50V 2
1 2 4 1
BYP C86 C84
R293 1 1

GND1
GND2
GND3
0.1uF C94 C339 1uF 0.1uF
1 5 2 1 11K
6.8uF SHDN SENSE 0.01uF
2 2
50V 2 35V 25V
25V 2 2

3
6
7
16V 500mA LT1763

5
6
7
8
U14
5V @3A 0V

VIN
Q2 (LIMITED BY SCHOTTKY DIODE) 1
1 7 IRF7201 R291
SENSE BOOST
XREF=16/C2,17/C2 3VOK 1 2 2 6 4 10K
I/RUN TG
3 GND 5 5V
VFB SW C24 2
CR7 1
C28 C25 0.1uF
1 1

1
2
3
470pF 100pF L5
TMMBAT42 LTC1624 2
4

50V 25V
2 2 900mA 1 2
50V
10uH C154 C55
1 1 3.5A 1 1 1
220uF 220uF
R5 CR14 R431
4.7K MBRS340 2 2 35.7K
16V 16V
2 2
2

1
R432
11K
2

B 3.3V 2.5V_BC B
U77
8 1
IN OUT

DWG_NO
4 1
BYP C147 C315
R226 1 1

GND1
GND2
GND3
C150 C251 1uF 0.1uF
1 5 2 1 11K
6.8uF SHDN SENSE 0.01uF
2 2
2 35V 25V
2 500mA 2

3
6
7

757 044 11W

16V LT1763 50V
0V
1
R225
10K
2

3.3V 1.5V_GX 5V 3.3V_AUX_BZ

U95 U96
8 1 8 1
IN OUT IN OUT
4 1 4 1
BYP C162 C220 BYP C218 C221
R187 1 1 R185 1 1
GND1
GND2
GND3

GND1
GND2
GND3
C149 C217 C219 6.8uF 0.1uF C153 C216 1uF 0.1uF
1 5 2 1 1 2.32K 1 5 2 1 21K
6.8uF SHDN SENSE 0.01uF 6.8uF SHDN SENSE 0.01uF
0.01UF 2 2 2 2
2 16V 25V 2 35V 25V
2 500mA 2 2 2 2
3
6
7

3
6
7
16V LT1763 50V 50V 16V 500mA LT1763 50V
0V 0V
1 1
R186 R184
10K 12.1K
2 2
A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 15

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 16 OF 24
4 3 2 1

13V 13V
U23
U24 R15 CR11
2 1 3 2 1 2

GND
IN OUT IN OUT1
1 3
C436 C435 C45 C430 C431 C427 C426 C44
1 1 1 1 1 1 4 1 1 1 4.7K 1N914
0.1uF 0.1uF 6.8uF 0.1uF 0.01uF ADJ OUT2 0.01uF 0.1uF 6.8uF

3
LM3480
2 2 2 2 2 LX1117 2 2 2
25V 5V 25V 16V 25V 50V 50V 25V 16V
0A
100mA
0V
R414
1 2

1K
D BAT54 D
CR8

1 3

R405
1 2
3.3V TT_BAT
1MEG ohms
3
Q3
R378 1 2
2N7002
1 2 1 1 2 3 SLEEVED
IRLML6302
2 R411 NIMH
C411 Q6
1 1 1 4.7K 10K 3 140AH
0.1uF 2 3
R403 R387 1 3.6V
Q4 1
100K ohms 10K 2 R379 BT1
25V 2N7002
4.7K 1 1

6
2 2 U15 2 R410
5 2 3 402K

GND VCC
TS Q5
1 2
TM LED 2N7002 2
3 8 1
BATT CC
1 1 7 2
INH
R404 R386
332K ohms 10K 1 1

4
C433 BQ2002
1 R377 R409
2 2 0.1uF 5V
150 392K
250uA
2
25V 2 2

TT_BAT_CHG
18/C2

C C

1
R396
3.3V 1MEG
2 5V TT_5V
1

1
R395
10K
3 3VOK
2 Q9 15/C4,17/C2
1 3
2N7002
1 CR12
C47 C423
2 2 BAT54 1 1
6.8uF 0.1uF
1 3.3V
IRLML6302
2 2
Q8 16V 25V
3
1 3 1 3
U22 CR9 CR10
1 3 BAT54 BAT54
IN OUT
TT_BAT_OK 4
FB
16/B2 3 1 1

GND
C43 C429 C428 C42
CR13 1 1 5 6 R412 1 1
1uF 0.1uF SHDN POK 0.1uF 1uF
BAT54 2MEG 2
2 2 MAX8880 2 2 1 TT_3V

2
25V 25V 2 25V 25V IRLML6302
50mA

1
Q7
0V 3
1
1 R406
R530 10K
C424
100K 1
2 0.1uF
2 2
25V
1
R413
B 1.1MEG B
2

DWG_NO
VOUT3 3.3V 3.3V
9/D2,13/B3,16/B1,17/C1,19/A3
3.3V
VOUT3
C422 C18 9/D2,13/B3,16/B3,17/C1,19/A3
1 1
0.1uF 0.1uF C522
1 1

757 044 11W

0.1UF
2 1 1 2 R531
25V 25V
R391 R394 2 4.7K
25V
3V_LITHIUM 1MEG 4.64K
17/D3 2
U117

8
U26 2 2
16/B4
10MEG 10MEG 5
VCC
2 1 TT_BAT_OK 1 TT_BAT_OKJ
1 2 1 2 OE
R398 5 7 SRAM_BAT_LO 2 4 18/C2
10/D1 A Y
1 2 R399 R400 3
6 3
GND
1.27MEG 1 1
REF_BT2 BT2 R401 R532
1.1MEG 4 ICLT665 150 NC7SP125

1 2 2 2

3 40

10MEG 10MEG

R390 1 2 1 2
1 2 R392 R393

1.1MEG
1
R397
1MEG
2
A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

16 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 17 OF 24
4 3 2 1

D D

16/B4 3V_LITHIUM

3.3V
3.3V 3.3V
3.3V
C191
1
0.1uF
C142
1 1 1 3.3V 2
0.1uF 25V
13V R120 R202 3.3V
2 3.3V 10K 2.2K
25V 10/A3,14/A4,18/A2
3.3V

14
1 2 2 U71
R204 1 3 3VOK PWR_GOOD 1

VCC
A0 O0 C120
68K 3.3V 5V 2 1 R119
B0 0.1uF

10
U69 10K
2 15/C4,16/C2
1 9 4 6

GND VCC
2
IN1 OUT1 A1 O1 25V 2
2 8 5
IN2 OUT2 B1
3 7 3.3V
IN3 OUT3
4 6 13 11
<10V = IRQ IN4 OUT4 A2 O2
12
B2

2
U65

5
1
C136 MAX6338AUB
R205 10 8 4 5 PORJ

GND

VCC
C229 C158 0.1uF A3 O3 PFI PFO 17/B4,18/C4
10K 1 1 1 9
0.1uF 0.1uF 0A B3
3.3V 8 7
2 VBATT RESET
2 2 2 3.3V

GND
25V 25V 25V 74AC08
6 VOUT3
C124 WDI VOUT 9/D2,13/B3,16/B1,16/B3,19/A3
1 1
C 0.1uF
1 1
C

3
MAX690T
2 R118 1 R110
25V SUPERVISORY C129
2.2K 1 100K
C130 6.8uF
2
2 0.1uF 2
2
25V 16V
WATCHDOGCSJ
4/B2
FPGA_DONE
4/C4,6/A4,10/D4
V13_FAIL_INTJ
5/C2
5V

1
C132
1 R207
0.1uF Synchronizes H-L edge of CPU reset
2.2K
OPTION OPTION 2
25V 2 next cclk/cclk2 L-H edge is "A"
CCLK2 CCLK
C231 C230
3/C1,17/B4 1 3/C1,17/B4 1 5V 4 14
10pF 10pF
U67
2 2 3.3V
50V 50V PRE VDD
1 RESETQ 2 5 CPURESET 3.3V 5V
D Q C159
R209 1
0.1uF
2.2K
2
2 25V
3 6 CPURESETJ 1 1 1 1
CLK Q
3.3V R199 R196 R198 R195
2.2K 2.2K 2.2K 2.2K
10 14
CLR GND 2 2 2 2
U67 74ACT14

14
FF U72
PRE VDD
1 7

VCC
PORJ 12 9 2 3 RST3J
17/C1,18/C4 D Q A0 OUT0 4/B3,6/D4,10/C3,13/B3,18/D2,20/C4,21/C4,24/B3
1
OE0
5 6 RST3
A1 OUT1 4/C1
4
B 11
CLK Q
8 12
OE1
A2 OUT2
11 RST5J
19/C3
B
13
OE2
9 8 RST5
A3 OUT3 2/C4,12/B4,23/B4

GND

DWG_NO
10
CLR GND OE3
CCLK 74ACT14
3/C1,17/C4
FF

7
1
13 7 R201
74LCX125A
150

757 044 11W

CCLK2
3/C1,17/C4

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 17

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 18 OF 24
4 3 2 1

TT_3V

1
1 1 1 1
R92 R94 R99 R97
470K 470K 470K 10K
2 2 2 2
J11 TT_3V
TT_TMS

1
TT_TDI
TT_TDO 1
TT_TCK TT_3V R115
470K

1
3.3V
D C127 C425
2
OPTION D
TT_3V TT_3V 1 1
6.8uF 0.1uF

1
2 2 R111 100K
16V 25V
1 2 RST3J
C510 C511 4/B3,6/D4,10/C3,13/B3,17/B1,20/C4,21/C4,24/B3
1 1
0.1UF 0.1UF
R104 22
2 2 TT_3V SRAM0CE
25V 25V 9/C1,9/C2
1 2

1
R103 22
1 1 1 1 TT_1.8V TT_3V SRAM0CEJ
9/C1,9/C2
R448 R447 R446 R449 1 2

1
470K 470K 470K 470K
R116 22
TT_3V TT_3V 2 2 2 2 SRAM1CE

26
35
9/B2,9/B1

7
U63 1 2

1
BILLVAL_DETJ

VCC1
VCC2
VCC3
VCC4
14/C2
U106 U105 CARDCAGE_DETJ 10 R93 22
14/C2 TMS
DROPDOOR_DETJ 9 SRAM1CEJ

5
14/C2 TDI 9/B2,9/B1
MAINDOOR_DETJ 2 4 2 4 MAINDOOR_DETJ_3.3V 24 30 1 2
14/C2 TDO JTAG
11
TCK
TT_3V R254 42 R96 47 TT_5V
SRAM0CE

3
1 2 R256 38 43 SRAMWRJ

1
BVDETJ SRAM0CEJ 9/B2,9/B1,9/C1,9/C2
1 2 R269 37 44 1 2
CCDETJ SRAM1CE
10K 1 2 R255 36 1 1
DDDETJ SRAM1CEJ
1 1 1 1 10K 1 2 34 2 R95 22 R272
MDDETJ SRAMWRJ
R258 R261 R259 R98 10K 3 SRAMOEJ 10K
SRAMOEJ 9/B2,9/B1,9/C1,9/C2
470K 470K 470K 10K 10K 33 1 2
CC_ALARM 2
32 5 BVOPENJ
2 2 2 2 MD_ALARM BVOPENJ 10/D1
Door signal from Darlington optic can be as high as 1.1V for a low. 6 CCOPENJ R273
CCOPENJ 10/D1
TT_CLK 18 8 DDOPENJ 1 2 TTDETJ
18/B1 TT_CLK DDOPENJ 10/C1 10/C1
Comp neg threshold for OR gate on backplane can be as low as 0.8V. TT_DISABLEJ 29 12 MDOPENJ
10/C1 TT_EN MDOPENJ 10/C1
TT_CTL1 28 100K
10/C1 TTCTL1
Inverters are used to translate 5V output (when game is powered) to 3.3V for CoolRunnerII. TT_CTL2 27 13 1 1 1 1 TT_3V
10/C1 TTCTL2 TTCLKOUT
INTERROGATE 23 R112 R113 R101 R102 DOORVAL_OUT

1
10/C1 INTERROGATE 14/C2
PORJ 22 10K 10K 10K 10K
17/B4,17/C1 PORJ
LEGACY 21 1
3/C3,6/D4,13/B3 LEGACY 2 2 2 2
RTC1_SRAM_OEJ 20 R270
5/D2,19/C2 RTC1_SRAMENJ
SRAM0CSJ 19 200K
4/B2,4/C1 SRAM0CSJ 3
SRAM1CSJ 39
C 4/C1,4/B2
4/B2,5/B3,10/C3
SWR1J 40
SRAM1CSJ
WRJ BAT_LO_OUT
14 2 R271
Q10
IRLML2402 C
SRDJ 41 16 TT_CLK_G 1 2 1
4/C1,4/B2,5/D2,5/A3,10/C3,13/B3,20/C4,24/C3 RDJ BAT_LO_IN
31 2
BAT_CHG

GND1
GND2
GND3
100
1 1 1 1 1

OPTION
R106 R107 R105 R100 R108 BAT_LO_OUT
10/D1
10K 470K 470K 470K 470K

4
17
25
ICNAME
R529 0
2 2 2 2 2 TT_BAT_OKJ
16/B1

2
OPTION

R512 0
TT_BAT_CHG
16/C1

2
1 R257 1 1 R260 1
1K R114 1K R274
10K 10K OPTION 1
R402
3.3V 2 2 2 2 10K

1
2
OPTION

OPTION OPTION

TT_3V TT_3V
B R240 B

1
1 2

C432

DWG_NO
332K 1
0.1uF
1 1 1 TT_3V 1
PLACE AS CLOSE AS POSSIBLE R234 R236 R239
C308
1 R241 2

1
0.001uF 25V
47K 10K 10K 200K
TO PIN U63.15 2

16
2 2 2 50V 2
U82

757 044 11W

1
TT_3V TT_1.8V 2
Iin ~ 3.5uA max. 3 13 TT_CLK
1

18/C4
U101 9 6
1 3 10 4
IN OUT
4 11 5
FB
1 1 12
GND

C514 C517 C513 C515

1 1 5 6 R525 R526 1 1 7
1UF 0.1UF SHDN POK 1UF 0.1UF
1MEG 1MEG 14
2 2 MAX8880 2 2 15
2

10V 25V 2 2 10V 25V

50MA
0V R144 R231 R238 R235 R242 R237 4536

8
1K 1K 1K 1K 1K 1K
Ishdn ~ 0.1uA max. 1 1 1 1 1 1
C307
1 1 TIMER
0.001uF
R521
uPower device 100K 2
50V 2 2 2 2 2 2
2

1
R522
1.1MEG
2

10/A3,14/A4,17/C2 PWR_GOOD

Idiv ~ 1uA

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

18 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 19 OF 24
4 3 2 1

D D

C36
1
0.1uF
5V
2 5V
25V
2
Y3 1

15
16
32.768KHz U41 R23
1 4.7K

1 2
2 7

WR5J 3 6
5/D1
RST5J 13
17/B1
9

RD5J 12
5/D1
10 RTC1_SRAM_OEJ
5/D2,18/C3
RTC1_CSJ 11
4/C2
VOUT3
4
14
C328
1
0.1uF
1 1
2 R21 R20 DS1315

5
8
25V
4.7K 4.7K RTC
C C
2 2

3.3V

C59
1 5V
0.1uF
2
25V
3.3V 1
R22
4.7K

14
U47
2

VCC
SRAMD0 2 3 RTCDI
19/C2 A0 OUT0
RTCDILOJ 1
4/C2 OE0
SRAMD16 5 6
19/C2 A1 OUT1
RTCDIHIJ 4
4/C2 OE1
12 11 SRAMD16
A2 OUT2 19/C3
13
OE2
9 8 SRAMD0
A3 OUT3 19/C3

GND
RTCDOUTJ 10
4/C2 OE3

7
74LCX125A

B B

DWG_NO
Y2

4
RTC_3V

3
32.768KHz

4
2

757 044 11W

8
U27
1

VDD
OSCI
2 3
OSCO INT
I2C2_CLK 6 7

GND
10/B2 SCL CLKOUT
I2C2_DATA 5
10/B2 SDA
PCF8563TD

4
L4 RTC_3V
VOUT3
1 2
9/D2,13/B3,16/B1,16/B3,17/C1
50 OHMS

A 1
C48
1
C49
0.1uF A
6.8uF
2 2
16V 25V

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 7587 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 19 OF 24

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 19

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 20 OF 24
4 3 2 1

3.3V 3.3V
3.3V

C482 C455 C454 C480 C451 C481 C325 C324 C323 C322 C304 C321
1 1 1 1 1 1 1 1 1 1 1 1
C165 C92 C52 C79 C193 C194 C202 C204 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
1 1 1 1 1 1 1 1
6.8uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF
2 2 2 2 2 2 2 2 2 2 2 2
50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V 50V
2 2 2 2 2 2 2 2
16V 25V 25V 25V 25V 25V 25V 25V

D D

DSP_D[16:47]

20/C3,21/C2
J4 3.3V

DSP_A[0:23]
20/C3,21/D2
3.3V
3.3V U40

141

109
127
42
84

37
55
73
8

1
1 1 1 1

VCCINT1
VCCINT2
VCCINT3
VCCINT4

VCCIO1
VCCIO2
VCCIO3
VCCIO4
VCCIO5
VCCIO6
2X4 R284 R288 R287 R278
VERTICAL 4.7K 4.7K 4.7K 4.7K
HEADER 2 2 2 2 DSP_A[0:23]
M 67 20 DSP_A0 20/D2,21/D2
TCK DSP_A0
65 21 DSP_A1 3.3V 3.3V
TMS DSP_A1
63 22 DSP_A2
TDI DSP_A2
122 23 DSP_A3
TDO DSP_A3
24 DSP_A4
DSP_A4
25 DSP_A5
DSP_A5
26 DSP_A6
DSP_A6
27 DSP_A7

14
27
43
49

14
27
43
49
DSP_A7
SDRAM FOR THE AUDIO DSP

1
3
9

1
3
9
9 DSP_A8 U6 U11
DSP_A8
SRDJ 32 10 DSP_A9

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7

VCC1
VCC2
VCC3
VCC4
VCC5
VCC6
VCC7
4/C1,4/B2,5/D2,5/A3,10/C3,13/B3,18/C4,24/C3 SRDJ DSP_A9
SWR0J 38 11 DSP_A10 DSP_A0 23 2 DSP_D16 DSP_A0 23 2 DSP_D32
4/C1,4/B2,5/B3,5/D2,13/B3,24/C3 SWRJ DSP_A10 A0 DQ0 A0 DQ0
SND_RDY 5 12 DSP_A11 DSP_A1 24 4 DSP_D17 DSP_A1 24 4 DSP_D33
20/A4 SND_RDY DSP_A11 A1 DQ1 A1 DQ1
13 DSP_A12 DSP_A2 25 5 DSP_D18 DSP_A2 25 5 DSP_D34
DSP_A12 A2 DQ2 A2 DQ2
14 DSP_A13 DSP_A3 26 7 DSP_D19 DSP_A3 26 7 DSP_D35
DSP_A13 A3 DQ3 A3 DQ3
YAM_RSTJ 6 15 DSP_A14 DSP_A4 29 8 DSP_D20 DSP_A4 29 8 DSP_D36
4/A3,10/B4,20/A4 YAM_RSTJ DSP_A14 A4 DQ4 A4 DQ4
LEGACYJ 3 16 DSP_A15 DSP_A5 30 10 DSP_D21 DSP_A5 30 10 DSP_D37
3/C3,4/B3,10/B3,13/B3 LEGACYJ DSP_A15 A5 DQ5 A5 DQ5
RST3J 143 17 DSP_A16 DSP_A6 31 11 DSP_D22 DSP_A6 31 11 DSP_D38
4/B3,6/D4,10/C3,13/B3,17/B1,18/D2,21/C4,24/B3 RST3J DSP_A16 A6 DQ6 A6 DQ6
19 DSP_A17 DSP_A7 32 13 DSP_D23 DSP_A7 32 13 DSP_D39
DSP_A17 A7 DQ7 A7 DQ7
SA[0:31] 28 DSP_A18 DSP_A8 33 42 DSP_D24 DSP_A8 33 42 DSP_D40
DSP_A18 A8 DQ8 A8 DQ8
SA1 115 31 DSP_A19 DSP_A9 34 44 DSP_D25 DSP_A9 34 44 DSP_D41
C 2/C1,4/C2,4/C4,5/D3,9/D3,10/C4,13/D4 SA1 DSP_A19
DSP_A20
33 DSP_A20 22
A9
A10
DQ9
DQ10
45 DSP_D26 22
A9
A10
DQ9
DQ10
45 DSP_D42 C
4 DSP_A21 DSP_A11 35 47 DSP_D27 DSP_A11 35 47 DSP_D43
DSP_A21 A11 DQ11 A11 DQ11
SD0 92 7 DSP_A22 48 DSP_D28 48 DSP_D44
SD0 DSP_A22 DQ12 DQ12
SD1 93 34 DSP_A23 DSP_A13 20 50 DSP_D29 DSP_A13 20 50 DSP_D45
SD1 DSP_A23 BA0 DQ13 BA0 DQ13
SD2 94 DSP_A14 21 51 DSP_D30 DSP_A14 21 51 DSP_D46
SD2 BA1 DQ14 BA1 DQ14
SD3 95 DSP_D[16:47] 53 DSP_D31 53 DSP_D47
SD3 DQ15 DQ15
SD4 96 35 DSP_D16 20/D1,21/C2 16 16
SD4 DSP_D16 WE WE
SD5 97 39 DSP_D17 19 R456 0 19 R476 0
SD5 DSP_D17 CS CS
SD[0:31] SD6 98 40 DSP_D18 38 36 38 36
SD6 DSP_D18 CLK NC1 CLK NC1

2
SD7 100 41 DSP_D19 17 40 17 40
2/D1,5/D4,6/C4,9/D4,10/C4,13/D4,24/D4 SD7 DSP_D19 CAS NC2 CAS NC2
43 DSP_D20 18 OPTION 18 OPTION
DSP_D20 RAS RAS
44 DSP_D21 37 37
DSP_D21 CKE CKE
OUTCSJ 117 135 DSP_D22 DSP_A12
4/B3,10/B4,20/A4 OUTCSJ DSP_D22 20/C1
VOLCTLCSJ 118 136 DSP_D23
4/B2,10/B3,20/A4 VOLCTLCSJ DSP_D23
AUDIO1CSJ 107 137 DSP_D24 39 39

GNDQ1
GNDQ2
GNDQ3
GNDQ4

GNDQ1
GNDQ2
GNDQ3
GNDQ4
4/B2,20/A4 AUDIO1_CSJ DSP_D24 DQMU DQMU

GND1
GND2
GND3

GND1
GND2
GND3
AUDIO2CSJ 113 138 DSP_D25 15 15 DSP_A12
4/B2,20/A4 AUDIO2_CSJ DSP_D25 DQML DQML
AUX_AUDIO_CSJ 106 139 DSP_D26
4/B2,20/A4 AUX_AUDIO_CSJ DSP_D26 20/C2
140 DSP_D27
DSP_D27
SDRAM SDRAM

28
41
54

6
12
46
52

28
41
54

6
12
46
52
121 DSP_BMSJ
DSP_BMSJ 20/A4
YAA0 50 126 DSP_MS1J
YAA0 DSP_MS1J 21/C2,21/C1
YAA1 51 128 DSP_MS2J
YAA1 DSP_MS2J 21/C2,21/C1
YAA2 52 129 DSP_MS3J
YAA2 DSP_MS3J 21/C2,21/C1
YAA3 53
YAA3
YAA4 54
YAA4
YAA5 56 30 DSP_CLKOUT
YAA5 DSP_CLKOUT 21/C4
YAA6 57 124 DSP_WRJ
YAA6 DSP_WRJ 21/B2,21/D1
YAA7 58 125 DSP_RDJ SDA10
YAA7 DSP_RDJ 20/A4,21/B2,21/D1 21/B2
YAA8 59
YAA9 60
YAA8
YAA9
XC95288XL 21/B2
SDWEJ
YAA10 61 142 HBRJ
YAA10 HBRJ 21/C4,21/D1
YAA11 64 45 HBGJ DSP_MS0J
YAA11 HBGJ 21/C4,21/D1 21/C2,21/D1
YAA12 66
YAA12
YAA13 68 46 DSP_IRQ0J SDCLK0
YAA13 DSP_IRQ0J 20/A4,21/A4,21/C1 21/B2
YAA14 69 48 DSP_IRQ1J
YAA14 DSP_IRQ1J 20/A4,21/A4,21/C1
YAA15 70 49 DSP_IRQ2J SDCLK1
YAA15 DSP_IRQ2J 20/A4,21/A4,21/C1 21/B2
YAA16 116
YAA16
YAA17 71 130 FLAG2 CASJ
YAA17 FLAG2 21/B4 21/B2
YAA18 74 131 FLAG3
B YAA19 75
YAA18
YAA19
FLAG3
FLAG7
132 FLAG7
21/B4
21/B4 21/B2
RASJ B
YAA20 76 133 FLAG8
YAA20 FLAG8 21/B4
YAA21 77 134 FLAG9 SDCLKE
YAA21 FLAG9 21/B4 21/B2

DWG_NO
YAA[0:26] YAA22 78 119 FLAG10
YAA22 FLAG10 21/B4
YAA23 79 120 FLAG11 DQM
13/A2,20/A2 YAA23 FLAG11 21/B4 21/B2
YD0 80
YD0
YD1 81 101 AUDIOMEMCSJ
YD1 S1 4/C2,13/B4
YD2 82 102 AAMUX_CTL
YD2 S2

757 044 11W

YD3 83 103 TEST1
YD3 S3 20/A4
YD4 85 104 TEST2
YD4 S4 20/A4
YD5 86 105 TEST3
YD5 S5 20/A4
YD[0:7] YD6 87
YD6
YD7 88
13/A2 YD7
110 VOL_LOAD
VOL_LOAD 10/A2
YMOEJ 2 111 VOL_CLK
13/B2,20/A4 YMOEJ VOL_CLK 10/A2
DSP_BOOT_CSJ 91 112 VOL_DATA 3.3V
13/B2 DSP_BOOT_CSJ VOL_DATA 10/A2

C74
1
0.1uF
GND10
GND11
GND12
GND13
GND1
GND2
GND3
GND4
GND5
GND6
GND7
GND8
GND9

3.3V 2
25V
RAA[24:26]
18
29
36
47
62
72
89
90
99
108
114
123
144

10/A4

16
U19
RAA24 2 YAA[0:26]

VCC
IN1A
FLAG4 3 4 R369 47 YAA24
21/B4 IN1B OUT1Y 13/A2,20/B4

2
RAA25 5
IN2A
FLAG5 6 7 R371 47 YAA25
21/B4 IN2B OUT2Y

2
RAA26 11
IN3A
FLAG6 10 9 R366 47 YAA26
21/B4 IN3B OUT3Y

2
14
IN4A
13 12
IN4B OUT4Y
Debug header 15

GND
G
1
AB
J2
SND_RDY

8
20/C4
YAM_RSTJ DSP_IRQ0J 74LVC157
A 4/A3,10/B4,20/C4
DSP_IRQ1J
20/B3,21/A4,21/C1
20/B3,21/A4,21/C1 A
1

2
YMOEJ DSP_IRQ2J MUX
13/B2,20/B4 20/B3,21/A4,21/C1
R364
150

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

OPTION
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

Debug header
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

TEST1
J3
DSP_BMSJ
COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
20/B3 20/C3 OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
20/B3
TEST2
AUDIO1CSJ
TEST3
DSP_RDJ
20/B3
OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
4/B2,20/C4 20/B3,21/B2,21/D1
AUDIO2CSJ OUTCSJ
4/B2,20/C4
AUX_AUDIO_CSJ VOLCTLCSJ
4/B3,10/B4,20/C4 WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
4/B2,20/C4 4/B2,10/B3,20/C4 DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
OPTION DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 20 OF 24

4 3 2 1

20 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 21 OF 24
4 3 2 1

R7 4.7K
1 2
R3 4.7K
1 2 3.3V
3.3V 1.8V DSP_AVDD R454 0
U16 1 2 3.3V
3 R360 10 R1
IN
2 4 1 2 1 1 1
OUT1 OUT2

2
1 4.7K R2 R453 R361 DSP_RDJ R346 10K
GND 20/A4,20/B3,21/B2
4.7K 4.7K 4.7K 1 2
C32 C37 C385 C376 C368 C369
1 1 ADP3338AKC 1 1 1 1 1 DSP JTAG HEADER DSP_WRJ R277 10K
C33 1uF 220uF 1uF 0.1uF 0.1uF 0.01uF 2 2 2 20/B3,21/B2
1.8V 1 2
6.8uF 25V
2 2 2 2 2 2 2 J1 DMAR1J R450 10K
16V 16V 25V 25V 25V 50V 21/B4
EMUJ 1 2
21/C4
DMAR2J R452 10K
21/B4
TMS 1 2
21/C4
TCLK HBRJ R339 10K
D TRSTJ
21/C4
21/C4
20/B3,21/C4
1 2 D
TDI DSP_RDY R357 10K
21/C4 21/C4
TDO 1 2
21/C4
DSP_CSJ R358 10K
21/C4
OPTION 1 2
BRST R348 10K
21/C4
1 2

3.3V 1.8V DSP_AVDD

3.3V
WHEN USING THE ICE,

REMOVE THE 0 OHM RESISTORS DSP_MS0J R344 10K

20/B3,21/C2
1 2

G11

H11

N14
E11

E10

K11
F11
L11

L10
J11
HBGJ R289 10K

M8
G5

D8
H3
H5
E5
E7
E9

E6
E8

K5
F5
L5
L7
L9

L6
L8
J5
20/B3,21/C4
U18 DSP_A[0:23] 1 2
M5 DSP_A0 SBTSJ R342 10K

AVDD
VDDEXT1
VDDEXT2
VDDEXT3
VDDEXT4
VDDEXT5
VDDEXT6
VDDEXT7
VDDEXT8
VDDEXT9
VDDEXT10
VDDEXT11
VDDEXT12
VDDEXT13

VDDINT1
VDDINT2
VDDINT3
VDDINT4
VDDINT5
VDDINT6
VDDINT7
VDDINT8
VDDINT9
VDDINT10
VDDINT11
VDDINT12
VDDINT13
VDDINT14
A0 20/D2,20/C3 21/C4
N5 DSP_A1 1 2
A1
P8 L4 DSP_A2 DMAG2J R451 10K
BR1 A2 21/B4
N8 R4 DSP_A3 1 2
BR2 A3
R7 P4 DSP_A4 DMAG1J R475 10K
BR3 A4 21/B4
P7 N4 DSP_A5 1 2
BR4 A5
N7 M4 DSP_A6 DSP_IRQ2J R27 10K
BR5 A6 20/A4,20/B3,21/A4
M7 R3 DSP_A7 1 2
BR6 A7
P3 DSP_A8 DSP_MS1J R280 10K
A8 20/B3,21/C2
P2 DSP_A9 1 2
A9
AUDIO_MCLK2 BRST N9 N3 DSP_A10
23/C4,23/B4 21/D1 BRST A10
M12 R2 DSP_A11
ACK A11
SBTSJ P6 M2 DSP_A12
21/D1 SBTS A12
A2 P1 DSP_A13
BMSTR A13
AUDIO_MCLK1 N1 DSP_A14
22/B1 A14
N2 DSP_A15 3.3V
A15
TCLK D2 M1 DSP_A16
21/D2 TCLK A16
TDI B2 L2 DSP_A17
21/D2 TDI A17
TMS C1 M3 DSP_A18
21/D2 TMS A18
OPTION TDO D1 L1 DSP_A19
21/D2 TDO A19
TRSTJ B1 K3 DSP_A20 DSP_MS2J R279 10K
21/D2 TRST A20 20/B3,21/C2
R8 4.7K EMUJ C2 L3 DSP_A21 1 2
21/D2 EMU A21
1

K2 DSP_A22 DSP_MS3J R281 10K

A22 20/B3,21/C2
3.3V K4 DSP_A23 3.3V 1 2
A23
R9 4.7K DSP_IRQ1J R359 10K
C 20/A4,20/B3,21/A4
C
1

N6 DSP_MS0J 1 2
MS0 20/B3,21/D1
R13 M6 R345 47 DSP_MS1J 1 DSP_IRQ0J R25 4.7K
XTAL MS1 20/B3,21/C1 20/A4,20/B3,21/A4

2
R10 4.7K AUDIO_MCLK0 P12 P5 DSP_MS2J R353 1 2
CLKIN MS2 20/B3,21/C1
1

2
R9 R5 DSP_MS3J 10K FS2 R380 10K
Y1 CLKOUT MS3 20/B3,21/C1 21/B4,24/C3
DSP_CLKOUT R347 47 1 2
11.2896MEGHz 20/B3 2

2
1 4 3 A3 DSP_BMSJ FS3 R381 10K
BMS 21/B4
R362 VDD OUT R349 47 1 2
4.7K RST3J E2 DSP_D[16:47]
4/B3,6/D4,10/C3,13/B3,17/B1,18/D2,20/C4,24/B3 RESET
L14 DSP_D16
2 D16 20/D1,20/C3
EN GND M13 DSP_D17
D17
1 2 DSP_CSJ N11 L15 DSP_D18
21/D1 CS D18
3.3V HBRJ R10 K13 DSP_D19
20/B3,21/D1 HBR D19
HBGJ R11 L13 DSP_D20
20/B3,21/D1 HBG D20
DSP_RDY P11 K14 DSP_D21 3.3V
C479 21/D1 REDY D21
1 K12 DSP_D22
0.01uF D22
K1 K15 DSP_D23
TIMEEXP D23
2 J13 DSP_D24
50V D24
J14 DSP_D25
D25
D0A E4 J12 DSP_D26
23/A3,23/C4,23/B4 D0A D26 C38 C399 C366 C70 C81 C397 C404 C282 C228
C5 J15 DSP_D27 1 1 1 1 1 1 1 1 1
D0B D27 0.1uF 0.01uF 0.01uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF
SCLK0 D5 H13 DSP_D28
23/A3,23/C4,23/B4 SCLK0 D28
FS0 B5 H12 DSP_D29 2 2 2 2 2 2 2 2 2
23/A3,23/C4,23/B4 FS0 D29 25V 10V 10V 25V 25V 10V 10V 10V 10V
H14 DSP_D30
D30 C63
D1A C6 H15 DSP_D31 1
22/B1 D1A D31 6.8uF
D6 G15 DSP_D32
D1B D32
SCLK1 B6 G14 DSP_D33
22/B1
22/B1
FS1 D7
SCLK1
FS1
ADSP21161J D33
D34
G12 DSP_D34
2
16V
G13 DSP_D35
D35 C362 C448 C359 C80 C388 C77 C384 C257 C245 C267 C270
D2A C7 F15 DSP_D36 1 1 1 1 1 1 1 1 1 1 1
24/C3 D2A D36 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.1uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF
D2B B7 F12 DSP_D37
24/C3 D2B D37
SCLK2 A7 F14 DSP_D38 2 2 2 2 2 2 2 2 2 2 2
24/C3 SCLK2 D38 10V 25V 10V 25V 10V 25V 10V 10V 25V 10V 10V
FS2 C8 E13 DSP_D39
21/C1,24/C3 FS2 D39
F13 DSP_D40
D40
B8 E15 DSP_D41
D3A D41
A8 D13 DSP_D42
D3B D42
D9 E14 DSP_D43
SCLK3 D43
FS3 C9 D15 DSP_D44
21/C1 FS3 D44
C14 DSP_D45
D45
D14 DSP_D46 1.8V
D46
C4 C15 DSP_D47
B A4
SPICLK
SPIDS
D47 B
B4
MOSI
D4 R8 DSP_RDJ
MISO RD 20/A4,20/B3,21/D1

DWG_NO
M9 DSP_WRJ
WR 20/B3,21/D1 C410 C408 C365 C403 C363 C400 C395 C379 C355 C381
1 1 1 1 1 1 1 1 1 1
0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF
DMAR1J N15
21/D1 DMAR1
DMAG1J M15 L12 CASJ 2 2 2 2 2 2 2 2 2 2
21/C1 DMAG1 CAS 20/B3 25V 25V 25V 10V 10V 25V 10V 10V 10V 10V
DMAR2J P15 M11 RASJ
21/D1 DMAR2 RAS 20/B3 C35
DMAG2J M14 R14 SDWEJ 1

757 044 11W

21/D1 DMAG2 SDWE 20/B3 6.8uF
P13 DQM
DQM 20/B3
H1 P10 R354 47 SDCLK0 2
FLAG0 SDCLK0 20/B3 16V

2
FLAG1 G1 P9 R352 47 SDCLK1
22/B2 FLAG1 SDCLK1 20/B3

2
FLAG2 G2 N10 SDCLKE
20/B3 FLAG2 SDCLKE 20/B3 C398 C356 C406 C378 C364 C402 C394 C383 C358 C387 C360
FLAG3 G4 M10 SDA10 1 1 1 1 1 1 1 1 1 1 1
20/B3 FLAG3 SDA10 20/B3 0.01uF 0.1uF 0.1uF 0.1uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
FLAG4 R368 47 G3
20/A3 FLAG4
1

FLAG5 R370 47 F1 2 2 2 2 2 2 2 2 2 2 2
20/A3 FLAG5 10V 25V 25V 25V 10V 10V 10V 10V 10V 10V 10V
1

FLAG6 R365 47 F4 E12

20/A3 FLAG6 L0DAT0
1

FLAG7 F2 B11
20/B3 FLAG7 L0DAT1
FLAG8 E3 A11
20/B3 FLAG8 L0DAT2
CLOCK MODES (DEFAULT IS 010) FLAG9 F3 D11
20/B3 FLAG9 L0DAT3
FLAG10 E1 A9
20/B3 FLAG10 L0DAT4
3.3V FLAG11 D3 D10
20/B3 FLAG11 L0DAT5
C10
L0DAT6
B9
L0DAT7
3.3V DSP_IRQ0J H2
20/A4,20/B3,21/C1 IRQ0 C393 C392 C391 C390 C389 C386
1 1 1 DSP_IRQ1J H4 B10 1 1 1 1 1 1
20/A4,20/B3,21/C1 IRQ1 L0CLK 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF 0.01uF
R383 R384 R355 DSP_IRQ2J J1 A10
20/A4,20/B3,21/C1 IRQ2 L0ACK
10K 10K 10K 2 2 2 2 2 2
10V 10V 10V 10V 10V 10V
1
2 2 2 R367 R6 B14
PA L1DAT0
R382 0 10K B3 C13
RBPA L1DAT1
A14
2 L1DAT2
1

C12
L1DAT3
CLK_CFG0 N13 B12
CLK_CFG0 L1DAT4
R385 0 CLK_CFG1 N12 D12
CLK_CFG1 L1DAT5
CLK_DBLJ R12 A12
CLKDBL L1DAT6
1

C11
L1DAT7
OPTION A6
LBOOT
EBOOT A5 A13
EBOOT L1CLK
R356 0 B13
A J4
ID0
L1ACK
A
1

J2 A1
ID1 NC1
J3 A15
ID2 NC2
B15
GND10
GND11
GND12
GND13
GND14
GND15
GND16
GND17
GND18
GND19
GND20
GND21
GND22
GND23
GND24
GND25
GND26

NC3
AGND

GND3
GND4
GND5
GND6

GND8
GND9
GND1
GND2

GND7

R1
NC4
NC5
R15 ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
G10

K10

9295 PROTOTYPE DRIVE RENO NV 89521

G8
G9

K6
K7
K8
K9
F10

H10
F8
F9

H6
H7
H8
H9

J6
J7
J8
J9
J10

C3
P14

G7
F6
F7

ADSP21161J
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
BOOT MODE IS HARDWIRED FOR BOOTING FROM EXTERNAL MEMORY OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
EBOOT = 1, LBOOT = 0, BMSJ = 1
WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 21 OF 24

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 21

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 22 OF 24
4 3 2 1

D D
13V
U7 5VAUDIO 5VAUDIO

1 3 U3 3.3V_AUDIO
IN OUT

GND
3
C16 C492 C14 C15 IN
1 1 1 1 2 4
6.8uF 0.1uF 6.8uF 6.8uF OUT1 OUT2
1

2
KA7805R C493 GND C1
2 2 2 2 1 1 1 C9
16V 5V 1A 25V 16V 16V 1uF 22uF
ADP3338 0.1uF
2 3.3V 2 2 25V
25V 35V
1A

OPTION

C C

C476
1 2

470pF

R465
1 2

6.81K
3.3V_AUDIO

5VAUDIO
3.3V_AUDIO
C470 C8
6.81K 1 1
U1 C7 0.1uF 1uF
C5 R462 R458 3.3V
10uF

8
AUX_L 2 1 1 2 2 150 2 2
14/D2 25V 25V
1 AIN_L
OPA2340

2
1 3 10uF 3
C198 C452
CR4 1 16V OPAMP 2 1 1
C460 0.1uF 1uF

4
1N914 R467 1 1 L16
0.01uF
1N914 100K R511 50 OHMS 3.3V 2 2
25V 25V
CR1 2 10K
3 1 2 50V
1
R459 2
REF_2.5V 1 2 OPTION

1
3.32K U5
22/B3,23/B2,23/D2,23/C2
21/B4 FLAG1 16

VCCA

VCCD
RST
5VAUDIO 15
VQ
C472
1 2 AIN_L14 2 AUDIO_MCLK1 21/C4
C471 AINL MCLK
1
B 0.1uF
470pF AIN_R13
AINR SCLK
3 SCLK1 21/B4 B
2
25V
R461 11 4 D1A 21/B4 TO AUDIO DSP SPORT 1
C457 C458 FILT+ SDATA

DWG_NO
1 2 1 1
0.1uF
10 7 FS1 21/B4

R_GND
1uF TST LRCK
6.81K 2 2

GND
25V 25V
9 8
DIF DIV
1
5VAUDIO R455

757 044 11W

25V

6
2 2 12 47K
1uF
6.81K
U1 C6 0.1uF 2
C2 R466 R457 1 1
10uF C456 C453
8

AUX_R 2 1 1 2 6 150 CS5333

14/D2 25V
OPAMP 7 AIN_R A/D CONVERTER
OPA2340

2
1 3 10uF 5
CR3 1 16V
C459
4

1N914 R468 1
0.01uF
1N914 100K
CR2 2
3 1 2 50V
REF_2.5V 1 2

R460 3.32K
22/B3,23/B2,23/D2,23/C2

OPTION

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

22 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 23 OF 24
4 3 2 1

Approx. 11.5V output

5VAUDIO
13V 12VAUDIO U8

U12 1 2 REF_2.5V

GND
IN OUT 22/B3,22/B3,23/B2,23/C2
2 4
IN OUT

1
3
C461 ADR381

C483
GND1
GND2
1 5

10V

1uF
1 1
SHDN ADJ C484 0.1uF 2.5V
R503 1 1
C485 0.1uF 120mA
8.45K

2
1 2
C500 10uF 0% 25V
LT1963 2 2

3
6
10uF 2 25V
1.5A
D 2
0V D

1
2
1
C502
1 R502
0.01uF
1K
10%
2
50V 2
HS_U12
HEATSINK

R474 5VAUDIO
4.75K R488
12VAUDIO 51K 12VAUDIO

2
5VAUDIO
C468
2 1 1 1
0.1uF C469 C488 C489
C494 L18 R481 1 1
1uF 0.1uF 1uF
2 1 2 50H 2 2 47K
25V 0%
L17 2.5A 2 2
25V 2 25V 25V
C464 1 1 C465 50 OHMS 470pF 1 R480
0.1UF 1 2
1UF
2 2 1
47K 12VAUDIO
R472 R473 R491
U2
910 4.75K 11.3K OPAMP R487

8
2 C495 20K U10 C12

6
1

2
1 1 3 AUDIO_L_P

VDD
DAC_PWR 1 2 1 2
23/B4 OPA2340 -VINA VOUTA 14/D2

2
2 3
C474 C477
1 1 0.47UF 2 470uF
0.0033uF 0.0033uF SHTDN

4
U103 R471 16V

9
25V
10K 2 2 16V R490 8

VA
25V BYPASS
D0A 1 DAC_OUTL 1 1% 20K C13

GND1
GND2
GND3
21/C4,23/A3,23/B4 SDIN 7
AOUTL 9 7 1 2 AUDIO_L_N
-VINB VOUTB 14/D2

2
SCLK0 2 LM4950 470uF

4
5
10
21/C4,23/A3,23/B4 DEM/SCLK
AMPLIFIER 16V
10 DAC_OUTR 1 1
AOUTR R496 R495
C 21/B4,23/A3,23/B4
FS0 3
LRCK
REF_2.5V 100K 100K C

2
5 2 2

2
VQ R478
22/B3,22/B3,23/B2,23/D2
AUDIO_MCLK2 4 1K R489
21/C4,23/B4 MCLK C518 C520 C497
1 1 1 20K
0.01UF 3.3UF C4 10uF
6 2 2 2

GND
FILT+ 50V 35V 16V

2
C503
1 R482
10UF 22uF 35V
4.75K 12VAUDIO R484
8

2 CS4344 51K 12VAUDIO

25V

2
OPTION D/A CONVERTER

2
1
R479
C3 C486 C487
C490 47K 1 1
0.1uF 1uF
1 2
2

2
R493 2 2
25V 25V
470pF 1 2
22uF 35V

CIRRUS LOGIC AUDIO DAC 47K

12VAUDIO
R470 R463 R464
U2
910 4.75K 11.3K OPAMP R483

8
6 C491 20K U9 C10

6
1

2
5VAUDIO 7 1 3 AUDIO_R_N

VDD
1 2 1 2
OPA2340 -VINA VOUTA 14/D2

2
2 5
C473 C475
DAC_PWR 1 1 0.47UF 2 470uF
23/C4 0.0033uF 0.0033uF SHTDN

4
R469 16V
25V
10K 2 2 16V R486 8
25V BYPASS
1 1% 20K C11

GND1
GND2
GND3
9 7 1 2 AUDIO_R_P
-VINB VOUTB 14/D2

2
U100
8

LM4950 470uF
VDD

4
5
10
2
FS0 1 AMPLIFIER 16V
21/B4,23/A3,23/C4 LRCIN
R524 D0A 2 11 1 1
21/C4,23/A3,23/C4 DIN NC2
10K SCLK0 3 9 DAC_OUTL R494 R492
21/C4,23/A3,23/C4 BCKIN VOUTL
1 RST5 10 6 DAC_OUTR 100K 100K
2/C4,12/B4,17/B1 MUTE VOUTR C496
12 5 REF_2.5V 1
DEEMPH CAP 10uF 2 2

2
13 4
FORMAT NC1
AUDIO_MCLK2 14 R477 R485
B SCKI 22/B3,22/B3,23/D2,23/C2
2
16V B
GND

1K 20K
21/C4,23/C4 C519
WM87XXGED/RV
7

1 1
22UF

DWG_NO
R520 ICSUBTYPE
2
16V
150
2

757 044 11W

WOLFSON AUDIO DAC
OPTION (WHEN USING DIGITAL AUDIO OUTPUT, WHICH IS NOT THE NORM).
EITHER DAC OPERATS AS A SLAVE AT 44.1KHz, I^2S MODE

5V AUDIO_CLKN
C168 14/D2
1
0.1uF
1
2 1 R374
25V
R375 120
3.3K 5V
2
2 AUDIO_CLKP
16

14/D2
U17
12
VCC

G
4 2 AUDIO_LRN
G 1Y 14/D2
SCLK0 1
A 21/C4,23/C4,23/B4 1A
1Z
3 1
A
6 R376
2Y
FS0 7 120
21/B4,23/C4,23/B4 2A
5
2Z 2
10
3Y
21/C4,23/C4,23/B4
D0A 9
3A
AUDIO_LRP
14/D2
ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE
3Z
11
ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
14 9295 PROTOTYPE DRIVE RENO NV 89521
4Y
15 AUDIO_DATAN INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R
GND

4A 14/D2
13
4Z
1
INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE
1 R373 COPIED, REPRODUCED, REVEALED TO OR APPROPRIATED BY PCB, GK ENHANCED, CTL A,
8

R372 AM26C31 120

OTHERS IN PART OR IN WHOLE, WITHOUT THE EXPRESS CONSENT
150
2 OF IGT. THIS PRINT IS LOANED AND RECIPIENT CONVENANTS IT
W/TT BAT, SCH
2 AUDIO_DATAP
14/D2 WILL NOT BE USED IN ANY MANNER DETRIMENTAL TO THE
DWG_SIZE DWG_NO REV_LTR
INTEREST OF IGT, AND MUST BE RETURNED ON DEMAND.
C 757 044 11W A
DRAWN DATE CHECKED DATE APPROVED DATE SCALE
KRK/GXM 3OCT05 RBP 21SEP06 TWG 21SEP06 NONE SHT 23 OF 24

4 3 2 1

MAY 4, 2007 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE 23

GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC 757 044 11W REV A PAGE 24 OF 24
4 3 2 1

J8
V2_D2N
D 24/D3
24/D3
V2_D2P
1
2 D
3
4
SD[0:31]
5
V2_DDC_CLK
2/D1,5/D4,6/C4,9/D4,10/C4,13/D4,20/C4 24/C3 6
V2_DDC_DATA
24/C3 7
V2_VSYNC
24/C3 8
V2_D1N
24/D3 9
V2_D1P
24/D3 10
5V 5V
11
polyfuse
12
RT1
13

tų
1 2
14
V2_D0P V2_D0N
24/D1 C30 D30 24/D1 15
V2_D1P 750MA HPD
A30 B30 24/D1 24/C3 16
V2_D0N
24/D3 17
V2_D2P V2_D0P
24/D1 C29 D29 24/D3 18
V2_D2N V2_D1N
24/D1 A29 B29 24/D1 19
20
V2_CLKP V2_CLKN
24/C1 C28 D28 24/C1 21
THESE GO BY THE DVI CONNECTOR
A28 B28 22
V2_CLKP
24/C3 23
V2_RED V2_CLKN
24/C2 C27 D27 24/C3 24
V2_GRN HPD L7
24/C2 A27 B27 24/D1
V2_RED 1 2 L6 V2_R
24/C3 C1
V2_BLUE V2_VSYNC V2_GRN 50 1 2 L8 V2_G
24/C2 C26 D26 24/D1 24/C3 C2
V2_HSYNC V2_BLUE 50 1 2 V2_B
A26 B26 24/C1 24/C3 C3
V2_HSYNC
50 24/C3 C4
V2_DDC_CLK
24/D1 C25 D25 C5
D2A SCLK2
21/B4 A25 B25 21/B4
1 1 1
C66 C64 C68
D2B FS2
21/B4 C24 D24 21/B4,21/C1 10pF 10pF 10pF
V2_DDC_DATA 2 2 2
A24 B24 24/D1 50V 50V 50V

C23 D23
OPTBD_CCLK OPTBD_CCLK2
3/C1,24/B2 A23 B23 3/C1,24/B2
OPTION
SRDJ SWR0J
4/C1,4/B2,5/D2,5/A3,10/C3,13/B3,18/C4,20/C4 C22 D22 4/C1,4/B2,5/B3,5/D2,13/B3,20/C4
BRDJ
A22 B22 2/B3,4/C1,4/B3,5/D4,5/C2,5/C1,5/A4,9/C3,9/B3

DTRJ
C 5/D4
2/B3,2/B2,2/B2,4/C1,4/B3,6/C4
BALEJ
C21 D21
A21 B21
BADSJ
2/A3,4/C1,4/B3,5/D4,6/C4 C
OPTBD_RDYJ SBE3J
4/A2 C20 D20 4/B2,9/B1,9/C1,13/C3
SBE2J
A20 B20 4/B2,9/B1,9/C1,13/C3
SBE1J
4/B2,9/B2,9/C2,13/C4 C19 D19
SBE0J
4/B2,9/B2,9/C2,13/C4 A19 B19
SD0 SD1 3.3V 5V 13V
C18 D18
SD2
A18 B18
SD3
C17 D17 C114 C115 C111 C109 C117
SD4 SD5 1 1 1 1 1
A17 B17 6.8uF 6.8uF 6.8uF 6.8uF 6.8uF
SD6 SD7 2 2 2 2 2
C16 D16 16V 16V 16V 16V 16V
SD8
A16 B16
SD9
C15 D15
SD10 SD11
A15 B15
SD12 SD13
C14 D14
SD14
A14 B14
SD15
C13 D13
SD16 SD17
A13 B13
SD18 SD19
C12 D12
SD20
A12 B12
SD21
C11 D11
SD22 SD23
A11 B11
MTG1 MTG2 MTG6
SD24 SD25
C10 D10
SD26 OPTION
A10 B10
SD27 OPTBD_CCLK2
C9 D9
SD28 SD29
A9 B9 C320
3/C1,24/C3 1
10pF MTG4 MTG5 MTG10
SD30 SD31
C8 D8
OPTBD1CSJ
B A8 B8 4/B2
2
50V B
OPTBD_HOLD
4/B3 C7 D7
OPTBD_HLDA OPTBD2CSJ
4/B3 A7 B7 4/B2

DWG_NO
MTG8 MTG9 MTG12
BLE0J
C6 D6
BLE1J
A6 B6
OPTION
C5 D5
RST3J

757 044 11W

A5 B5 4/B3,6/D4,10/C3,13/B3,17/B1,18/D2,20/C4,21/C4
OPTBD_CCLK
MTG11 MTG3 MTG7
BC2OPT[0:1] USB_P USB_N
14/D1 C4 D4 14/D1 C319
BLE2J 3/C1,24/C3 1
4/A2 A4 B4 10pF
BC2OPT0 2
C3 D3 50V
BC2OPT1 BLE3J
A3 B3
USB_1
14/D1 C2 D2
USB_2
A2 B2 14/D1

C1 D1
OPT_BDJ
4/B3 A1 B1
J9
3.3V
13V

BLE[0:3]J
2/B3,4/B4,5/D4,6/C4

A A

ALL DESIGN, OPERATIVE AND PROCESS DATA PERTAINING TO THE

ARTICLE SHOWN ON THIS SHEET IS THE PROPERTY OF INTERNATIONAL GAME TECHNOLOGY
9295 PROTOTYPE DRIVE RENO NV 89521
INTERNATIONAL GAME TECHNOLOGY, RENO, NEVADA. THIS R

INFORMATION IS DISCLOSED IN CONFIDENCE AND IS NOT TO BE TITLE

4 3 2 1

24 ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE MAY 4, 2007

MAY 4, 2007
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
1
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

2
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
MAY 4, 2007
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

MAY 4, 2007
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
3
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

4
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
MAY 4, 2007
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

MAY 4, 2007
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
5
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

6
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
MAY 4, 2007
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

MAY 4, 2007
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
7
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

8
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
MAY 4, 2007
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

MAY 4, 2007
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
9
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W
R

10
ELECTRONIC DIAGRAMS & PARTS: 960 TRIMLINE
MAY 4, 2007
GK ENHANCED CONTROLLER WITH TELLTALE BATTERY SCHEMATIC
757 044 11W

MK8 SVMOD 0002 - Peripherals
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IGT AVP User's Guide OS 1.4
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