0% found this document useful (0 votes)
14 views6 pages

Computer Architecture Exam Questions

This document appears to be an exam for a Computer Science course, covering topics related to computer architecture. It contains multiple choice and short answer questions assessing students' knowledge of topics like: registers and their purposes; control words; status bits; addressing modes; addition and multiplication algorithms; priority interrupts; main memory; vector processing; multi-processors; instruction cycles; stack organization; floating point arithmetic; asynchronous data transfer; associative memory; parallel processing; and pipelining. The exam is divided into three parts with a total of 75 marks possible.

Uploaded by

Raja Prathumnan
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
0% found this document useful (0 votes)
14 views6 pages

Computer Architecture Exam Questions

This document appears to be an exam for a Computer Science course, covering topics related to computer architecture. It contains multiple choice and short answer questions assessing students' knowledge of topics like: registers and their purposes; control words; status bits; addressing modes; addition and multiplication algorithms; priority interrupts; main memory; vector processing; multi-processors; instruction cycles; stack organization; floating point arithmetic; asynchronous data transfer; associative memory; parallel processing; and pipelining. The exam is divided into three parts with a total of 75 marks possible.

Uploaded by

Raja Prathumnan
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

(6 pages) Reg. No. : ........................................

Code No. : 41190 E Sub. Code : JACS 31/


JASE 31

[Link]. (CBCS) DEGREE EXAMINATION,


NOVEMBER 2018.

Third Semester

Computer Science — Allied

COMPUTER ARCHITECTURE

(For those who joined in July 2016 only)

Time : Three hours Maximum : 75 marks

PART A — (10  1 = 10 marks)

Answer ALL questions.


Choose the correct answer :

1. ————— holds the address of reset instruction.


(a) Stack pointer
(b) Input Register
(c) Accumulator
(d) Program counter
2. A memory that is part of control unit is referred to
as a —————.
(a) Control Memory (b) Data memory
(c) Main memory (d) Registers

3. In the multiplication process multiplier is stored


in —————.
(a) PC register (b) Shift Register
(c) Cache (d) Data Register

4. Generally, the subtraction is carried out by


(a) 1’s complement (b) 2’s complement
(c) 10’s complement (d) None

5. In which mode of effective address is equal to the


address part of the instruction.
(a) Implide mode
(b) Immediate mode
(c) Direct Address mode
(d) Indirect address mode

6. When A  B , the subtract magnitude for the


operation (  A )  (  B ) is —————.
(a)  ( A  B ) (b)  ( A  B )
(c)  (B  A) (d)  ( A  B )

Page 2 Code No. : 41190 E


7. A ————— command is used to test various
status conditions in the interface and the
peripheral.
(a) Control (b) Status
(c) I/O (d) None

8. Hand shaking is ————— type of data transfer.


(a) Synchronous
(b) Asynchronous
(c) DMA
(d) Interrupt

9. The virtual Memory basically stores the next


segment of data to be executed on the —————.
(a) RAM
(b) ROM
(c) Disks
(d) Secondary storage

10. Pipelining organization is applicable to ————.


(a) Instruction (b) Arithmetic
(c) Both (d) None

Page 3 Code No. : 41190 E


PART B — (5  5 = 25 marks)

Answer ALL questions, choosing either (a) or (b).

Each answer should not exceed 250 words.

11. (a) Draw the Block diagram of general Register


organization and explain its purposes.

Or
(b) Explain control word with examples.

12. (a) Explain the use of status bits register with


the block diagram.

Or
(b) Convert the following infix into prefix
notation:
(i) ( A  B )  (C  D )  E
(ii) A  B  C  (D  C)
(iii) ( A  B  C )  (C  D  E )
(iv) ( A  B )  (C  D )  ( E  D )
(v) (( A  B )  C  D )  ( E  D ) .

13. (a) Explain he Hardware implementation of


Addition Algorithm.

Or
(b) Explain the Hardware Algorithm for
Divisions?
Page 4 Code No. : 41190 E
[P.T.O.]
14. (a) What is priority Interrupt? Explain.
Or
(b) Explain about Main memory.

15. (a) What is Vector processing? Explain.


Or
(b) Discuss about Multi processors.

PART C — (5  8 = 40 marks)
Answer ALL questions, choosing either (a) or (b).
Each answer should not exceed 600 words.

16. (a) Explain about computer Instruction.


Or
(b) Explain the process of Instruction cycle.

17. (a) Explain stack organization in detail.


Or
(b) What is Addressing Mode? Explain the
various types.

18. (a) Explain Booth multiplication Algorithm with


an example.
Or
(b) Explain Addition and Subtraction of floating
point numbers with its register
configurations.
Page 5 Code No. : 41190 E
19. (a) What do you understands about
Asynchronous Data transfer? Explain in
detail.

Or
(b) Explain about Associative Memory.

20. (a) Explain parallel processing.

Or
(b) Write about Pipe Lining.

———————

Page 6 Code No. : 41190 E

Common questions

Powered by AI

Associative memory, also known as content-addressable memory, allows data retrieval based on content rather than specific address location, enabling faster retrieval times in certain applications. Traditional memory, however, requires data to be accessed by specific addresses, relying on sequential or direct memory location accesses .

Handshaking in asynchronous data transfer is significant because it ensures data is sent only when both the sender and receiver are ready. This handshake involves a series of signal exchanges to confirm readiness, optimize data integrity, and avoid data collision during transmission .

Two's complement is used for subtraction by effectively reversing the number you want to subtract and adding it using normal binary addition. This involves inverting the bits of the subtrahend and adding one, making the arithmetic uniform for both addition and subtraction in the system without the need for a dedicated subtraction unit .

Pipelining enhances execution efficiency by breaking down instruction processing into separate stages, allowing different instructions to be processed concurrently at various pipeline stages. This increases throughput by reducing the idle times typically inherent in non-pipelined processor designs .

Status bits in a register, often stored in a status register, are used to indicate the outcome of operations or specific conditions of the CPU. They can denote flags like overflow, carry, zero, and negative conditions which are critical for decision-making processes in executing further instructions .

The main purpose of a program counter is to hold the address of the next instruction that needs to be executed. This ensures that the processor knows where to continue reading instructions from in a sequential manner .

Control memory, as part of the control unit, is used to store the microprogram that defines the processing sequence of micro-operations in a CPU. In contrast, data memory is generally part of main memory used to store data variables and intermediate results during program execution .

Virtual memory allows systems to use hard disk space as an extension of RAM, effectively enabling the execution of processes larger than physical memory. This abstraction allows for more efficient multitasking and process management but can impact performance negatively through increased access times and page swapping, which needs to be managed to minimize thrashing .

Booth's multiplication algorithm is a method for multiplying binary numbers that reduces the number of addition operations by encoding the multiplier in a form that allows for efficient bypassing of strings of zeros. It is advantageous because it can handle both positive and negative multipliers uniformly and is more efficient for numbers with several consecutive zero or one bits .

In direct addressing mode, the effective address is specified within the instruction, meaning it directly points to the memory location where data is located. In immediate addressing mode, the operand itself is part of the instruction, not requiring any additional memory lookup, making data access faster though limited in operand size .

You might also like