CS-212 Computer Organization & Design
Buses
A bus is a shared set of wires used to interconnect two or more devices or subsystems. The term bus is a contraction of the
Latin word omnibus meaning for all. The reason for this terminology is that it behaves like a highway that can be used by
lots of different traffic. In a computer, all the devices that wish to communicate with each other use a bus.
Advantages of Buses
+ Versatility
New devices can be added easily.
Peripheral devices can be moved between computer systems that use the same bus standard.
+ Low Cost
A single set of wires is shared in multiple ways.
Disadvantage of Buses
– The major disadvantage of a bus is that it creates a communication bottleneck limiting throughput as only one
device can put its data on the bus at a time.
Bus Speed
The maximum bus speed is largely limited by the following factors:
length of the bus
number of devices on the bus
need to support a range of devices with widely varying latencies and data transfer rates
The General Organization of a Bus
A bus comprises:
1. Data Lines (Data Bus)
They carry actual data. The number of data lines determines (data) bus width and hence, affects data transmission rate
(i.e. bus bandwidth).
2. Address Lines (Address Bus)
Address bus carries address of source or destination of data on data bus. It determines the maximum memory capacity
of a system.
3. Control Lines (Control Bus)
̅
Control bus is used to control access to and use of data and address buses, e.g. 𝑅/𝑊
Multiplexed Address-Data Bus
A set of lines may be used as both data and address bus at different times. This is called time-multiplexed or simply
multiplexed bus. However, a control signal is required to identify data or address on multiplexed bus.
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CS-212 Computer Organization & Design
A Bus Transaction
A bus transaction consists of three steps:
a) Gaining access to the bus – becoming bus master
b) Issuing the command (and address) – request
c) Transferring the data – action
In the simplest system, processor is the only bus master. In such a case, the major drawback is that the processor must be
involved in every bus transaction.
Bus Arbitration
At any given instant, only one device can be bus master. If more than one device wants to become bus master at the same
time, there must be a mechanism to resolve or arbitrate this conflict of choosing next bus master. This mechanism of
choosing the next bus master is called bus arbitration. The hardware that makes this decision is known as bus arbiter.
Bus Arbitration Scheme
This generally consists of following three steps:
The potential master requests the arbiter
The arbiter grants use of bus
The master informs the arbiter about release of bus
Bus Arbitration strategies can be broadly classified as follows:
1. Centralized Schemes
In a centralized scheme, a single hardware device, referred to as a bus controller or arbiter, is responsible for allocating
time on the bus. The device may be a separate module or part of the processor.
2. Distributed Arbitration
In a distributed scheme, there is no central controller. Rather, each module contains access control logic and the modules
act together to share the bus.
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CS-212 Computer Organization & Design
Types of Buses
1. Processor-Memory Bus
This interconnects processor and memory.
It's design-specific or proprietary.
It's a shorter (a few inches long) bus, hence has the highest bandwidth and lowest latency.
It contains parallel lines.
It follows synchronous timings.
2. I/O Bus (Industry Standard)
This bus connects various peripherals to the system.
These are longer (as they need to be) and hence slower (high latency and low bandwidth).
They must handle wide range of device latency, bandwidth and characteristics.
An I/O bus usually connects to processor-memory or backplane bus.
These are usually serial buses (preferred nowadays).
It follows asynchronous timings.
Examples are SCSI (small computer system interface), SAS (serially attached SCSI), USB (universal serial bus),
etc.
3. Backplane Bus (Industry Standard)
This bus receives its name as it lies in the back of the chassis structure (motherboard) of the system.
These are usually serial buses (preferred nowadays).
It follows asynchronous timings.
Peripheral Component Interconnect Express (PCI-e) is a widely used backplane bus.
Bus Configuration - Three-Bus System
Processor-Memory Bus
Processor Memory
Bus
Adapter
Bus Adapter
Backplane Bus I/O Bus
Bus Adapter
A backplane bus taps via bus adapter, into the processor-memory bus. Processor-memory bus is only used for
processor-memory traffic. I/O buses are connected to the backplane bus via bus adapters. It has the advantage that
loading on the processor-memory bus is greatly reduced.
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