3D IC Technology – OSAT Perspective
Min Yoo in Amkor Technology Taiwan
Status Update: Amkor’s
2.5D and 3D TSV Development
Agenda
• Drivers & Timing
• Key Product Development Activity
• Production Challenges
Amkor TSV Platform Roadmap
“Drivers and Timing”
FCBGA – Migration to TSV
New !!
Logic 1 Logic
Cache Cache
Analog 1 Multi-Die
Traditional Logic 2
SOC Logic 1 Interposer
Logic SOC
Analog
Logic 1 Logic 2 2
Monolithic Logic Logic Multi-Die
FPGA Logic Interposer
SOC
Logic Logic SOC
• Die-to-die connections at on-chip speeds and power.
• Allows multiple process nodes in a single silicon package.
• Only use 28nm for functions that need it.
• Partition large logic blocks into smaller, higher yield sub-blocks.
– Much lower cost 28nm products
– Less sensitivity to 28nm process issues
TSV Production Intercepts
– Amkor View
Si InterpT + DDRT + Logic
Interposer Required
GPU, CPU
Apps ProcessorT + DDR
Smart Phone / Tablet
MEMsT
Mobile Devices
Memory (DDRT)
Server, Wide I/O
Si InterposerT + Logic
Interp. Req’d
ASIC, FPGA
Logic – Backside Metal Production
Power Amp. Since 2010
Die with SV indicated by = T 2011 2012 2013 2014 2015
All Products planning on 22/20nm in future platforms for TSV
Key TSV Product &
Development Activity
TSV Bearing Wafer Supply Chain
Logistics
TSV Product Challenges
Micro Copper
Thermal Pillar Bumping
Micro Joining
Silicon
Interposer
Substrate
Interposer Thinning Underfill
Thin Wafer
Handling Subassembly
&
Package
Warpage
Amkor Capability
2.5D FPGA Module
µBumping of TSV Devices
• Formation of Back-side / Front-side µBumps
– All development and qualifications at 40µm pitch today
– 30µm pitch demonstrated
– 20µm pitch requires development (registration) & new photoresist (resolution)
Wafer Finishing of TSV Devices
• 200/300mm Thin Wafer Support in ATK4
– Cleared to bond up to 40um front side bumps ; excellent TTV at ~2µm
Wafer Finishing of TSV Devices
• TSV Reveal, Isolation and Passivation
– Key : No damage to silicon, liner or tip
– Critical : No copper residue on surface
Grind – Expose TSV
Silicon Etch Recess
Ni – Au on Copper Via
Completed TSV Backside
Structure
SiN
TEOS
Oxide liner
Wafer Finishing of TSV Devices
• 200/300mm Thin Wafer Handling – De-bonding
Assembly (BEOL)
Joint technology
• Compression technology primarily used with TSV pitches ~ 40µm
• Mass reflow begins to reach limit at 40µm pitch due to shorting potential
• Warpage of substrate under mass reflow limits ability to reduce TSV pitch
Bump Pitch 50um 40um 30um 20um
Bonding Reflow Reflow/ Compression Compression
Method Compression
Bump Solder Cu-Solder Cu-Solder Cu-Solder
Structure
2010 2011 2012 2013
Process Chip to Substrate ( Organic / Si interposer)
Chip to Chip Chip to Wafer
Substrate + Logic + Memory
Interposer Only
Wide I/O MPGA
APU
80µm
BumpCross Section of Memory on Logic
Good Registration
• Thermo-Compression Bond + Non Conductive Paste (NCP)
– Thin die handling capability to 50µm
– Material dispense critical
Chip
Pitch ≥ 40µm today ; 30µm 2012 Cu Pillar with SnAg µBumps
Pillar to Ni-Au Pad as standard 40µm today
Courtesy of Xilinx, TSMC, Amkor
Assembly of TSV Devices
• Assembly Experience on Silicon Interposer
• Substrate body size ranges from 35mm up to 55mm
• Interposer thickness as thin as 60um, but typically at100um
Chi
p
Chi
p
Pitch ≥ 40µm today ; 30µm 2012 80µm Tall Plated SnAg or SnPb Bumps
Pitch ≥ 150µm today ; ≥ 130µm 2012
Many Assembly Flows – Requires
Flexibility
Many Options – Amkor Engaged in Each
Chip on Substrate Chip on Wafer Chip on Chip
“Co-CoS” “CoW-oS” “CoC-oS”
TSV Reliability Data – General
• ASIC (die to die = face to face)
• Multiple Die on Interposer ; 100µm thick, 10µm TSV at 210µm pitch
• Logic at 40µm pitch µbump with 25µm dia. ; over 200k micro-bumps
• Passed Level 4 MRT ; TC Condition B 1000 cycles ; HTS 1000 hrs and
HAST 110C, 85% RH, 500 Hours
• Handset – 45nm Baseband (die to die = face to back)
• Memory ~ 100µm thick
• Logic ~ 50µm thick with 10µm TSV at 40um pitch ; either peripheral or area
array bump pitch to substrate
• Passed MRT L3 260’C (3x reflow) ; T/C-B 1000 cycles ; HTS 1000 hrs
TSV Lessons Learned
• Design Rules and Standards
• Simulation, Thermal, Mechanical, Tolerance
• Test and FA Methods
• Adaptive assembly methods
• Feed forward product characteristics
Design Rules and Standards
• Successful deployment of 2.5D and 3D
TSV requires careful definition of design rules.
• International standards will help reduce
variability and complexity.
Simulation
• Complexity forces computational solutions for
predicting performance and yield.
• Better specification of material properties
is needed.
Adaptive Assembly Methods
• For greater process latitude, process
equipment must adapt to the measured
characteristics of incoming material.
– For example:
• Warpage
• Planarity
• TTV
TSV Must Succeed or We Face
This:
