1

STATCOM as a Solution to Improve the

Voltage Profile of a Power Grid
(Master Thesis Extended Abstract)

Yasin Ahmad
Department of Electrical and Computer Engineering
Instituto Superior Técnico – Technical University of Lisbon, Portugal
Email: [Link]@[Link]

scientific field, and is slowly starting to pressure governments

Abstract— The aim of this dissertation is to propose and to turn to renewable energy systems as a means of replacing old
evaluate a power electronics based system, using reactive shunt and cheap energy productions methods that produce a
compensation to guarantee a better voltage profile at the MV/HV significant amount of greenhouse gas, are starting to create
grid, thus allowing a better use of the line capacities. balancing issues in the delivery systems.
An H-bridge Static Synchronous Compensator (STATCOM) is
Imbalances in the voltage profile along the electric network
developed using a star configured Cascaded Multilevel Converter
(CMC). The system is designed for a 𝟏𝟎 𝐤𝐕 application, with seven are one of the biggest challenges for system operators.
modules and a Phase-Shifted Pulse Width Modulation (PS-PWM) Therefore if the voltage and reactive power are not controlled,
strategy, in which a phase shift of the carrier waveforms is used in then the difference in voltage between the generation source
order to obtain the desired AC output voltage from the converters. and the load can lead to voltage instabilities or even voltage
PI controllers are used for the grid side currents and voltages and collapse.
a voltage balancing technique for the DC capacitors is also A solution using Flexible AC Transmission Systems
designed to guarantee that the voltages in the DC link do not (FACTS) can overcome some of these issues. This solution is
diverge significantly. extremely important in overcoming limitations in the static and
The developed system is tested, using an equivalent model of a
dynamic transmission capabilities of electrical networks.
MV line. Several simulation scenarios are tested and the obtained
results show that the proposed system allows for the regulation of The aim of this dissertation is to propose and evaluate a
reactive power injected/consumed in the network, guaranteeing power electronics based system that is able to guarantee a stable
the regulation of the voltage at the point of common coupling voltage profile in the HV/MV grid for the transmissible power
(PCC). along the power lines to be increased, using reactive shunt
compensation, allowing for system operators to have a better
Index Terms— Flexible Alternating Current Transmission use of line capacity without needing to build new lines, and new
Systems (FACTS), Static Synchronous Compensator generation sources which are a costly endeavour and represent
(STATCOM), Cascaded Multilevel Converter (CMC), Phase a mid to long term strategy. It is important to acknowledge that
Shifted Pulse Width Modulation (PS-PMW). the use of FACTS will not solve all the existing problems,
which means that although extending the lines capacity can
I. INTRODUCTION bring benefits, sometimes it is necessary to build new lines or

S ince the introduction of electrical energy in the 19 th

century, there have been significant technological
developments and the modern day electric power systems have
upgrade current and voltage capabilities of existing lines and
corridors. What FACTS system can provide is an alternative to
some of these problems.
been built. These systems have grown in complexity and The present paper is organized as follows: Section II: The
nowadays are constituted by a vast network of transmission designed H-bridge STATCOM is explained. Section III:
interconnections, multiple types of generation resources and Controllers design. Section IV: The PS-PWM strategy and the
loads. Due to these technological advancements and many other balancing technique for the CMC are described. Section V: In
scientific achievements, in the last century the quality of life for this section the simulation results for the constructed H-bridge
most people has increased significantly. However, the rapid STATCOM in the Simulink environment are presented. Section
growth of the population, the development of industry, the VI: This section summarizes all the achieved results.
increase of generation sources at the load and the networks
underlying unpredictability, are starting to strain the power II. MODEL
generation systems. This means that the added load demands, A STATCOM using a Cascade Multilevel Converter (CMC)
growth of interconnections, economic restrictions, and factors with a star configuration, is designed in this paper. The H-
such as global warming, that is a leading concern in the
 2

bridge STATCOM has been receiving increased attention in By utilising a CMC topology the voltage output, number of
recent years, as well as being implemented in various markets, levels and number of operation modes can be expressed by
[1]. This sort of configurations allows for the control of the (II.1), where 𝑁 stands for the number of modules in use.
reactive power in the system, attenuation of voltage flicker, From the analysis of Fig. 2 the STATCOM state space
regulation of voltage in distribution lines among others. equations (II.2) are obtained, where 𝑉𝑃𝐶𝐶𝑎.𝑏.𝑐 represents the grid
Another advantage in a cascaded H-bridge STATCOM results voltages at the PCC, 𝑉0𝑎,𝑏,𝑐 is the three-phase output voltage
from the use of CMC, which offers the system added from the CMC, and 𝑖𝑎,𝑏,𝑐 is the three-phase balanced current
modularity and an increased number of levels for the voltage
flowing from the STATCOM.
output, this will allow for a generated output voltage with less 𝑑𝑖𝑎
harmonics. Another advantage from using this configuration is 𝑉𝑃𝐶𝐶𝑎 = 𝐿 + 𝑅𝑖𝑎 + 𝑉𝑜,𝑎
𝑑𝑡
direct connection to the grid without the need of a bulky step-
𝑑𝑖𝑏
up transformer, thanks to each converter being connected to a 𝑉𝑃𝐶𝐶𝑏 = 𝐿 + 𝑅𝑖𝑏 + 𝑉𝑜,𝑏
galvanic isolated DC capacitor, [1], reducing the weight added 𝑑𝑡
𝑑𝑖𝑐
{ 𝑉𝑃𝐶𝐶𝑐 = 𝐿 𝑑𝑡 + 𝑅𝑖𝑐 + 𝑉𝑜,𝑐
to the system by the transformer and also removing its costs and (II.2)
reducing losses.
Using the Clarke and Park transformations the system is
Fig. 1 illustrates the system being implemented in this paper.
represented in a 𝑑𝑞 coordinate synchronous reference, equation
At the point of common coupling (PCC) where the connection
(II.3). In this equation, 𝜔𝐿𝑖𝑑 and 𝜔𝐿𝑖𝑞 represent the cross
between the system and the STATCOM takes place a reactor is
coupling terms.
required, which serves as a current smother to attenuate the high
𝑑𝑖𝑑
frequency current harmonics that the STATCOM generates, 𝑉𝑃𝐶𝐶𝑑 = 𝑅𝑖𝑑 + 𝐿 − 𝜔𝐿𝑖𝑞 + 𝑉𝑜,𝑑
[2]. { 𝑑𝑡
𝑑𝑖𝑞
𝑉𝑃𝐶𝐶𝑞 = 𝑅𝑖𝑞 + 𝐿 + 𝜔𝐿𝑖𝑑 + 𝑉𝑜,𝑞 (II.3)
𝑑𝑡

Fig. 2 – Simple representation of the system in study

Under balanced conditions, the coordinates of the voltage
and current vectors in the synchronous reference frame are
constant quantities. This feature is useful for analysis for
decoupled control of the two current components, [3], [4] , [5].
The power decoupling control, allows for separate active and
Fig. 1 – Model of an H-bridge STATCOM reactive power control. With this information at hand the
controllers needed can be designed using a decoupled
A. Converter
methodology. Which allows for reactive power to be controlled
The proposed H-bridge STATCOM uses a modular solution by adjusting 𝐼𝑞 and for active power to be controlled adjusting
which results from the application of 𝑛 single phase converters 𝐼𝑑 . The active power in the STATCOM serves to compensate
in series, per phase, connected in a star configuration. the voltages in the DC capacitors.
The single phase converter is comprised of two arms, each 𝑃 = 𝑉𝑑 𝐼𝑑
with two semiconductors with turn OFF capability, with two {𝑄 = −𝑉 𝐼 (II.4)
𝑑 𝑞
freewheeling diodes connected in anti-parallel. The The modularity that is introduced with a cascaded multilevel
semiconductors with turn OFF capability can be either IGBTs, topology is a great advantage, as it will provide the system with
MOSFETs and GTOs, [3]. added flexibility. As a result, when a module is damaged during
𝑛
the course of the STATCOM operation time, if the converters
𝑉𝐷𝐶 𝑜 = ∑ 𝑉𝑖 are correctly sized, and therefore there are extra modules, than
𝑖=1 (II.1) the STATCOM can continue to operate normally, by simply
𝐿𝑒𝑣𝑒𝑙𝑠 = 2𝑁 + 1
bypassing the faulty modules. This will allow a faulty module
𝑁𝑐 = 2𝑁+1 − 1 .
to be removed without affecting the overall functioning of the
 3

STATCOM. from (II.11), where 𝑃𝑑 is the dissipated power.

The developed system is sized for a 10 𝑘𝑉 application. 𝑃𝑑
𝑟𝐿 = = 5 𝑚Ω
𝐼𝑐𝑚𝑎𝑥 2 (II.11)
Va
C. Sizing of the DC capacitors
r L Vb
STATCOM The design of the DC capacitors starts with studying the
r L Vc
relation of the DC voltage and the AC voltage. Also, the
r L capacitors should be able to supply power for a certain duration
Fig. 3 – Model of a H-bridge STATCOM without discharging bellow an established value that would
compromise the normal operation of the converter. Another
The number of modules in use by the developed system,
factor that needs to be taken into account is that a voltage fault
needs to guarantee that the voltage on the DC side is higher than
consists in an abrupt loss of voltage that can go from ninety to
the voltage in the AC side, to ensure that the VSC converters
five percent of the nominal value for a duration that can last
work adequately. The minimum number of modules, N, that the
from a few milliseconds to a minute [6]. Interruptions have
system needs can be approximately calculated from equation
three classifications: momentary (few 𝑚𝑠 to 3 seconds),
(II.5), where 𝑉𝐷𝐶𝑛 is the voltage of a single DC capacitor:
temporary (lasting 3 seconds to 1 minute) and sustained (lasting
√2𝑉𝑆𝑝ℎ more than 1 minute), [7].
√3 1
𝑁> 𝑊𝑐 = 𝐶𝑉 2 (II.12)
𝑉𝐷𝐶 𝑛 (II.5) 2
2𝑃∆𝑡
From the analysis of Fig. 3, the single phase voltages are: 𝐶= = 0.1516 𝐹
2 1 𝑉𝑖𝑛𝑖𝑡𝑖𝑎𝑙 2 − 𝑉𝑓𝑖𝑛𝑎𝑙 2 (II.13)
𝑉𝐴𝑁 = 𝑉𝐴𝐵 + 𝑉𝐵𝐶
3 3 Using equation (II.13) the capacitance of the DC converters
2 1 can be obtained. To create a STATCOM model as close as
𝑉𝐵𝑁 = 𝑉𝐵𝐶 + 𝑉𝐴𝐶
3 3 possible to reality, each capacitor will be considered to have a
2 1 slight deviation from the calculated value from (II.13).
{𝑉𝐶𝑁 = 3 𝑉𝐶𝐴 + 3 𝑉𝐴𝐵 (II.6)
D. Semiconductors
With 𝑉𝐴𝑁𝑅𝑀𝑆𝑚𝑎𝑥 is defined as:
𝑉𝐷𝐶𝑜 In this work the chosen semiconductors are Insulated Gate
𝑉𝐴𝑁𝑅𝑀𝑆𝑚𝑎𝑥 ≈ (II.7) Bipolar Transistor (IGBT), [8], which are usually preferred for
√2 applications with low duty cycle, low frequency (<20kHz), high
To guarantee the adequate operation of the converter the
voltage and current applications, high output powered demands.
value of 𝑉𝐴𝐵𝑅𝑀𝑆𝑚𝑎𝑥 , represented in (II.8), should be higher than
It should be noted that when choosing an IGBT the highest
the output voltage of the converter, (II.9), where 𝑖𝑚𝑎𝑥 is the voltage the IGBT should block, should be no higher than eighty
maximum current that is supplied by the STATCOM. percent of the 𝑉𝐶𝐸𝑆 rating, amongst other more technical
𝑉𝐴𝐵𝑅𝑀𝑆𝑚𝑎𝑥 = √3𝑉𝐴𝑁𝑅𝑀𝑆𝑚𝑎𝑥 (II.8)
reasons.
2 In the present work the voltage per DC capacitor is:
√2𝑉𝑆𝑝ℎ 11.7
𝑉𝐷𝐶 𝑜 => √( ) + (𝜔0 𝐿 𝑖𝑚𝑎𝑥 )2 𝑉𝐷𝐶𝑛 = 𝑘𝑉 = 1.671 𝑘𝑉
𝑚𝑎𝑥
√3 (II.9)
7
(II.14)
The number of modules that will be used in the simulation in To guarantee the safety margin the semiconductor should be
this dissertation is 7, with a total DC voltage capacity of sized to be able to block a voltage of:
11.7 𝑘𝑉, that is, 1.671 𝑘𝑉 in each capacitor, which will 𝑉𝐶𝐸𝑆 = 2500 𝑉 (II.15)
guarantee the correct operation of the converter and its Which guarantees a safety margin of 50%.
modularity. The maximum value of the RMS current in the
B. Sizing of the filtering inductors in the connection to the semiconductors is:
𝑖𝑎𝑐 350
grid 𝑖𝑟𝑚𝑠 = = = 247.49 𝐴 (II.16)
In a converter with a high number of modules, when √2 √2
To determine the average value of the current it is necessary
compared to other topologies, a connection filter with a lower
to use the relation between the power of the DC side and AC
value can be used, as the harmonic contents decrease for higher
side. Therefore, from equation (III.8) the DC current 𝑖𝐷𝐶 in the
number of levels.
capacitors can be obtained, and then the average value of the
To calculate the filter, equation (II.10) is used where 𝑉𝐷𝐶 𝑘
current in each semiconductor can be calculated using from
represents the output voltage of one module, 𝑓𝐶 is the switching (II.17).
frequency, and ∆𝐼𝐿𝑚𝑎𝑥 is maximum ripple of the current. 𝑖𝑑𝑐
𝑉𝐷𝐶 𝑘 𝑇𝐶 𝑖𝑎𝑣 = = 63.45 𝐴 (II.17)
𝐿= = 13𝑚𝐻 2
2. ∆𝐼𝐿𝑚𝑎𝑥 (II.10)
The IGBT used in this work should be able to block a voltage
The internal resistance of the inductor 𝑟𝐿 can be estimated of 2.5 𝑘𝑉 and a maximum current of 400 A.
 4

III. CONTROLLERS DESIGN 𝑉𝐷𝐶𝑜𝑚𝑎𝑥

𝐾𝐷 =
A. Control Method 𝑉𝑝 (III.3)
The delay used in this sort of endeavours can be a value
The proposed feedback decoupled control scheme is
presented in Fig. 4. For both the voltage and current loop, belonging to the interval [0, 𝑇𝑐 ], therefore it will be defined to
Proportional-Integral (PI) controllers are designed, with its be half of the commutation time.
𝑇𝑐
components defined in rotating synchronous coordinates 𝑑𝑞, 𝑇𝑑 = (III.4)
[3], [4], [9]. The use of PI compensators is a common choice, 2
Solving the closed loop system present in Fig. 5 will yield
as they guarantee fast responses times and zero tracking error
(III.5), which is then solved as a second order system to obtain
to the step response.
the values of 𝐾𝑝 and 𝐾𝑖 in (III.6).
The proposed control scheme uses four PI compensators and
𝐾𝐷
the coordinates transformations described in the previous
𝑖 𝑇𝑝 𝑇𝑑 𝑅
chapter, will be an integral part of the controllers designed in 𝐻(𝑠) = =
this dissertation. The PI compensator that allows for the DC 𝑖𝑟𝑒𝑓 𝑠 2 + 𝑠 + 𝐾𝐷
𝑇𝑑 𝑇𝑝 𝑇𝑑 𝑅 (III.5)
capacitors to be balanced controls the active power that results
𝐿 𝑇𝑧
from the power losses in each converter. The output of this PI 𝑇𝑧 = 𝐾𝑝 = = 0.0056
compensator is the current reference for the grid 𝑖𝑑 current. 𝑅 𝑇𝑝
{ ⇒
The PI controller that outputs the reactive current reference 2𝑇𝑑 𝐾𝐷 1
𝑇𝑝 = 𝐾𝑖 = = 53.420
uses the information of the 𝑑 component voltage at the PCC in 𝑅 { 𝑇𝑝 (III.6)
order to determine the necessary reactive compensation to keep
a stable voltage profile along the line. In the current control Compensator Conversor

stage, the reference voltages for the modulating wave are

obtained, which are then used for the gating signals.

Fig. 5 - Current Control

C. Voltage Control loop

The outer control loop, otherwise known as voltage
controller, is designed as a PI controller, this controller will
have a slower time than the current controller.
The relation between the current the flows from the
STATCOM and the voltage of the converter is obtained from:
Fig. 4 - Control Scheme 𝑑𝑣𝐷𝐶 𝑇𝐿 1
𝑖𝑐 = 𝐶 ⇒ 𝑖𝑐 = 𝑠𝐶𝑣𝐷𝐶 ⇔ 𝑣𝐷𝐶 = 𝑖
𝑑𝑡 𝑠𝐶 𝑐 (III.7)
B. Current Control loop The relation between the DC capacitors charging/discharging
The inner control loop, otherwise known as the current current and the current that flows out in the AC side. This can
controller, is designed as a PI controller, so that a fast response be done using the relationship between the input/output power
and a zero steady-state error to step response can be obtained. (III.8).
From Fig. 2 the following equations are obtained: 𝑃𝐷𝐶 = 𝑃𝐴𝐶 ⇔ 𝑉𝐷𝐶 𝑖𝐷𝐶 = 3𝑉𝑒𝑓 𝐼𝑒𝑓 (III.8)
𝑉𝐷𝐶𝑜,𝑎 − 𝑉𝑎𝑁
𝑖𝑎 = With the following relationship of the Power at the AC side
𝑅 + 𝑠𝐿 and DC side the voltage control loop can be built, as illustrated
𝑉𝐷𝐶𝑜,𝑏 − 𝑉𝑏𝑁 in Fig. 6.
𝑖𝑏 =
𝑅 + 𝑠𝐿 The gain K, represents the coefficient between the DC and
𝑉𝐷𝐶𝑜,𝑐 − 𝑉𝑐𝑁 AC side of the converter.
{ 𝑖𝑐 = 𝑅 + 𝑠𝐿 (III.1)
𝑖𝐷𝐶 3𝑉𝑒𝑓
The compensator and the converter will be described as 𝐾= =
𝐼𝑒𝑓 𝑉𝐷𝐶 (III.9)
follows:
𝐾𝑖 𝑠𝑇𝑧 + 1
𝐶(𝑠) = 𝐾𝑝 + =
𝑠 𝑠𝑇𝑝
𝐾𝐷
𝐺(𝑠) ≈
1 + 𝑠𝑇𝑑 (III.2)
The gain 𝐾𝐷 is obtained from the ratio between the voltage
in the DC side and the maximum voltage of the carrier wave:
 5

capacitors.
Compensator Converter When implementing a PS-PWM technique, it is necessary to
create a phase difference in the triangular carrier waves. This
means each phase will receive the modulation waveforms from
the controller, but in each module of the system, there will be a
phase difference in the triangular carrier waveforms in order to
Fig. 6 - Voltage Control Loop
correctly send the signals to the gates, which will allow for the
correct operation of the CMC and will produce the maximum
From Fig. 6, the voltage response of the system to the load number of levels in the output.
can be acquired, which is presented in (III.10). The developed system is operated at 𝑓𝑐 = 5 𝑘𝐻𝑧 and the
number of modules in each phase is 𝑁 = 7. Therefore, the
phase shift of the triangular carrier waveforms will be given by
(IV.1), that is: they will be shifted 𝜑𝑝𝑠 , where 𝑛 represents the
 v Ki K index of the module.
( sTz  1) 𝑇𝑐
VDC CTd 𝜑𝑝𝑠 = 𝑛
 𝑁
(IV.1)
VDC ,ref s2
s K K  K K
s3   v p  v i B. Capacitors Voltage Balancing
Td CTd CTd (III.10)
The implementation of a PS-PWM technique, provides the
The next step consists in taking into account the final value system with a reasonable control over the voltage profile of the
theorem (III.11). DC capacitors, but due to the existence of losses from the
VDC systems components which aren’t equal for all the converters
𝑙𝑖𝑚𝑠→0 =1 allied with the fact that the control method implemented with
VDC ,ref (III.11)
PS-PWM is made taking into account the average value of the
In order to calculate the PI controller parameters, the various capacitors and that these capacitors aren’t all used in the
denominator of equation (III.11), in canonical form, must be same fashion [7], there will be a divergent behaviour of the
compared to the third order polynomial present in equation various voltages when the need to transfer power occurs. It
(III.12), [6]. becomes necessary to implement a second system, with a
𝑃3 (𝑠) = 𝑠 3 + 1.75𝑤0 𝑠 2 + 2.15𝑤0 2 𝑠 + 𝑤0 3 (III.12)
slower reaction time to the first, otherwise some conflicts may
Following these steps allow for the conclusions presented in occur. If the voltages are not balanced it may affect the voltage
(III.13) to be taken. output of the convert which can lead to the system not working
1 as it was designed to.
1.75𝜔0 =
𝑇𝑑 2.15𝐶 The voltage balancing technique is developed taking
𝐾𝑝 =
𝛼𝑣 𝐾𝑝 𝐾 1.752 𝛼𝑣 𝑇𝑑 𝐾 advantage of the systems redundant levels. These redundant
2.15𝜔0 2 = ⇔ levels can be used by taking a configuration that produces the
𝑇𝑑 𝐶 𝐶
𝐾𝑖 = same voltage output, but allows for the charging or discharging
𝛼 𝐾
𝑣 𝑖 𝐾 { 3
1.75 𝛼𝑣 𝑇𝑑 𝐾
𝜔0 3 = of a capacitor whose voltage needs to be compensated.
{ 𝑇𝑑 𝐶
The current CMC is being developed to have 7 modules,
𝐾𝑝 = 106.7498
⇔{ which means it has 2𝑁 + 1 = 15 levels and 2𝑁+1 − 1 = 255
𝐾𝑖 = 2837.2 (III.13)
combinations to produce said levels.
IV. PS-PWM AND DC VOLTAGE BALANCING TECHNIQUE
A. PS-PWM i
This solution was chosen due to it having dynamic
performance, being more robust in line disturbances and faults,
and more flexible in applications, compared to the staircase
solutions [7], as well as minimizing the outputs total harmonic
distortion, the application of this strategy to a CMC enhances
output voltages, reduces voltage stress on semiconductors
switches and lowers acoustic noise and electromagnetic Fig. 7 - Single Converter
interference (EMI), [8], [9], [10]. The solution is also an
important part in the correct operation of the STACOM system, From Fig. 7 it can be seen that when the converter is
as it will allow for some degree of control in the individual DC producing a voltage of +𝑉𝐷𝐶 , that is 𝑆11 and 𝑆22 are ON while
capacitors voltages, because it will operate by distributing an 𝑆12 and 𝑆21 are OFF, and the current is positive then the
equal workload among the modules, guaranteeing the capacitor will start discharging, on the other hand, if the current
minimization of the error in the total average voltage of the DC is negative than the capacitor will be charged. If the converter
 6

is producing a voltage of −𝑉𝐷𝐶 , that is 𝑆12 and 𝑆21 are ON while 6. It is determined which is the combination from the
𝑆11 and 𝑆22 are OFF, than with a positive current the capacitor possible redundancies that has the highest weight
will be charged, and with a negative current the voltage will be value.
discharged. In the case that the output voltage from the 7. With the information obtained in the last step, it is
converter is 0 then independently of the current there will be no necessary to send the driving signals to the switches in
change to the capacitors voltage. With this information it is order to apply the desired AC voltage level with the
possible to build Table 1. desired combination of modules.
Table 1 - Capacitor Behaviour
V. SIMULATION RESULTS
𝒊𝒂 𝑺𝟏𝟏 𝑺𝟏𝟐 𝑺𝟐𝟏 𝑺𝟐𝟐 𝑽𝑷𝑾𝑴 𝑽𝑫𝑪
This section will test the designed systems capabilities to
>0 1 0 0 1 +𝑉𝐷𝐶 ↓
perform the various tasks needed.
<0 1 0 0 1 +𝑉𝐷𝐶 ↑
>0 1 0 1 0 0 → A. Capacitive Compensation
<0 1 0 1 0 0 → For this simulation the system starts in rated conditions and
>0 0 1 0 1 0 → at 𝑡 = 80 𝑚𝑠 a step is applied to 𝐼𝑞,𝑟𝑒𝑓 , as illustrated in Fig. 8.
<0 0 1 0 1 0 → This will lead to a change in the modulation index, as the system
>0 0 1 1 0 −𝑉𝐷𝐶 ↑ reacts to the current controller, thus changing the driving
<0 0 1 1 0 −𝑉𝐷𝐶 ↓ signals sent to the semiconductors of the numerous modules in
The Algorithm used for the capacitors balancing works as the STATCOM.
follows:
1. The DC capacitor reference, 𝑉𝐷𝐶,𝑟𝑒𝑓 , the voltage level
of individual capacitors, the intended voltage output,
and the sign of the AC currents are acquired and
analysed.
2. The voltages deviation from their reference ∆𝑉𝐷𝐶,𝑖 =
𝑉𝐷𝐶,𝑟𝑒𝑓 − 𝑉𝐷𝐶,𝑖 , where 𝑖 represents the index of the
module, are calculated.
3. With the information provided by the PWM, the
voltage level that is to be implemented is determined.
From this information the number of redundant levels
is known.
4. Arranging ∆𝑉𝐷𝐶,𝑖 :
 When the applied voltage level output is positive and Fig. 8 - 𝑰𝒒 and 𝑰𝒒,𝒓𝒆𝒇
the AC current sign is higher than zero, than ∆𝑉𝐷𝐶,𝑖
should be sorted from smallest to biggest, as the The effects of this step in the 𝐼𝑞,𝑟𝑒𝑓 , current are illustrated in
capacitors will discharge. On the other hand if the Fig. 9, where the voltage and current that flow from the
current sign is negative then ∆𝑉𝐷𝐶,𝑖 should be sorted STATCOM at the PCC are represented. When the step is
from biggest to smallest, as in this case the applied to 𝐼𝑞,𝑟𝑒𝑓 there is a transition period, as the system
capacitors will charge. responds to the controllers, after which the current will lead the
 When the applied voltage level output is negative, voltage by approximately 90°, which is an indicative that the
and the AC current sign is higher than zero, than STATCOM is operating in capacitive mode, and therefore the
∆𝑉𝐷𝐶,𝑖 should be sorted from biggest to smallest, as STATCOM will provide the system with reactive power.
the capacitors will charge. On the other hand if the
current has a negative signal then ∆𝑉𝐷𝐶,𝑖 should be
sorted from smallest to biggest, and in this case the
capacitors will discharge.
 If the current is zero than the algorithm should be
exited and the original signals will be sent with no
changes.
5. With ∆𝑉𝐷𝐶,𝑖 ordered, each element will be attributed a
weight value. The first element of the array will be
given the highest weight value, and from there each
element will be given subsequently lower weight
values until the last element receives the smallest
weight value.
 7

Fig. 9 - Voltage and current of phase A at the PCC Fig. 11 - Iq and Iq,ref

When working in capacitive mode the STATCOM will From Fig. 12, it is possible to analyse the behaviour of the
increase the voltage at the PCC. This is directly caused by the voltage and current, that is to say, it is possible to see how the
increase in the voltage output of the CMC, as seen in Fig. 10, current will respond to the STATCOM operated in inductive
which means that in order to have the STATCOM working in mode. The analysis is done at the PCC, from which it is possible
capacitive mode the voltage level of the CMC needs to be to see that after 𝑡 = 80𝑚𝑠 the voltage will lead the current by
increased, and therefore the voltage of the DC side is higher approximately 90°, as would be expected.
than the AC side. As a result, a leading current is then produced
and the STATCOM enters capacitive mode as previously
shown.

Fig. 12 - Voltage and current of phase A at the PCC

Fig. 10 – Voltage output of the CMC in phase A When operating in inductive mode the STATCOM will
lower the voltage at the PCC. This is directly caused by a
B. Inductive Compensation decrease in the voltage output of the CMC, as seen in Fig. 13.
This section will continue evaluate several scenarios o
operation, but this time it will focus on the inductive behaviour
of the STATCOM.
As the simulation starts, the system is working in rated
conditions. At 𝑡 = 80 𝑚𝑠 a negative step is applied to the
reference current 𝐼𝑞,𝑟𝑒𝑓 , as shown in Fig. 11. This will lead to a
response from the controllers, where the system adapts to the
new operation conditions, and the STATCOM switches to
inductive mode, which means that the STATCOM will now
consume reactive power from the grid.

Fig. 13 - Voltage output of the CMC in phase A

 8

C. Compensation a Capacitive Load

A capacitive load is connected to the system with 𝐶 =
7.79 𝜇 𝐹 and will cause the current to lead the voltage by
approximately 17.46°, as demonstrated in the beginning of Fig.
14.
At 𝑡 = 100 𝑚𝑠 the STATCOM has a negative step is applied
to the reference current, 𝐼𝑞,𝑟𝑒𝑓 , as ilustrated in Fig. 15. The
inductive current produced by the STATCOM successfully
counters the effects of a capacitive load, as demonstrated in Fig.
14.

Fig. 16 - DC voltages without compensation system

Fig. 14 - Voltage and current of phase A at the PCC

Fig. 17 - DC voltage with compensation system

E. Voltage sags
A voltage sag at the source is analysed. A voltage drop of
25% occurs at the source. In order to compensate this voltage
dip, the STATCOM needs to enter capacitive mode. From the
analysis of the voltage at the PCC a positive step is applied to
the reference current, 𝐼𝑞,𝑟𝑒𝑓 , which is illustrated by Fig. 18.
When the STATCOM functioning in capacitive mode it will
supply a current that will be ahead of the voltage, Fig. 19.
Fig. 15- 𝑰𝒒 and 𝑰𝒒,𝒓𝒆𝒇

D. Voltage Balancing at the DC Level

To demonstrate the developed voltage balancing technique,
the voltages in the DC level of phase A will be unbalanced. The
results show that without the use of the balancing technique,
Fig. 16, the system will not try to stabilize the individual
voltages of the DC capacitors, to the value of VDC,ref , but will
ensure that the average value in the DC level is in fact VDC,ref .
Whilst with the balancing technique, Fig. 17, the voltages are
successfully balanced leaving a smaller margin of error
between the various voltages in the DC level.

Fig. 18 - 𝑰𝒒 and 𝑰𝒒,𝒓𝒆𝒇

The STATCOM sucssefully compensates the fault which can

be seem in Fig. 20, where the voltage profile is maintaned at the
 9

desired value. In order to enter a capacitive mode the voltage important that the system is capable of adjusting the phase shift
level used in the DC side is elavated as seen in Fig. 21 parameters to suit the new conditions of the system. A simple
recalculation during the simulation takes place, using equation
(IV.1), with the new number of modules, for the updated phase
shift to be implemented.
From Fig. 22 the modulation wave can be seen to suffer an
increase with the loss of the modules which will result in a
higher voltage level applied by the CMC, as shown in Fig. 23,
this occurs due to the converter having a lower number of levels
to present whilst performing the same task. From Fig. 24 it can
be seen that the STATCOM continues to perform its task of
maintaining the voltage at the load, without any issues.

Fig. 19 - Voltage and current of phase A at the PCC

Fig. 22 - Modulation wave

Fig. 20 - Voltage at the PCC

Fig. 23 - Voltage output of the CMC in phase A

Fig. 21 - Voltage output of the CMC in phase A

F. Modularity
To simulate the modularity of the STATCOM, and showcase
the systems stability, the following simulation was done. At 𝑡 =
50 𝑚𝑠 one module, per phase, is going to be disconnected from
the STATCOM, this means that the STATCOM will go from
functioning with seven modules and fifteen levels to
functioning with six modules and thirteen levels, per phase.
When the command is sent to disconnect the modules it is
 10

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pp. 1037-1113.
[5] C. Schauder e H. Mehta, “Vector Analysis and
Control of Advanced Static Var Compensators,”
Electric Power Research Institute, pp. 266-272.
[6] E. 50160, Voltage Characteristics of Electricity
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50160, 2010.
[7] UST, “Utility Systems Technologies, Inc.,”
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VI. CONCLUSION complete DC and AC analysis of three-phase
controlled-current PWM rectifier using circuit D-Q
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been presented. The implemented solution proved that it could
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