Scribd
Upload
13 views1 page

FSM-Based Complex Number Multiplier

This lab covers designing a complex numbers multiplier using a finite state machine. The objective is to multiply two complex numbers represented by real and imaginary parts. A possible implementation is described that uses a datapath with registers and arithmetic components like adders and multipliers. An example sequence of operations is provided that multiplies the real and imaginary parts, stores the partial products, and combines them over 6 clock cycles to produce the final complex product. The sequence is then optimized to reduce the number of cycles by performing subtraction and multiplication concurrently.

Uploaded by

Usman jan
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
13 views1 page

FSM-Based Complex Number Multiplier

This lab covers designing a complex numbers multiplier using a finite state machine. The objective is to multiply two complex numbers represented by real and imaginary parts. A possible implementation is described that uses a datapath with registers and arithmetic components like adders and multipliers. An example sequence of operations is provided that multiplies the real and imaginary parts, stores the partial products, and combines them over 6 clock cycles to produce the final complex product. The sequence is then optimized to reduce the number of cycles by performing subtraction and multiplication concurrently.

Uploaded by

Usman jan
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

Lab 14 | Digital Design

Lab: 14
Open Ended Lab (Design of Complex Numbers Multiplier
Using Finite State Machine (FSM))

Objective:
 Design Complex numbers multiplier using FSM.

Explanation:

In the diagram, the signals upon which data flows are drawn with thicker lines, since they
carry multibit binary-coded values. The remaining signals, drawn with lighter weight lines,
are the clock and the control signals. They include select signals for the multiplexers, clock-
enable signals for the registers, and a signal to choose the operation to be performed by the
adder/subtractor. The values of the control signals are driven by a separate control section.

We first need to determine a sequence of operations to be performed by the datapath to


implement the required function. There are many possible sequences, but we must ensure
that there is no conflict for resources; that is, we must ensure that we don’t try to use an
element of the datapath for more than one operation at a time. One possible sequence,
initiated by input_rdy being 1, is:
1) Multiply a_r and b_r, and store the result in partial product register 1.
2) Multiply a_i and b_i, and store the result in partial product register 2.
3) Subtract the partial product register values and store the result in the product real
part register.
4) Multiply a_r and b_i, and store the result in partial product register 1.
5) Multiply a_i and b_r, and store the result in partial product register 2.
6) Add the partial product register values and store the result in the product imaginary
part register.
This sequence would take six clock cycles to complete. In each cycle, only one of the
arithmetic components is used, so there is no conflict for resources. However, we can reduce
the number of cycles required, without creating conflict, by using the multiplier and the
adder/subtractor concurrently. Specifically, we can merge steps 3 and 4 into one step, in
which we subtract partial products to form the real part of the product and we multiply a_r
and b_i to form a further partial product.

Page 0

You might also like