Microprocessor Lab
Experiment 4
Observation:
a. Some jump instruction can result to an infinite loop and have to be interrupted to stop
b. When JR,nn is ran with halt, the jump will start to count after the address of the HALT
instruction
c. DJ NZ,e – this function monitor the value of register B. It decreases the value of B every time the
instruction is executed and jump back e address if B is not zero
Conclusion:
Unconditional Jump Instructions – cause programs to jump to a specified address without
condition
a. JP NN – jumps to specific address
b. JP (HL) – PC will jump to the address of HL
c. JP e – jumps to a relative address within range of e = +127 to -127, PC+e
Conditional Jump Instructions – cause programs to jump to a specific address only if the
condition specified by a CPU flag is met
Flags Flag = 1 or set Flag = 0 or reset
Carry JP C,nn JP NC,nn
Zero JP Z,nn JP NZ,nn
Parity/Overflow JP PE,nn JP PO,nn
Sign JP M,nn JP P,nn
Conditional Relative Addressing Jump Instructions – jumps by a certain number of byte count
from the original address if only the flag condition is met. PC + e
Flags Flag = 1 or set Flag = 0 or reset
Carry JR C,e JR NC,e
Zero JR Z,e JR NZ,e
DJ NZ,e – monitors the value of register B and jump to the relative address if B is not zero
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Microprocessor Lab
Experiment 5
Observation:
EX NN,NN simply swaps the values of register pair
Push, Pop and EX instructions are useful in exchanging data addresses
LDIR and LDDR are useful in bulk transfer of data
When using CPIR/CPDR, Z flag will set if match is found otherwise z flag will reset. If the
search/compare of HL and A is finished when BC is not equal to zero then P/V flag is set.
If the search is finished and there is no match found BC is zero then P/V is reset.
Conclusion:
a. Data exchange – used for swapping data from original address to another address
EX DE,HL – swaps the value of register pair DE and HL
EX AF,AF’ – accumulator and flag register are swapped with their alternative accumulator and
flag register
EX (SP),HL – value of stack at address SP and SP+1 are with contents of registers L and H,
respectively
b. Memory-to-memory data transfer – used for copying data from original address to
another address
BC: byte counter
DE: starting address of destination memory area
HL: starting address of original memory area
LDI – (load and increment). The data in the address of HL is copied to DE then the address of HL
and DE incremented by one. BC is decreased by one. P/V will be zero if the value of BC equals
zero.
LDD - (load and decrement). The data in the address of HL is copied to DE then the address of HL
and DE decremented by one. BC is decreased by one. P/V will be zero if the value of BC equals
zero
LDIR – (load and increment repeat). The data in the address of HL is copied to DE then the
address of HL and DE is incremented. This process repeats until the value of BC is 0
LDDR - (load and decrement repeat). The data in the address of HL is copied to DE then the
address of HL and DE is decremented. This process repeats until the value of BC is 0.
c. Search memory instructions – used to search for an identical data in a memory area
A : 8-bit data to be searched
HL : starting address of memory area to be searched
BC : byte counter
CPI – data in address pointed by HL is compared with the value of accumulator. S and Z flags
indicate the result of the comparison. Then, HL is incremented and BC is decremented
CPD - data in address pointed by HL is compared with the value of accumulator. S and Z flags
indicate the result of the comparison. Then, HL is decremented and BC is decremented
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Microprocessor Lab
CPIR - data in address pointed by HL is compared with the value of accumulator. S and Z flags
indicate the result of the comparison. Then, HL is incremented and BC is decremented. These
process repeats until A is equal to data in address HL or BC is zero
CPDR - data in address pointed by HL is compared with the value of accumulator. S and Z flags
indicate the result of the comparison. Then, HL is decremented and BC is decremented. These
process repeats until A is equal to data in address HL or BC is zero
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Microprocessor Lab
Experiment 6
Observation:
Bit setting is used to set a bit b in register r. Bit resetting is used to reset a bit b in register r.
These instructions change the value of the register one bit at a time.
Bit testing test the bit of register r if it is ‘0’ then z flag is set otherwise z flag is reset. This
instruction does not alter or change the value of r.
Instructions like AND and OR are used to mask a value so the resulting bit of the logic will always
be equal to 1 or 0 depending on the problem or if use of RES and SET are not allowed. This is
useful when setting or resetting multiple bits at a time.
To Reset multiple bits without using RES, use AND instruction and bit logic 1 to those bit that are
desired to always be reset
To set multiple bits without using SET, use OR instruction and bit logic 1 to those bits that are
desired to always be set.
Conclusion:
a. Bit Testing
BIT b,r – b is the nth bit from 0-7 where 0 is the least significant bit. Bit b of the register r is
tested. If b is ‘0’ then Z flag is set and if b is ‘1’ then Z flag is reset to zero. The value of r, tested
bit, is not changed.
BIT b,(HL) – bit b of the data in address HL is tested
b. Bit Setting
SET b,r – Bit b of register r is set to one
SET b,(IX+d) – sets the bit to one of the data pointed by Index register plus displacement d
c. Bit Resetting
RES b,r – resets the bit b of register r to zero
RES b,(HL) – resets the bit of the data in address HL to zero
RES b,(IY+d) – resets the bit of the data in address pointed by Index Register IY plus
displacement d to zero
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