D D D D: SN74ALS166 Parallel-Load 8-Bit Shift Register
D D D D: SN74ALS166 Parallel-Load 8-Bit Shift Register
FUNCTION TABLE
INPUTS INTERNAL
OUTPUT
PARALLEL OUTPUTS
CLR SH/LD CLK INH CLK SER QH
A...H QA QB
L X X X X X L L L
H X L L X X QA0 QB0 QH0
H L L ↑ X a...h a b h
H H L ↑ H X H QAn QGn
H H L ↑ L X L QAn QGn
H X H ↑ X X QA0 QB0 QH0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Copyright 2000, Texas Instruments Incorporated
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
logic symbol†
9 SRG8
CLR R
15
SH/LD M1 [Shift]
M2 [Load]
6
CLK INH ≥1
7 C3/1
CLK
1
SER 1, 3D
2
A 2, 3D
3
B 2, 3D
4
C
5
D
10
E
11
F
12
G
14 13
H QH
† This symbol is in accordance with ANSI/IEEE Standard 91-1984 and IEC Publication 617-12.
1 2 3 4 5 10 11 12 14
15
SH/LD
9
CLR
R R R R R R R R
1A 1A 1A 1A 1A 1A 1A 1A 13
C1 C1 C1 C1 C1 C1 C1 C1 QH
7 1S 1S 1S 1S 1S 1S 1S 1S
CLK
CLK INH 6
CLK INH
CLR
SER
SH/LD
A H
B L
C H
D L
Parallel
Inputs E H
F L
G H
H H
QH H H L H L H L H
Inhibit
Serial Shift Serial Shift
Clear Load
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W
DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W
Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
† Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The package thermal impedance is calculated in accordance with JESD 51-7.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
MIN MAX UNIT
fclock Clock frequency 45 MHz
CLR low 9
tw Pulse duration CLK high 10 ns
CLK low 10
SH/LD 16
tsu ↑
Setup time before CLK↑ Data 7 ns
CLR inactive 11
th Hold time, data after CLK↑ 3 ns
tw(clear)
3.5 V
CLR
1.3 V 1.3 V
(see Note C)
0.3 V
tn + 1 (see Note D) tn + 1
tn tn 3.5 V
CLK
1.3 V 1.3 V 1.3 V 1.3 V
(see Note E)
0.3 V
tw(CLK) tsu th tsu th
3.5
Data Input
1.3 V 1.3 V 1.3 V 1.3 V
(see Test Table)
0.3 V
tPHL tPLH tPHL
VOH
Output QH
VOL
VOLTAGE WAVEFORMS
NOTES: A. CL includes probe and jig capacitance.
B. Propagation delay times (tPLH and tPHL) are measured at tn+1. Proper shifting of data is verified at tn+8 with a functional test.
C. A clear pulse is applied prior to each test.
D. tn = bit time before clocking transition, tn+1 = bit time after one clocking transition, and tn+8 = bit time after eight clocking transitions.
E. The clock pulse has the following characteristics: tw(clock) ≤ 20 ns and PRR = 1 MHz. The clear pulse has the following
characteristics: tw(clear) ≤ 20 ns.
F. All pulse generators have the following characteristics: ZO ≈ 50 Ω; tr = tf = 2 ns. Duty cycle = 50% when testing fmax.
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Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2007, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
[Link] 18-Sep-2008
PACKAGING INFORMATION
Orderable Device Status (1) Package Package Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Type Drawing Qty
SN74ALS166D ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DBR ACTIVE SSOP DB 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DBRE4 ACTIVE SSOP DB 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DBRG4 ACTIVE SSOP DB 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DE4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DG4 ACTIVE SOIC D 16 40 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DR ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DRE4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166DRG4 ACTIVE SOIC D 16 2500 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166N ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74ALS166NE4 ACTIVE PDIP N 16 25 Pb-Free CU NIPDAU N / A for Pkg Type
(RoHS)
SN74ALS166NSR ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166NSRE4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74ALS166NSRG4 ACTIVE SO NS 16 2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
[Link] for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
Addendum-Page 1
PACKAGE OPTION ADDENDUM
[Link] 18-Sep-2008
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
[Link] 19-Mar-2008
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
[Link] 19-Mar-2008
Pack Materials-Page 2
MECHANICAL DATA
0,38
0,65 0,15 M
0,22
28 15
0,25
0,09
5,60 8,20
5,00 7,40
Gage Plane
1 14 0,25
A 0°–ā8° 0,95
0,55
Seating Plane
PINS **
14 16 20 24 28 30 38
DIM
4040065 /E 12/01