VERSATILE GATE FOR ARTIFICIAL NEURAL NETWORK CIRCUIT
Abul hasanat Muhammad jahanur rahman email: [Link]@[Link]
Texas A&M University and College of North Atlantic 60030860@[Link]
Member of IEEE and AIChE Mobile: +974-5408676
ABSTRACT
This paper provides descriptive design analysis of an innovative device called Versatile gate by
analyzing its electronic structure. The prime purpose of this device is to introduce hardware base
flexible neural network system which can change internal electronic structure by changing the
gates arrangement. Currently electronics circuit chips are made based on basic logic gates like
AND, OR, NOR etc. Once they are embedded, the chip structure is permanent. This Versatile
gate removes this hindrance through its multipurpose function of converting into any one of the
basic six logic gates based upon input control signals. In short, any circuit architecture can be
made only using this gate and using external software they can be turned into series or parallel
connection of AND or NOR or XOR gates. It’s like hardware base artificial neural network chip,
whose internal logic gates arrangement can be changed through software control. Because this
gate can act like any other logic gates one at a time. This can introduce flexible AI (artificial
intelligent) Microchip in its basic level.
It is a multipurpose device, which can be transformed into any types of gates, amplifier,
differentiator, and integrator. It has control inputs which guides transformation of this device.
This implies that any chip made of this device can change hardware structure just by using
software program. This enables hardware upgrading without buying new chips. This reduces
electronic wasteland, which proves that it is very ergonomic and environmental friendly.
RESEARCH PURPOSE
• This versatile logic gate can perform various gate functions by selecting control inputs
• Demonstrate its capability to function as amplifier, differentiator, integrator, XOR, AND,
OR, NOT and its inverse gates
• Experiment is continuing to make it as close as possible to ideal op-amp functionality, for
example infinite open-loop gain, infinite bandwidth, infinite input impedances resulting
in zero input currents, infinite slew rate, zero output impedance and zero noise.
• Reduce inverse relationship between bandwidth and gain and also noise interference.
• It is made of high impedance CMOS transistor for higher input resistance and wide
bandwidth with low impedance BJT transistor at the output for lower impedance.
• Introduction of internal harmonic resonance power regulator circuit and ring bus
feedback system in this gate for further advancement.
CIRCUIT DESIGN
It has two main parts known as master and slave. First one is called “Logic network” and later
one is “Balancing network” which is a upgraded structure of op-amp. The main part is the master
or “Logic network”, which provides transformation functionality of changing from one logic
gate to another. It has twelve control inputs and three outputs. Input 1 and 8 are main control
system or power inputs. Channel inputs have complementary sides with each other either one
have to be logic 1(positive power source) and other 0 (negative source). It consists of two
enhanced MOSFET connected with four JFET complementary differential circuits. These JFETs
have internal dynamic memory functionality for the main channel input. This JFET has control
gate (CG) and floating gate (FG) that is insulated all around by an oxide layer. The FG is
between the CG and the substrate and acts like a capacitor to store the binary information on it as
a static memory. When electrons are on the FG, they modify (partially cancel out) the electric
field coming from the CG along with the threshold voltage of the cell. Depending on this
tunneling voltage on the CG, electrical current will either flow or not flow.
This is controlled by the number of electrons present on the FG. The presence or absence of this
charge level (incoming signal from input 2 and 5) is sensed and translated into 1s and 0s. These
four JFETS of this logical circuit are programmed by starting up electrons flowing from the
source to the drain through two master inputs through hot-electron injection process. The bit can
be erased by a large voltage differential between the CG and source. Input 3, 4, 6 and 7 are
control inputs connected through micro thyristor switch which induces different functionality
based on the logical input arrangement. Input 2 and 5 are for digital or analog data input. In the
following logic table, different configuration of this gate is given based upon eigth control inputs
(four SCR inputs and four AUX inputs). Rests are for data inputs and outputs. Any one or all
three outputs can be used. Usually these three outputs are directly connected “balance network”
which is slave part, not necessary for the main function of this versatile gate. In the table ‘X’
indicates either 1 or 0 bit. ‘-’ means no signal needed or open circuit connection.
MASTER CHANNEL INPUT
SCR INPUT AUX INPUT
INPUT Input 2&5
n-JFET n-JFET P-JFET P-JFET Input Input Input Input GATE
Input1 Input8 Input3 Input4 Input6 Input7
39B 38B 37B 36B
(1) (2) (1) (2) 9 10 11 12
41B 40B 35B 34B 3B 32B
1
56B X
5B X
54B X
53B X
52B X
51B 1
50B 1
49B 0
48B 0
47B X
46B X
45B X
4B X
43B OR
42B
X
71B 1
70B X
69B X
68B X
67B X
6B 0
65B 0
64B 1
63B 1
62B X
61B X
60B X
59B X
58B NOR
57B
-
86B -
85B X
84B X
83B X
82B X
81B 0
80B 1
79B 0
78B 0
7B X
76B 1
75B X
74B X
73B AND
72B
-
10B -
10B X
9B X
98B X
97B X
96B 1
95B 0
94B 0
93B 0
92B 1
91B X
90B X
89B X
8B AND
87B
-
16B -
15B X
14B X
13B X
12B X
1B 0
10B 0
109B 1
108B 0
107B X
106B X
105B 1
104B X
103B NAND
102B
-
13B -
130B X
129B X
128B X
127B X
126B 0
125B 0
124B 0
123B 1
12B X
12B X
120B X
19B 1
18B NAND
17B
-
146B -
145B X
14B X
143B X
142B X
14B 1
140B 0
139B 1
138B 0
137B 1
136B X
135B 1
134B X
13B XOR
132B
-
16B -
160B X
159B X
158B X
157B X
156B 0
15B 1
154B 0
153B 1
152B X
15B 1
150B X
149B 1
148B XOR
147B
1
176B 1
175B X
174B X
173B X
172B X
17B 1
170B 1
169B 1
168B 1
167B X
16B X
165B X
164B X
163B XNOR
162B
Output 1 and 2 are complementary of each other. Based upon eight control inputs, 8 bits signal is
required to change the internal function of this versatile gate. In the following demonstration,
data inputs 5 and 2 are feed with logic high or 1 for one time functioning as OR gate and another
time as AND gate by changing the eight control inputs according to above table.
From the voltage meter, value is zero and current has value above zero which indicates output is
logic high or one. Likewise other truth table of different logic gates can be carried out by this
versatile gate (The program used here is MultiSim7). For the slave or “balancing network” of
this gate, it is just a modified op-amp for stabilizing the gate’s signal process. It has push-pull
complementary amplifiers, level translator and current sensing bridge, current limiter, offset
remover and signal stabilizing through emitter follower feedback transistor connects back to the
source reducing saturation distortion and increases bandwidth. It has internal filter that smooth
out the voltage signal level by removing (spike or noise) sideband harmonic distortion or ripples.
The circuit within the black box in the above figure has two open base inputs for two cascade
amplifier where outputs 1 and 2 goes in. One single output comes out from circuit at the end
within the green box, which has NOT gate configuration that can be turn on or off. This whole
design with master and slave connected together can act as clock or counter since master can
produce two complementary output signals. The clock speed depends on internal capacitance
called transient response (τ = RC). Its Miller capacitance can decrease bandwidth and increase
noise. In order to reduce this effect, capacitive schottky transistors (it has low forward voltage
drop and a very fast switching action) must be used for high processing speed and bandwidth.
External crystal or RLC filter circuit can also be added to the slave section of this gate. In the
blue box of the above figure, this circuit provides a constant voltage drop between its collector
and emitter regardless of the current passing through it. If the base current to the transistor is zero
then voltage between base and emitter becomes equal to threshold voltage, which makes the
current flowing through the two bridge resistors with same value. This serves to bias the two
output transistors slightly into conduction reducing crossover distortion. Current limiting circuit
(yellow box) increases source impedance along with high differential gain.
CONCLUSION
• It enables hardware base artificial neural network (ANN) circuit design like human brain
(neurons) instead of software base ANN circuit using fuzzy logic.
• It can be used to build upgradeable microprocessors and microcontroller, whose hardware
3B
structure can be changed.
• It can be used to build Random access decoder (RAD) whose address code can be
184B
changed using external signal or software.
• 185B It can operate as Digital to Analog converter and vice versa, oscillator, comparator,
modulator and demodulator for amplitude, frequency and phase modulation based upon
the configuration of the slave circuit.
• 186B It can miniaturize the circuit. Since same amount of gates can be used to make different
circuit structure for different functions within the same chip. For example, a microchip
made with this gate can be turned into any Intel or AMD chip through programming .This
enables hardware upgrading without buying new chips. This lower electronic wasteland.