Dynamic Combinational

Circuits

•
Dynamic circuits

–
Charge sharing, charge redistribution

•
Domino logic

•
np-CMOS (zipper CMOS)

Krish Chakrabarty 1

Dynamic Logic

•
Dynamic gates use a clocked pMOS pullup

•
Two modes: precharge and evaluate

Krish Chakrabarty 2

1
 The Foot

•
What if pulldown network is ON during
precharge?

•
Use series evaluation transistor to prevent fight.

Krish Chakrabarty 3

Dynamic Logic


D


VD
D


VD

Mp



Me



t


Ou

CL



1


In

1


In
2


In
N
PU



2


In
N
PD


3


In

3


In
t


Ou

Me

Mp

CL

n network


p network

•
P
re

c
ha

rg
e


2
ph
a

se

op
e

ra

t
io
n
:


•
E
va

lu
a

t
io
n

Krish Chakrabarty 4

2
 Logical Effort

Krish Chakrabarty 5

Dynamic Logic

•
N+2 transistors for N-input function

–
Better than 2N transistors for complementary static CMOS

–
Comparable to N+1 for ratio-ed logic

•
No static power dissipation

–
Better than ratio-ed logic

•
Careful design, clock signal
needed

Krish Chakrabarty 6

3
 Dynamic Logic: Principles


D


VD •
Precharge


= 0, Out is precharged to VDD by Mp.



Mp


Me is turned off, no dc current flows


t


Ou
(regardless of input values)

CL



1


In •
Evaluation


2


In
N
PD



3


In
= 1, Me is turned on, Mp is turned off.

Output is pulled down to zero depending

Me

on the values on the inputs. If not,




precharged value remains on CL.

Important: Once Out is discharged, it cannot be charged again!

Gate input can make only one transition during evaluation

•
Minimum clock frequency must be maintained

•
Can Me be eliminated?

Krish Chakrabarty 7

Example


D
VD

Mp



t


Ou
•
Ra

ti

o
le

s
s

•
No

S
ta

ti
c

P
o
w
e
r
Co

n
s
u
m
p
ti
o

n

A
•
No

is

e
Ma

rg

in


s
s
m
a
ll

(N

M

L
)


C

•
Re

q
u
ir
e

s
Cl
o

c
k

B

Me

Krish Chakrabarty 8

4
Dynamic 4 Input NAND Gate
VDD

Out

In1
In2
In3
In4

 GND

Krish Chakrabarty 9

Cascading Dynamic Gates

D


VD
D
VD

V

Mp



Mp


In


Ou
t
1

Ou
t
2

Ou
t
1


In

VT

n

Ou
t
2




Me



Me

t

Internal nodes can only make 0-1 transitions during evaluation period

Krish Chakrabarty 10

5
 Monotonicity

•
Dynamic gates require monotonically rising inputs
during evaluation

–
0 -> 0

–
0 -> 1

–
1 -> 1

–
But not 1 -> 0

Krish Chakrabarty 11

Monotonicity Woes

•
But dynamic gates produce monotonically falling
outputs during evaluation

•
Illegal for one dynamic gate to drive another!

Krish Chakrabarty 12

6
Reliability Problems — Charge Leakage

D
VD





Mp


Ou
t


(1
)

C

L

A
t

Vo

u
t
pr
e
c
h

a
r
g
e

ev
a
l
u

a
t
e


(2
)

A = 0


Me

t

(a
)

Le
a
k
a
g
e

so
u
r
c
e
s

(b
)

Ef
f
e
c
t

on

wa
v
e
f
o
r
m

s

(1) Leakage through reverse-biased diode of the diffusion area

(2) Subthreshold current from drain to source

Mi

n
im


u
m
Cl
o

c
k
Fr
e

q
u
e
n
c
y
:
>
1
MH

z

Krish Chakrabarty 13

Leakage

•
Dynamic node floats high during evaluation

–
Transistors are leaky (IOFF
0)

–
Dynamic value will leak away over time

–
Formerly miliseconds, now nanoseconds!

•
Use keeper to hold dynamic node

–
Must be weak enough not to fight evaluation

Krish Chakrabarty 14

7
 Charge Sharing (redistribution)
•
Assume: during precharge, A and B are 0, Ca is discharged

V
DD



•
During evaluation, B remains 0 and A rises to 1

•
Charge stored on CL is now redistributed over CL and Ca

M
p

O
ut

C
L
CLVDD = CL Vout(t) + CaVX

A
M
a

X
VX = VDD - Vt, therefore

Ca

C
a

Vout(t) = Vout(t) - VDD = (VDD-Vt)

B
=
0
M
b
CL

C
b
Desirable to keep the voltage drop below threshold

M
e

of pMOS transistor (why?)  Ca/CL < 0.2

Krish Chakrabarty 15

Charge Sharing

•
Dynamic gates suffer from charge sharing

Krish Chakrabarty 16

8
Charge Redistribution - Solutions
V
DD


V
DD

M
p
M
b
l


M
p
M
b
l

O
ut


O
ut


A
M
a
A
M
a

B
M
b
B
M
b

M
e


M
e

(
a
)
S
ta

ti
c

b
le

e
d
e
r
(
b
)
P
r
e
c
h
a
r
ge

o
f
i
n
te

r
n
a
l
n
o
d
e
s

Krish Chakrabarty 17

Secondary Precharge

•
Solution: add secondary precharge transistors

–
Typically need to precharge every other node

•
Big load capacitance CY helps as well

Krish Chakrabarty 18

9
 Domino Logic

V
DD


V
DD



V
DD

M
p


M
p
M
r

O
ut

1

O
ut

2

I
n1

S
t
at

i
c
I
nv

er
t

e
r

I
n2

P
D
N
I
n4

P
D
N
w
i
t
h
L
e
v
e
l
R
e
st

o
re

r

I
n3

M
e


M
e

Static inverters

between dynamic stages

Krish Chakrabarty 19

Domino Gates

•
Follow dynamic stage with inverting static gate

–
Dynamic / static pair is called domino gate

–
Produces monotonic outputs

Krish Chakrabarty 20

10
 Domino Logic - Characteristics

• Only non-inverting logic

• Very fast - Only 1->0 transitions at input of inverter

•
Precharging makes pull-up very fast

• Adding level restorer reduces leakage and
charge redistribution problems

• Optimize inverter for fan-out

Krish Chakrabarty 21

Domino Optimizations

•
Each domino gate triggers next one, like a string of
dominos toppling over

•
Gates evaluate sequentially but precharge in parallel

•
Thus evaluation is more critical than precharge

•
HI-skewed static stages can perform logic

Krish Chakrabarty 22

11
 Dual-Rail Domino

•
Domino only performs noninverting functions:

–
AND, OR but not NAND, NOR, or XOR

•
Dual-rail domino solves this problem

–
Takes true and complementary inputs

–
Produces true and complementary outputs

sig_h
sig_l
Meaning

0
0
Precharged

0
1
‘0’

1
0
‘1’

1
1
invalid

Krish Chakrabarty 23

Example: AND/NAND

•
Given A_h, A_l, B_h, B_l

•
Compute Y_h = A * B, Y_l = ~(A * B)

•
Pulldown networks are conduction complements

Krish Chakrabarty 24

12
 Example: XOR/XNOR

•
Sometimes possible to share transistors

Krish Chakrabarty 25

Domino Summary

•
Domino logic is attractive for high-speed circuits

–
1.5 – 2x faster than static CMOS

–
But many challenges:

•
Monotonicity

•
Leakage

•
Charge sharing

•
Noise

•
Widely used in high-performance microprocessors

Krish Chakrabarty 26

13
 np-CMOS (Zipper CMOS)

V
DD


V
DD

M
p


M
e

O
u
t1

I
n
1
P
UN



I
n
2
P
D
N
I
n
4

I
n
3
O
u
t
2

M
e


M
p

•
Only 1-0 transitions allowed at inputs of PUN

•
Used a lot in the Alpha design

Krish Chakrabarty 27

np CMOS Adder

Krish Chakrabarty 28

14
CMOS Circuit Styles - Summary

Krish Chakrabarty 29

15