Designing with
Protel
®
November 2002 Version 1.4
Abstract
Triscend supports the use of the Protel schematic editor for the creation of designs to place into the
Configurable System Logic (CSL) portion of a Triscend device.
Support is available with FastChip Release 2.4.0 and higher in the form of schematic libraries and EDIF
netlist import for the Protel schematic editor.
Contents
Introduction................................................................................................................................................ 2
System Requirements............................................................................................................................... 2
Before You Begin ...................................................................................................................................... 3
Further Reading..................................................................................................................................... 3
Creating Designs in Protel ........................................................................................................................ 4
Using Components with Bus Ports........................................................................................................ 7
General Guidelines ............................................................................................................................ 7
Connecting Arbitrary Signals ............................................................................................................. 9
Creating an EDIF Netlist in Protel ........................................................................................................... 10
Common Problems ................................................................................................................................. 15
© 2002 by Triscend Corporation. All rights reserved. [Link]
Triscend Part Number TCH406-0003-001
Introduction
The Protel schematic editor can be used to create designs for the CSL portion of Triscend devices.
Triscend supports this tool by providing schematic libraries, which contain elements to use to create
schematic designs. Upon completion, or as part of an iterative design process, the schematic designs
are exported from the schematic editor in EDIF 2.0.0 format and can then be imported into FastChip,
as modules, for use as design elements in that tool.
With the FastChip 2.4.0 release and higher, Protel schematic libraries are included in .lib format files
and FastChip import support can read Protel EDIF netlists.
System Requirements
To use Protel to create designs for FastChip, you need the following items:
• Protel 99 SE for Windows software:
This is the software you use to create schematic designs and EDIF netlists.
• Triscend Protel schematic libraries:
These are schematic libraries created specifically for use in the Protel schematic editor. They
contain design elements to use to access the configurable system logic portion of the device.
Currently, the default library is included as .lib files and consists of these files ([FastChip Dir] is the
root directory containing the FastChip software installation):
• [FastChip Dir]/data/libraries/Schematic/Protel/[Link]
• [FastChip Dir]/data/libraries/Schematic/Protel/[Link]
• [FastChip Dir]/data/libraries/Schematic/Protel/[Link]
• [FastChip Dir]/data/libraries/Schematic/Protel/[Link]
• The Triscend FastChip Development System:
You import into FastChip the EDIF files exported by Protel. Once imported, your designs become
Imported modules in FastChip and can be instantiated in designs.
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Before You Begin
Before creating a new design in Protel, you should first read the Triscend Primitives document, which
describes the use of parametric ports and other issues unique to schematic design using the Triscend
schematic libraries.
For complete information on using this schematic editor, refer to the Protel documents Protel 99 SE
Designer’s Handbook and Exploring Protel 99 SE Introductory Tutorial.
Further Reading
A variety of technical documents are available which describe FastChip design elements and
processes. In the Docs directory of the FastChip software installation, see the documents
Documentation_Guide.pdf and Description_of_Technical_Documents.pdf for an overview of available
reference material.
Recommended documents for further reading about CSI bus behavior and CSL design include:
• [FastChip Dir]/Docs/Technical Documents/Designing_with_Selector_Primitives.pdf
• [FastChip Dir]/Docs/Technical Documents/Designing_with_Triscend_Busses.pdf
• [FastChip Dir]/Docs/Technical Documents/Triscend_Primitive.pdf
You will find specific usage information about Triscend busses and CSL design in these references.
Also, Triscend data sheets for the E5 and A7 families contain a great deal of information about device
features and their use.
• [FastChip Dir]/Docs/Technical Documents/[Link]
• [FastChip Dir]/Docs/Technical Documents/[Link]
Documents are also available providing information on using third-party tools to create and verify user
designs.
• [FastChip Dir]/Docs/Technical Documents/Using_Soft_Modules_with_EDA_Tools.pdf
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Creating Designs in Protel
Follow these steps to begin using Protel:
1. Start Protel 99 SE.
The Design Explorer window opens for you to create a new design.
2. Using the menu command [File | New], invoke the New Design Database dialog box if this is your
first design (if designs already exist: create a new design with the menu command [File | New
Design]).
3. Enter the Design Storage Type (default is MS Access Database), the Database File Name (for
example [Link]) and Database Location for your project. The dialog box is shown below.
After you click the OK button, the design database is created and you may now create a new
design. The Design Explorer window should show the [Link] design database.
4. Use the menu command [File | New] to invoke the New Document dialog. In the Documents tab,
select the Schematic Document icon and click the OK button.
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By default, Protel names the schematic document “[Link]”. You can change the document
name by clicking on the name in the Explorer tab or [Link] tab in the Design Explorer
window and editing it. The Design Explorer window looks similar to the figure below.
To begin working on your design, click on the schematic tab on the right side of the Design
Explorer window, and then the Browse Sch tab on the left side of the window. In order to
instantiate symbols from the Triscend schematic library, you need to reference the Triscend
schematic capture library. Click on the Add/Remove button on the left to browse available libraries.
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5. After you click the Add/Remove button, the Change Library File List dialog appears. For Files of
type, select “Advanced Schematic binary library (*.lib)”. For the Look in directory, go to the
FastChip installation directory and select the Protel schematic library directory ([FastChip Dir] is the
root of the installation directory) [FastChip Dir]\data\libraries\Schematic\Protel. Select each of the
.lib files in the top window and click on the Add button. Click OK when done.
6. The following libraries should be now listed in the Browse Sch tab of the Design Explorer window:
[Link], [Link], [Link] and [Link]. Click on a library name to
select it and the available symbol names appear in the window area below. Here, the [Link]
library has been selected, which contains most of the symbols you will use.
The set of Protel schematic libraries includes the following files:
• [Link] (primitives)
• [Link] (macros)
• [Link] (sideband signals for the A7 device family)
• [Link] (sideband signals for the E5 device family)
The Design Explorer window should appear similar to the figure below:
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You can now begin to instantiate elements in your designs. If you are a new Protel user, some of the
more common practices to follow include the following:
• Make sure you annotate your design before exporting the EDIF netlist
• Set port types to a valid selection and do not leave it as “unspecified” (the default value)
• Label all busses
• Avoid underscores ‘_’ in names or use them with care
Using Components with Bus Ports
A number of Triscend components have a multi-bit input or output port, for example macros for multi-bit
counters and selector primitives. However, Protel components in the Triscend schematic libraries do
not support bus ports, and all ports are actually single-bit ports.
To create schematic designs that use these components, you will follow a set of conventions to enable
the FastChip import command to process the resulting EDIF netlist properly and interpret single bit
ports and wires as bus ports and bus connections; within Protel these are scalar ports and wires, and
errors may result during electrical rules checking (ERC) that will be ignored.
General Guidelines
If the component has a multi-bit output, for example Q[15:0], connect a wire and label it QNET[15:0].
Note that the component pin is actually a single bit in Protel, but based on the pin name the FastChip
software will treat it as a multi-bit pin when the EDIF netlist is imported. Also, this bus notation differs
from the Protel convention which uses the characters “..” as the range, for example QNET[15..0].
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When the wire is connected to a single bit input, for example QNET[15:0] is connected to the D input of
a flip-flop, the least significant bit is connected by FastChip when the EDIF netlist is imported (for a wire
labeled QNET[15:0], QNET[0] would be connected to the D pin).
When the wire is connected to a multi-bit input, for example QNET[15:0] is connected to the multi-bit
input X[7:0] of an 8-bit adder, the least significant bits are connected by FastChip when the EDIF netlist
is imported (for a wire labeled QNET[15:0], QNET[7:0] would be connected to X[7:0]). Note that X[7:0]
is interpreted by FastChip import as multi-bit pin, but in Protel it remains a single bit port.
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Connecting Arbitrary Signals
When the wire is to be connected to an arbitrary set of single bit inputs, for example I2, I1 and I0,
attach a wire to each input (A, B, C) but do NOT connect the wires. Add a label to each wire to
designate the connection to the multi-bit output, for example use a QNET7 label to connect Q[7] to
input I2, a QNET5 label to connect Q[5] to I1, and a QNET3 label to connect Q[3] to I0. Note that wires
are labeled and connected to only one component pin (an ERC error results because the wire is not
connected at both ends – ignore these errors). During FastChip import, the net connections will be
resolved.
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Creating an EDIF Netlist in Protel
When you have completed the schematic layout of your design and are ready to import it as a module
into FastChip, follow these steps to create an EDIF netlist:
1. In the Design Explorer, use the menu command [Tools | Annotate] to annotate the schematic.
The Annotate dialog is invoked to annotate the Protel schematic.
This process assigns references for each instance of a symbol. You must annotate the schematic
before proceeding. In the Annotate dialog box, you will select the Options tab to cause all parts in
the selected schematic pages to be updated; both part reference and package information may be
updated on existing parts.
In the Annotate Options frame, “All Parts” is selected and Current sheet only is checked in this
example. In the Group Parts Together If Match By frame, Part Type is checked. Click the OK
button.
An example of the Annotate dialog box is shown below.
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2. You can perform an Electrical Rule Check (ERC) by invoking the ERC dialog from the Design
Explorer (menu command [Tools | ERC]).
This option helps locate any reported warning messages by placing a highlighted marker on your
schematic drawing.
In the Setup tab, a useful set of ERC options includes the following:
• Multiple net names on net
• Unconnected net labels
• Unconnected power objects
• Duplicate sheet numbers
• Duplicate component designators
• Bus label format errors
• Floating input pins
• Create report file
• Add error markers
The ERC dialog is shown below.
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3. You should use the ERC dialog to invoke the Electronic Rule Checker (ERC) to check for any
design problems, but this is not necessary every time you import a design.
4. To invoke the Netlist Creation dialog, make sure the schematic is the active tab in the right half of
the Design Explorer window and use the menu command [Tools | Create Netlist].
In the Netlist Creation dialog box, click the Preferences tab.
Set the following options:
a) For Output Format, select Edif 2.0.
b) For Net Identifier Scope, select Sheet Symbol/Port Connections.
c) For Sheets to Netlist, select Active Project
d) Check boxes are not checked by default
Click the OK button.
A sample Netlist Creation dialog is shown below:
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5. After you close the Netlist Creation dialog, a Confirm dialog will appear and ask “Use Pin Names
instead of Pin Numbers?” You must click the Yes button.
6. The netlist is created and in the Design Explorer window, a <sheet_name>.NET tab appears. You
must save the netlist using the menu command [File | Save]. An example of the Design Explorer
window after netlist creation appears below.
7. To export the EDIF file, move the mouse pointer over the icon to the left of the netlist file in the
Explorer tab on the left side of the window. Click the right mouse button over the icon to the left of
the netlist file (in this example, [Link]) to pop up a menu and select the Export dialog.
You should specify the directory containing the FastChip Project, into which you want to import the
design (or specify any directory name and later copy the file to the FastChip project directory).
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8. Click the OK button.
Your design is exported to EDIF, and you can now import the design into FastChip as a module.
During the import process, a design rule check is run on the EDIF design to make sure it is compatible
with the internal Triscend tools. If the design rule check fails, you must change your design in Protel,
again export the design to EDIF, and then re-import your design into FastChip.
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Common Problems
If you experience problems importing EDIF netlists created with Protel, consult the items below for
some of the more common issues experienced by users.
1. Pin numbers used instead of pin names
When the Create Netlist dialog is closed, a Confirm dialog appears asking if you wish to use pin names
instead of pin numbers in the netlist. You must click on the Yes button (use pin names).
2. Design was not annotated
Before you create the netlist from the schematic, you must annotate the design. With the schematic
active (selected), go to the Tools menu and invoke the Annotate dialog.
3. Busses are not labeled
When creating your schematic, make sure all busses are labeled. You should also run an Electrical
Rule Check (ERC) before creating a netlist; from the Tools menu, select the ERC item.
4. Port type is not set
When adding a port, be sure to set the port type to input, output or bidirectional. It should not be left at
the default value “unspecified”.
5. Underscore character ‘_’ in identifiers results in FastChip import errors
When specifying identifier names, use care when (or avoid) using the underscore character ‘_’. When
Protel creates a netlist, certain characters such as square brackets ‘[‘ and ‘]’ are converted to the
underscore character. Because FastChip examines identifier names and looks for the underscore
character to create busses from flattened ports and nets, it may become confused and attempt to treat
a name as a bus if it contains an underscore. For example, a port named BPORT_1_ may be
interpreted as part of a bus port, even if the user did not actually define a bus port.
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®
Triscend Corporation
301 North Whisman Road Mountain View, CA 94043-3969 USA
Tel: 1-650-968-8668 Fax: 1-650-934-9393 Web: [Link]
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