Cyclone II EP2C35F67C6
End time and clock period – 200ns
Duty cycle – 50% and 100ns
Gagana lang ang button pag naka high or 1, 0 or low naman para sa buzzer
Prescaler – a counting circuit used to reduce a high frequency electrical signal to a lower
frequency by integer division. It takes the basic timer clock frequency and divides it by
some value before feeding it to the timer
- Allows the timer to be clocked at a rate the user desires; allows tweaking the ratio
between resolution & max period to achieve a desired effect.
std_logic : - one bit digital signal
A nine-value resolved logic type Std_logic is not a part of the VHDL Standard. It is
defined in IEEE Std 1164.
In order to facilitate specification of multiple-driven signals (like data buses) the
Std_Logic_1164 package defines resolution function for Std_ulogic, which in turn
serves as a basis for declaration of Std_Logic type.
The Std_Logic_1164 package defines overloaded logical operators ("and", "nand",
"or", "nor", "xor", and "not") for operands of the Std_ulogic type. Moreover, two
conversion functions are defined as well: Std_ulogic to Bit (function To_Bit), and Bit
to Std_ulogic (function To_StdULogic).
Std_Logic is a resolved type, which means that multiple assignments to the same
object are legal. If FlagC was of the Std_Ulogic type, such a code would not be
acceptable.
Important Notes
Std_Logic is defined as a subtype of Std_ULogic, therefore all operators and
functions defined for Std_Ulogic can be applied to Std_Logic.
Std_Logic is the industry standard logic type and in practice majority of signals
are of this type (or its vector derivative, Std_Logic_Vector type).
std_logic_vector:
The Std_Logic_Vector type is predefined in the Std_Logic_1164 package as a
standard one-dimensional array type with each element being of the Std_Logic type.
The basic VHDL logic operations are defined on Std_Logic_Vector
type: and, nand, or, nor, xor, xnor. These must be given two arrays of the same
size; they do the operation on ecah position and return another array.
The not operation negates each position in the array.
that use of the “std_logic_vector” data type allows us to have much more compact and
readable code.
Std_Logic_Vector is not a part of the VHDL Standard. Instead, it is defined by IEEE
Std 1164
Std_Logic_Vector is an unconstrained (unbound) vector of resolved nine-value logic
elements (std_logic type), which are defined in the Std_Logic_1164 package.
The Std_Logic_1164 package defines overloaded logical operators ("and", "nand",
"or", "nor", "xor", and "not") for operands of the Std_logic_vector type. In addition,
conversion functions from and to Bit_Vector are supported as well.
Assignment to an object of the Std_Logic_Vector type can be performed in the same
way as in case of arrays, i.e. using single element
assignments, concatenation, aggregates, slices or any combination of them.
Moreover, because the elements are of resolved type it is allowed to make multiple
assignments to a Std_Logic_Vector object type. In such a case, the resolution function
defined for Std_Logic is used.
Std_Logic_Vector should not be confused with the Std_Ulogic_Vector type.
Elements of the latter are of the type Std_Ulogic and are unresloved version of
Std_Logic. This means that it is illegal for the two values (e.g. '0' and 'Z') to be
simultaneously driven into a signal of the Std_ulogic type.
In order to use the Std_Logic_Vector type, the Std_Logic_1164 package must
be explicitly listed at the beginning of an entity:
library IEEE;
use IEEE.Std_Logic_1164.all;
Architecture
A body associated with an entity declaration to describe the internal organization or
operation of a design entity. An architecture body is used to describe the behavior,
data flow, or structure of a design entity.
Architecture assigned to an entity describes internal relationship between input and
output ports of the entity. It consists of two parts: declarations and concurrent
statements.
First (declarative) part of an architecture may contain declarations
of types, signals, constants, subprograms (functions and procedures), components,
and groups. See respective topics for details.
Concurrent statements in the architecture body define the relationship between inputs
and outputs. This relationship can be specified using different types of
statements: concurrent signal assignment, process statement, component
instantiation, concurrent procedure call, generate statement, concurrent assertion
statement and block statement. It can be written in different styles: structural,
dataflow, behavioral (functional) or mixed.
The description of a structural body is based on component
instantiation and generate statements. It allows to create hierarchical projects, from
simple gates to very complex components, describing entire subsystems. The
connections among components are realized through ports. Example 1 illustrates this
concept for a BCD decoder.
The Dataflow description is built with concurrent signal assignment statements. Each
of the statements can be activated when any of its input signals changes its value.
While these statements describe the behavior of the circuit, a lot of information about
its structure can be extracted form the description as well. Example 2 contains this
type of description for the same BCD decoder as in the previous example.
The architecture body describes only the expected functionality (behavior) of the
circuit, without any direct indication as to the hardware implementation. Such
description consists only of one or more processes, each of which contains sequential
statements (Example 3).
The architecture body may contain statements that define both behavior and structure
of the circuit at the same time. Such architecture description is
called mixed (Example 4).
Single entity can have several architectures, but architecture cannot be assigned
to different entities.
Architecture may not be used without an entity.
All declarations defined in an entity are fully visible and accessible within each
architecture assigned to this entity.
Different types of statements (i.e. processes, blocks, concurrent signal
assignments, component instantiations, etc.) can be used in the same
architecture.
Conditional statement – sequential – “if-else”
Conditional statement – concurrent – “when-else”
Under ng sequential:
If statement -condition tests each condition sequentially until the true condition. It also be treated as
decision making statement and associated with it could be either a Boolean expression or condition.
The boolean expressions will be evaluated successively until a true expression is found. The
assignment corresponding to this true expression will be performed. If none of these
expressions are true, the assignment after the “else” keyword will be executed.
Case statement-is like a switch construct in code which selects a particular branch among many
based on the value of expression
-functions like a multiplexer A multiplexer selects one of its n inputs based on the value of
control_expression.
-one option cannot be used more than once. Moreover, all the possible values of
the control_expression must be included in the set of the options. We can use the keyword
“others” in the final “when” branch of the “case” statement to make sure that all the possible
values of the control_expressionare covered.
Common anode means that the anode (positive) side of all of the LEDs are electrically
connected at one pin, and each LED cathode has its own pin. ... So driving one of these means
running a current from the particular anode (positive) pin for the desired segment to
the common cathode pin.
GPIO is a type of pin found on an integrated circuit that does not have a specific function. While
most pins have a dedicated purpose, such as sending a signal to a certain component, the
function of a GPIOpin is customizable and can be controlled by software