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Vedic Multiplication Techniques and Architectures

This document contains a list of figures describing vedic multipliers of various bit sizes ranging from 2 to 32 bits. The list includes line diagrams, architectures, block diagrams, and RTL schematics of the multipliers as well as simulations of the designs in operation.

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Kulwinder
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29 views2 pages

Vedic Multiplication Techniques and Architectures

This document contains a list of figures describing vedic multipliers of various bit sizes ranging from 2 to 32 bits. The list includes line diagrams, architectures, block diagrams, and RTL schematics of the multipliers as well as simulations of the designs in operation.

Uploaded by

Kulwinder
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd

List Of Figure

pages

Fig.1.1. The vedic Multiplication………………………………………………………………..4

Fig.2.1. Line diagram of two 3-bit numbers multiplication………………………………………9

Fig.2.2. vedic multiplication of three bit no……………………………………………………..10

Fig.2.3. Multiplication using Nikhilam sutra…………………………………………………….11

Fig.5.1. Architecture of 2 bit vedic multiplier…………………………………………………...23

Fig.5.2. Architecture of 4 bit vedic multiplier…………………………………………………...24

Fig.5.3. Architecture of 8 bit vedic multiplier…………………………………………………...25

Fig.5.4. Architecture of 16 bit vedic multiplier………………………………………………….26

Fig.5.5. Block diagram of 16 bit vedic mutiplier………………………………………………..27

Fig.5.6. RTL Shematic of 16 bit vedic multiplier………………………………………………..27

Fig.5.7. Architecture of 32 bit Urdhva vedic multiplier……………………………………… 28

Fig.5.8. RTL Shematic of 32 bit Urdhva vedic multiplier………………………………………29

Fig.5.9. Architecture of 32 bit Nikhilam vedic multiplier……………………………………….30

Fig.5.10. RTL Shematic of 32 bit Nikhilam vedic multiplier……………………………………31

Fig.6.1. Simulation of 32 urdhva vedic multiplier……………………………………………….32

Fig.6.2. Simulation of 32 Nikhilam vedic multiplier………………………………………….…33

Fig.6.3. Simulation of 16 vedic multiplier………………………………………………………34

Fig.6.4. Simulation of 8 vedic multiplier………………………………………………………..35

Fig.6.5. Simulation of 4 vedic multiplier……….……………………………………………….36

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