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Latch D Circuit Design

This document describes a latch entity with an input D, enable input Enable, and output Q. The latch uses an internal signal temp to store the value of D when Enable is high, and assigns temp to Q when Enable is low, maintaining the stored value.

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Karl Hummer
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4 views1 page

Latch D Circuit Design

This document describes a latch entity with an input D, enable input Enable, and output Q. The latch uses an internal signal temp to store the value of D when Enable is high, and assigns temp to Q when Enable is low, maintaining the stored value.

Uploaded by

Karl Hummer
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOC, PDF, TXT or read online on Scribd

LATCH D

entity latchd is
Port ( D : in STD_LOGIC;
Enable : in STD_LOGIC;
Q : out STD_LOGIC);
end latchd;

architecture Behavioral of latchd is

signal temp : STD_LOGIC;

begin

process (D, Enable)


begin
if (Enable = '1') then
q <= d;
temp <= d;
else
q <= temp;
end if;
end process;

end Behavioral;

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