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Synopsys Design Compiler Tutorial

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This document provides a tutorial on how to use the Synopsys Design Compiler synthesis tool. It outlines the steps to set up the tool, including downloading files and setting environment var…

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  • Introduction
  • Goal
  • Overview
  • Setup
  • Run DC
  • Netlists

Tutorial – Synopsys Design Compiler

Dae Hyun Kim

EECS
Washington State University
Goal
• Learn how to use Synopsys Design Compiler
Overview
• Netlist synthesis converts given HDL source codes into a netlist.

• Synthesis software
– Synopsys Design Compiler
– Cadence Genus
– ...
Setup
• Open a terminal.
• Create a work directory in your directory.
– mkdir hw03
• Go to the directory.
– cd hw03
• Check your shell by the following command.
– echo $SHELL
• If the terminal says you are using not bash (e.g., /bin/bash) but
something else (e.g., /bin/csh), run bash as follows.
– bash
• Notice
– If your default shell is not bash, you will have to run bash every
time you log in to your account.
– If you want to change the default shell to bash and forget it, run
“chsh –s /bin/bash”.
Setup
• Get the tutorial file. This will download [Link].
– wget [Link]
• Unzip it.
– unzip [Link]
• Run the following command to list all the files in your current
directory.
– ls –al
• Make sure you have the following files.
– ictools_generic.sh
– [Link]
– [Link] (Nangate 45nm library file)
– [Link] (Nangate 45nm library file)
Setup
• Run the following commands.
– source ictools_generic.sh
– source [Link]
• If you see any error, you will have to fix it or contact the TA or me to
fix it.
• Now you are ready to run DC.
Run DC
• Run the following command.
– design_vision –no_gui
• You will see the following message.
Run DC
• Set libraries.
– set link_library {[Link]}
– set target_library {[Link]}
• Read a source file.
– read_file –format verilog {ex.v}
• Compile (synthesis)
– compile –exact_map
• Save the synthesized netlist.
– write –format verilog –output ex_syn.v
• Exit from DC.
– exit
Netlists
• Open ex.v in a text editor.
– Draw a gate-level schematic for the netlist.
• Input: a [4:0]
• Output: z
– Express z as a Boolean function of the inputs.

• Open ex_syn.v in a text editor.


– Draw a gate-level schematic for the netlist.
– Express z as a Boolean function of the inputs.

• Are they equivalent?

Tutorial – Synopsys Design Compiler Dae Hyun Kim EECS Washington State University
Goal • Learn how to use Synopsys Design Compiler
Overview • Netlist synthesis converts given HDL source codes into a netlist. • Synthesis software – Synopsys Design Comp
Setup • Open a terminal. • Create a work directory in your directory. – mkdir hw03 • Go to the directory. – cd hw03 • C
Setup • Get the tutorial file. This will download tutorial-dc.zip. – wget http://eecs.wsu.edu/~ee434/Labs/tutorial-dc.zip (
Setup • Run the following commands. – source ictools_generic.sh – source synopsys.sh • If you see any error, you will hav
Run DC • Run the following command. – design_vision –no_gui • You will see the following message.
Run DC • Set libraries. – set link_library {ng45.db} – set target_library {ng45.db} • Read a source file. – read_file –f
Netlists • Open ex.v in a text editor. – Draw a gate-level schematic for the netlist. • Input: a [4:0] • Output: z – Exp

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