WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT : ELECTRONIC DEVICES AND CIRCUITS TIME : 09.00AM TO 12.00PM
DATE : 11/10/2017 YEAR/SEM : II / III
SUB. CODE : 34034
TIME TABLE
BATCHES REGISTRATION NUMBER NO. OF STUDENTS
BATCH I 17404422,17404424-17404428 6
INTERNAL EXAMINER CHIEF SUPERINTENDENT
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT : ELECTRONIC DEVICES AND CIRCUITS TIME : 09.00AM TO 12.00PM
DATE : 11/10/2017 YEAR/SEM : II / III
SUB. CODE : 34034
TIME TABLE
BATCHES REGISTRATION NUMBER NO. OF STUDENTS
BATCH I 17404422,17404424-17404428 6
INTERNAL EXAMINER EXTERNAL EXAMINER
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: ADVANCED COMMUNICATION SYSTEM PRACTICAL SEMESTER :V
DATE: 11/10/2017 TIME: 10 A.M TO 1P.M
SUBJECT CODE:34055
TIME TABLE
BATCHES REGISTRATION NUMBER NO. OF STUDENTS
16404628,
BATCH I 16404631-16404635,16404638- 22
16404645,16404653,16404657-
16404660,16404664,16404666,
16409686
(VASANDRA DEVI .V) (BABU ASHOK.R)
INTERNAL EXAMINER CHIEF SUPERINTENDENT
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: INTEGRATED CIRCUITS PRACTICAL SEMESTER :IV
DATE: /10/2017 TIME:
SUBJECT CODE:34046
TIME TABLE
BATCHES REGISTRATION NUMBER NO. OF STUDENTS
BATCH I 16404644,16404659 2
(VASANDRA DEVI .V) (BABU ASHOK.R)
INTERNAL EXAMINER CHIEF SUPERINTENDENT
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: INTEGRATED CIRCUITS PRACTICAL SEMESTER :IV
DATE: /10/2017 TIME:
SUBJECT CODE:34046
ALLOCATION OF MARKS
CIRCUIT DIAGRAM : 20
CONNECTION : 25
EXECUTION & HANDLING OF EQUIPMENT : 15
OUTPUT/RESULT : 10
VIVA VOCE : 05
TOTAL : 75
INTERNAL EXAMINER EXTERNAL EXAMINER
(VASANDRA DEVI. V) (MAHALAKSHMI.N)
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: INTEGRATED CIRCUITS PRACTICAL SEMESTER :IV
DATE: /10/2017 TIME:
SUBJECT CODE:34046
LIST OF EXPERIMENTS COMPLETED
1. Verification of truth table of OR, AND, NOT, NOR, NAND, EX-OR gates.
2. Realization of basic gates using NAND & NOR gates.
3. Realization of logic circuit for a given Boolean expression.
4. Half adder, Full adder using ICs.
5. Half subtractor, full subtractor using ICs.
6. Construction and verification of truth table for Decoder/Encoder.
7. Multiplexer/De-multiplexer using multiplexer ICs.
8. Parity generator and checker using parity checker/ generator ICs.
9. Construction and verification of truth table for RS, D, T & JK flip-flop.
10. 4- bit ripple counter using FF
11. Construct a Single digit Decade Counter with 7 segment display.
12. Astable Multi vibrator using IC 555.
13. Simulate the Clippers and clampers using the simulation tool like PSPICE/ multisim/orcad/tina.
14. simulate the inverting and non inverting amplifier, voltage follower, integrator, differentiator,
summing amplifier, difference amplifier(Any 3) using the simulation tool like PSPICE/
multisim/orcad/tina.
15. simulate the Hartley and phase shift oscillator, sine, square and triangular waveform generators and
precision rectifiers(Any 3) using the simulation tool like PSPICE/ multisim/orcad/tina.
INTERNAL EXAMINER EXTERNAL EXAMINER
(VASANDRA DEVI .V) (MAHALAKSHMI.N)
SYLLABUS
34046 - INTEGRATED CIRCUITS PRACTICAL
List of experiments
Note: At least 5 experiments should be constructed using breadboard
1. Verification of truth table of OR, AND, NOT, NOR, NAND, EX-OR gates.
2. Realization of basic gates using NAND & NOR gates.
3. Realization of logic circuit for a given Boolean expression.
4. Half adder, Full adder using ICs.
5. Half subtractor, full subtractor using ICs.
6. Construction and verification of truth table for Decoder/Encoder.
7. Multiplexer/De-multiplexer using multiplexer ICs.
8. Parity generator and checker using parity checker/ generator ICs.
9. Construction and verification of truth table for RS, D, T & JK flip-flop.
10. 4- bit ripple counter using FF
11. Construct a Single digit Decade Counter with 7 segment display.
12. Astable Multi vibrator using IC 555.
13. Simulate the Clippers and clampers using the simulation tool like PSPICE/
multisim/orcad/tina.
14. simulate the inverting and non inverting amplifier, voltage follower, integrator, differentiator,
summing amplifier, difference amplifier(Any 3) using the simulation tool like PSPICE/
multisim/orcad/tina.
15. simulate the Hartley and phase shift oscillator, sine, square and triangular waveform
generators and precision rectifiers(Any 3) using the simulation tool like PSPICE/
multisim/orcad/tina.
Verification of truth table of OR, AND, NOT, NOR, NAND, EX-OR gates.
Realization of basic gates using NAND & NOR gates.
Realization of logic circuit for a given Boolean expression.
Half adder, Full adder using ICs.
Half subtractor, full subtractor using ICs.
Construction and verification of truth table for Decoder/Encoder.
Multiplexer/De-multiplexer using multiplexer ICs.
Parity generator and checker using parity checker/ generator ICs.
Construction and verification of truth table for RS, D, T & JK flip-flop.
4- bit ripple counter using FF
Construct a Single digit Decade Counter with 7 segment display.
Astable Multi vibrator using IC 555.
Simulate the Clippers and clampers using the simulation tool like PSPICE/
multisim/orcad/tina.
Simulate the inverting and non inverting amplifier, voltage follower, integrator,
differentiator, summing amplifier, difference amplifier(Any 3) using the simulation
tool like PSPICE/ multisim/orcad/tina.
Simulate the Hartley and phase shift oscillator, sine, square and triangular
waveform generators and precision rectifiers(Any 3) using the simulation tool like
PSPICE/ multisim/orcad/tina.
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: ADVANCED COMMUNICATION SYSTEM PRACTICAL SEMESTER :V
DATE: 11/10/2017 TIME: 10 A.M TO 1P.M
SUBJECT CODE:34055
TIME TABLE
BATCHES REGISTRATION NUMBER NO. OF STUDENTS
16404628,
BATCH I 16404631-16404635,16404638- 22
16404645,16404653,16404657-
16404660,16404664,16404666,
16409686
(VASANDRA DEVI .V) (BABU ASHOK.R)
INTERNAL EXAMINER CHIEF SUPERINTENDENT
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: INTEGRATED CIRCUITS PRACTICAL SEMESTER :IV
DATE: /10/2017 TIME:
SUBJECT CODE:34046
TIME TABLE
BATCHES REGISTRATION NUMBER NO. OF STUDENTS
BATCH I 16404644,16404659 2
(VASANDRA DEVI .V) (BABU ASHOK.R)
INTERNAL EXAMINER CHIEF SUPERINTENDENT
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: INTEGRATED CIRCUITS PRACTICAL SEMESTER :IV
DATE: /10/2017 TIME:
SUBJECT CODE:34046
ALLOCATION OF MARKS
CIRCUIT DIAGRAM : 20
CONNECTION : 25
EXECUTION & HANDLING OF EQUIPMENT : 15
OUTPUT/RESULT : 10
VIVA VOCE : 05
TOTAL : 75
INTERNAL EXAMINER EXTERNAL EXAMINER
(VASANDRA DEVI. V) (MAHALAKSHMI.N)
WOMENS POLYTECHNIC COLLEGE-KARAIKALMEDU-KARAIKAL-609 605
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
SUBJECT: INTEGRATED CIRCUITS PRACTICAL SEMESTER :IV
DATE: /10/2017 TIME:
SUBJECT CODE:34046
LIST OF EXPERIMENTS COMPLETED
1. Verification of truth table of OR, AND, NOT, NOR, NAND, EX-OR gates.
2. Realization of basic gates using NAND & NOR gates.
3. Realization of logic circuit for a given Boolean expression.
4. Half adder, Full adder using ICs.
5. Half subtractor, full subtractor using ICs.
6. Construction and verification of truth table for Decoder/Encoder.
7. Multiplexer/De-multiplexer using multiplexer ICs.
8. Parity generator and checker using parity checker/ generator ICs.
9. Construction and verification of truth table for RS, D, T & JK flip-flop.
10. 4- bit ripple counter using FF
11. Construct a Single digit Decade Counter with 7 segment display.
12. Astable Multi vibrator using IC 555.
13. Simulate the Clippers and clampers using the simulation tool like PSPICE/ multisim/orcad/tina.
14. simulate the inverting and non inverting amplifier, voltage follower, integrator, differentiator,
summing amplifier, difference amplifier(Any 3) using the simulation tool like PSPICE/
multisim/orcad/tina.
15. simulate the Hartley and phase shift oscillator, sine, square and triangular waveform generators and
precision rectifiers(Any 3) using the simulation tool like PSPICE/ multisim/orcad/tina.
INTERNAL EXAMINER EXTERNAL EXAMINER
(VASANDRA DEVI .V) (MAHALAKSHMI.N)
SYLLABUS
34046 - INTEGRATED CIRCUITS PRACTICAL
List of experiments
Note: At least 5 experiments should be constructed using breadboard
1. Verification of truth table of OR, AND, NOT, NOR, NAND, EX-OR gates.
2. Realization of basic gates using NAND & NOR gates.
3. Realization of logic circuit for a given Boolean expression.
4. Half adder, Full adder using ICs.
5. Half subtractor, full subtractor using ICs.
6. Construction and verification of truth table for Decoder/Encoder.
7. Multiplexer/De-multiplexer using multiplexer ICs.
8. Parity generator and checker using parity checker/ generator ICs.
9. Construction and verification of truth table for RS, D, T & JK flip-flop.
10. 4- bit ripple counter using FF
11. Construct a Single digit Decade Counter with 7 segment display.
12. Astable Multi vibrator using IC 555.
13. Simulate the Clippers and clampers using the simulation tool like PSPICE/
multisim/orcad/tina.
14. simulate the inverting and non inverting amplifier, voltage follower, integrator, differentiator,
summing amplifier, difference amplifier(Any 3) using the simulation tool like PSPICE/
multisim/orcad/tina.
15. simulate the Hartley and phase shift oscillator, sine, square and triangular waveform
generators and precision rectifiers(Any 3) using the simulation tool like PSPICE/
multisim/orcad/tina.
Verification of truth table of OR, AND, NOT, NOR, NAND, EX-OR gates.
Realization of basic gates using NAND & NOR gates.
Realization of logic circuit for a given Boolean expression.
Half adder, Full adder using ICs.
Half subtractor, full subtractor using ICs.
Construction and verification of truth table for Decoder/Encoder.
Multiplexer/De-multiplexer using multiplexer ICs.
Parity generator and checker using parity checker/ generator ICs.
Construction and verification of truth table for RS, D, T & JK flip-flop.
4- bit ripple counter using FF
Construct a Single digit Decade Counter with 7 segment display.
Astable Multi vibrator using IC 555.
Simulate the Clippers and clampers using the simulation tool like PSPICE/
multisim/orcad/tina.
Simulate the inverting and non inverting amplifier, voltage follower, integrator,
differentiator, summing amplifier, difference amplifier(Any 3) using the simulation
tool like PSPICE/ multisim/orcad/tina.
Simulate the Hartley and phase shift oscillator, sine, square and triangular
waveform generators and precision rectifiers(Any 3) using the simulation tool like
PSPICE/ multisim/orcad/tina.