Dr.
Madhu Mutyam
Assistant Professor
Computer Architecture and Systems Laboratory
Department of Computer Science and Engineering
Indian Institute of Technology, Madras
madhu@[Link]
[Link]
Three registers, R1, R2, and R3
Swap the contents of R1 and R2
T1: R3 [R2]
T2: R2 [R1]
T3: R1 [R3]
Control signals:
T1: R2out, R3in
T2: R1out, R2in
T3: R3out, R1in
Control signals:
T1 T2 T3
1 0 0
0 1 0
0 0 1
module regn(R, Rin, Clk, Q); module shiftr(Resetn, w, Clk, Q);
parameter n = 8; parameter m = 4;
input [n-1:0] R; input Resetn, w, Clk;
input Rin, Clk; output reg [1:m] Q;
output reg [n-1:0] Q; integer k;
always @(posedge Clk) always @(negedge Resetn, posedge Clk)
if (Rin) if (!Resetn)
Q <= R; Q <= 0;
endmodule else
begin
module trin(Y, E, F); for(k = m; k > 1; k = k-1)
parameter n = 8; Q[k] <= Q[k-1];
input [n-1:0] Y; Q[1] <= w;
input E; end
output wire [n-1:0] F; endmodule
assign F = E? Y : ‘bz;
endmodule
module swap(Data, Resetn, w, Clk, Extern, RinExt, BusWires);
input Resetn, w, Clk, Extern;
input [7:0] Data;
input [1:3] RinExt;
output tri [7:0] BusWires;
wire [1:3] Rin, Rout, Q;
wire [7:0] R1, R2, R3;
shiftr control(Resetn, w, Clk, Q);
defparam control.m = 3;
regn reg_1(BusWires, Rin[1], Clk, R1);
assign Rin[1] = RinExt[1] | Q[3]; regn reg_2(BusWires, Rin[2], Clk, R2);
assign Rin[2] = RinExt[2] | Q[2]; regn reg_3(BusWires, Rin[3], Clk, R3);
assign Rin[3] = RinExt[3] | Q[1];
assign Rout[1] = Q[2]; trin tri_ext(Data, Extern, BusWires);
assign Rout[2] = Q[1]; trin tri_1(R1, Rout[1], BusWires);
assign Rout[3] = Q[3]; trin tri_2(R2, Rout[2], BusWires);
trin tri_3(R3, Rout[3], BusWires);
endmodule
Designa simple processor, with four
registers and an ALU, that performs the
following operations:
Operation Function performed
Load Rx, Data Rx Data
Move Rx, Ry Rx [Ry]
Add Rx, Ry Rx [Rx] + [Ry]
Sub Rx, Ry Rx [Rx] – [Ry]
Data
Bus
R0 R3 A B
Clk
G
Data
Bus
R0 R3 A B
Clk
R0in R0out R3in R3out Ain G
Gout
w AddSub
Control unit Gin
Instruction
Extern
Done
Load and Move require one clock cycle.
Add and Sub require three clock cycles:
◦ A [Rx]
◦ Bus [Ry]; Perform Add/Sub; Result is
stored in G
◦ Rx [G]
T0 T1 T2 T3
T0 No operation
T1 1st step of an y0 y1 y2 y3
operation
2-to-4 decoder
T2 2nd step of an w1 w0 En
operation
T3 3rd step of an 1
operation
Q1 Q0
Clk
Up-counter
Clear Reset
I0 I1 I2 I3 X0 X1 X2 X3 Y0 Y1 Y2 Y3
y0 y1 y2 y3 y0 y1 y2 y3 y0 y1 y2 y3
2-to-4 decoder 2-to-4 decoder 2-to-4 decoder
w1 w0 En w1 w0 En w1 w0 En
1 1 1
Clk
IRin Instruction Register (IR) I0 Load
I1 Move
f1 f0 Rx1 Rx0 Ry1 Ry0 I2 Add
I3 Sub
Instruction
Clear = (~w)T0 + Done
IRin = wT0
T1 T2 T3
Extern, Rin = X,
(Load): I0
Done
Rin = X, Rout = Y,
(Move): I1
Done
(Add): I2 Rout = X, Ain Rout = Y, Gin, Gout, Rin = X,
AddSub = 0 Done
(Sub): I3 Rout = X, Ain Rout = Y, Gin, Gout, Rin = X,
AddSub = 1 Done
Extern = I0T1
Done = (I0 + I1)T1 + (I2 + I3)T3
Ain = (I2 + I3)T1
Gin = (I2 + I3)T2
Gout = (I2 + I3)T3
AddSub = I3
R0in = (I0 + I1)T1X0 + (I2 + I3)T3X0
R0out = I1T1Y0 + (I2 + I3)(T1X0 + T2Y0)
R1in, R2in, R3in, R1out, R2out, and R3out are derived in the
same way.
Timing constructs are ignored.
initial construct is not supported.
◦ Use reset mechanism to initialize signals in the circuit.
For sequential logic, the always statement must
contain @(posedge clk) or @(negedge clk).
For combinational logic, the always statement must be
triggered by a signal other than the clk, reset, or preset.
Specify all signal widths and variable widths explicitly.
while and forever loops must contain @(posedge clk)
or @(negedge clk).
Thank You