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Universal Shift Register Overview

The universal shift register uses multiplexers and flip-flops to allow data to be shifted in any direction (left or right) and loaded in parallel. It consists of n 4x1 multiplexers connected to n flip-flops. The multiplexers' select lines determine the operating mode and their inputs are connected to either the output of the same, previous, or next flip-flop or an input data bit to allow shifting or parallel loading. This design allows flexible data input/output in any mode.

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Sam Sepiol
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10 views5 pages

Universal Shift Register Overview

The universal shift register uses multiplexers and flip-flops to allow data to be shifted in any direction (left or right) and loaded in parallel. It consists of n 4x1 multiplexers connected to n flip-flops. The multiplexers' select lines determine the operating mode and their inputs are connected to either the output of the same, previous, or next flip-flop or an input data bit to allow shifting or parallel loading. This design allows flexible data input/output in any mode.

Uploaded by

Sam Sepiol
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as ODT, PDF, TXT or read online on Scribd

1.

Universal Shift Register


Universal Shift Register is a register which can be configured to load and/or retrieve the data in
any mode (either serial or parallel) by shifting it either towards right or towards left. In other
words, a combined design of unidirectional (either right- or left-shift of data bits as in case of
SISO, SIPO, PISO, PIPO) and bidirectional shift register along with parallel load provision is
referred to as universal shift register. Such a shift register capable of storing n input bits is
shown by Figure 1.

The design shown by Figure 1 uses n 41 multiplexers to drive the input pins of n flip-flops in
the register which are also connected to clock and clear inputs. All of the multiplexers in the
circuit share the same select lines, S1 and S0 (pink lines in the figure), in order to select the
mode in which the shift registers operates. It is also seen that the MUX driving a particular flip-
flop has its

1. First input (Pin Number 0) connected to the output pin of the same flip-flop i.e. zeroth pin
of MUX1 is connected to Q1, zeroth pin of MUX2 is connected to Q2, zeroth pin of
MUXn is connected to Qn.
2. Second input (Pin Number 1) connected to the output of the very-previous flip-flop
(except the first flip-flop FF1 where it acts like an serial-input to the input data bits which
are to be shifted towards right) i.e. first pin of MUX2 is connected to Q1, first pin of MUX3
is connected to Q2, first pin of MUXn is connected to Qn-1.
3. Third input (Pin Number 2) connected to the output of the very-next flip-flop (except the
first flip-flop FFn where it acts like an serial-input to the input data bits which are to be
shifted towards left) i.e. second pin of MUX1 is connected to Q2, second pin of MUX2 is
connected to Q3, second pin of MUXn-1 is connected to Qn.
4. Fourth input (Pin Number 3) connected to the individual bits of the input data word which
is to be stored into the register, thus providing the facility for parallel loading.
2. Different types of Counters
A. Asynchronous Counters
This type of counters have JK Flop-Flops arranged in a way that the output of one flip-
flip feeds the clock of the following flip-flop [1] as shown in the figure below:
B. Synchronous Counters
This type of counters has each flip-flop clocked by the same clock source, thus eliminating the
cumulative delay found in asynchronous counters

Reference:
[1] [Link]
[2] [Link]/universal-shift-register/

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