David Money Harris and Sarah L.

Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 11

CHAPTER 2

Exercise 2.1

(a) Y = AB + AB + AB
(b) Y = ABC + ABC
(c) Y = ABC + ABC + ABC + ABC + ABC
(d)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
(e)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD

Exercise 2.2

(a) Y = AB + AB + AB
(b) Y = ABC + ABC + ABC + ABC + ABC
(c) Y = ABC + ABC + ABC
(d) Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
(e) Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
Exercise 2.3

(a) Y = A + B
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

12 SOLUTIONS chapter 2

(b)
Y = A + B + C A + B + C A + B + C A + B + C A + B + C A + B + C
(c) Y = A + B + C A + B + C A + B + C
(d)
Y = A + B + C + DA + B + C + DA + B + C + DA + B + C + DA + B + C + D
A + B + C + D A + B + C + D A + B + C + DA + B + C + D
(e)
Y = A + B + C + DA + B + C + DA + B + C + DA + B + C + DA + B + C + D
A + B + C + D A + B + C + DA + B + C + D

Exercise 2.4

(a) Y = A + B
(b) Y = A + B + C A + B + C A + B + C
(c) Y = A + B + C A + B + C A + B + C A + B + C A + B + C
(d)
Y = A + B + C + DA + B + C + DA + B + C + D A + B + C + D
A + B + C + DA + B + C + D A + B + C + D A + B + C + D
A + B + C + D
(e)
Y = A + B + C + DA + B + C + DA + B + C + D A + B + C + D
A + B + C + DA + B + C + D A + B + C + D A + B + C + D
A + B + C + D

Exercise 2.5

(a) Y = A + B
(b) Y = ABC + ABC
(c) Y = AC + AB + AC
(d) Y = AB + BD + ACD
(e)
Y = ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD + ABCD
This can also be expressed as:
Y = A BC D + A B C D

Exercise 2.6
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 13

(a) Y = A + B
(b) Y = AC + AC + BC or Y = AC + AC + AB
(c) Y = AB + ABC
(d) Y = BC + BD
(e) Y = AB + ABC + ACD or Y = AB + ABC + BCD
Exercise 2.7

(a)

A
Y
B

(b)

A
B
C
Y

(c)

A
C
Y

(d)

A B C D

Y
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

14 SOLUTIONS chapter 2

(e)

A
B
Y
C
D

Exercise 2.8

A
B Y
(a)

A C

Y or Y
C A
B B
(b)

Y
B
C
(c)

Y
B
D
(d)
ABCD ABCD

Y Y

or
(e)

Exercise 2.9
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 15

(a) Same as 2.7(a)

(b)

A
B
C
Y

(c)

A B C

(d)

A B C D

Y
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

16 SOLUTIONS chapter 2

(e)

A B C D

Exercise 2.10
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 17

A
B Y
(a)

A B C A B C

Y or Y

(b)
A B C

(c)

Y
B
D
(d)
ABCD

(e)

Exercise 2.11

(a)

A
Y
B
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

18 SOLUTIONS chapter 2

(b)

B Y
C

(c)

A
C
Y

(d)

A
B
Y

(e)

A
B
Y

C
D

Exercise 2.12
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 19

A
Y
B
(a)

A B C

(b)
A B C

(c)

Y
B
D
(d)
ABCD

(e)

Exercise 2.13

(a) Y = AC + BC
(b) Y = A
(c) Y = A + B C + B D + BD

Exercise 2.14

(a) Y = AB
(b) Y = A + B + C = ABC
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

20 SOLUTIONS chapter 2

(c) Y = A B + C + D + BCD = ABCD + BCD

Exercise 2.15

(a)

A
B Y
C

(b)

A Y

(c)

B
Y
D

Exercise 2.16

A
Y
B
(a)
A
B Y
C
(b)
ABCD

(c)

Exercise 2.17
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 21

(a) Y = B + AC

B
A Y
C

(b) Y = AB

A
Y
B

(c) Y = A + BC + DE

A B CD E

Exercise 2.18

(a) Y = B + C
(b) Y = A + C D + B
(c) Y = BDE + BD A C
Exercise 2.19

4 gigarows = 4 x 230 rows = 232 rows, so the truth table has 32 inputs.

Exercise 2.20
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

22 SOLUTIONS chapter 2

A
Y
B

Y=A

Exercise 2.21

Ben is correct. For example, the following function, shown as a K-map, has
two possible minimal sum-of-products expressions. Thus, although ACD and
BCD are both prime implicants, the minimal sum-of-products expression does
not have both of them.

Y Y
AB AB
00 01 11 10 00 01 11 10 BCD
CD ACD CD

00 1 0 1 1 00 1 0 1 1

ABD ABD
01 0 0 1 0 01 0 0 1 0
ABC ABC

11 0 0 0 0 11 0 0 0 0

10 1 0 0 0 10 1 0 0 0

Y = ABD + ABC + ACD Y = ABD + ABC + BCD

Exercise 2.22

(a)

B B B
0 0
1 1
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 23

(b)

B C D (B C) + (B D) B (C + D)
0 0 0 0 0
0 0 1 0 0
0 1 0 0 0
0 1 1 0 0
1 0 0 0 0
1 0 1 1 1
1 1 0 1 1
1 1 1 1 1

(c)

B C (B C) + (B C)
0 0 0
0 1 0
1 0 1
1 1 1

Exercise 2.23

B2 B1 B0 B2 B1 B0 B2 + B1 + B0
0 0 0 1 1
0 0 1 1 1
0 1 0 1 1
0 1 1 1 1
1 0 0 1 1
1 0 1 1 1
1 1 0 1 1
1 1 1 0 0

Exercise 2.24

Y = AD + ABC + ACD + ABCD

Z = ACD + BD

Exercise 2.25
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

24 SOLUTIONS chapter 2

Y Z
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 0 0 0 0 00 0 0 1 0
D ACD

01 1 1 1 1 01 0 1 1 1
ABC

11 1 1 1 1 11 0 1 1 0
BD

10 0 0 0 1 10 0 0 0 0

Y = ABC + D Z = ACD + BD

A B C D

Y Z

Exercise 2.26

A
B
C
D
Y
E

Y = (A + B)(C + D) + E
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 25

Exercise 2.27

A
B
C
D
Y
E
F
G

Y = ABC + D + (F + G)E
= ABC + D + EF + EG

Exercise 2.28

Two possible options are shown below:

Y Y
AB AB
CD 00 01 11 10 CD 00 01 11 10

00 X 0 1 1 00 X 0 1 1

01 X X 1 0 01 X X 1 0

11 0 X 1 1 11 0 X 1 1

10 X 0 X X 10 X 0 X X

(a) Y = AD + AC + BD (b) Y = A(B + C + D)

Exercise 2.29
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

26 SOLUTIONS chapter 2

Two possible options are shown below:

C
A

Y A
D
B Y
C
B D
(a) (b)

Exercise 2.30

Option (a) could have a glitch when A=1, B=1, C=0, and D transitions from
1 to 0. The glitch could be removed by instead using the circuit in option (b).
Option (b) does not have a glitch. Only one path exists from any given input
to the output.

Exercise 2.31

Y = AD + ABCD + BD + CD = ABCD + D A + B + C

Exercise 2.32

ABCD

Exercise 2.33

The equation can be written directly from the description:

E = SA + AL + H
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 27

Exercise 2.34

(a)

Sc Sd
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 1 0 1 00 1 0 0 1

01 1 1 0 1 01 0 1 0 0

11 1 1 0 0 11 1 0 0 0

10 0 1 0 0 10 1 1 0 0

Sc = D3D0 + D3D2 + D2D1 Sd = D3D1D0 + D3D2D1 +

D2D1D0 + D3D2D1D0
Se Sf
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 0 0 1 00 1 1 0 1

01 0 0 0 0 01 0 1 0 1

11 0 0 0 0 11 0 0 0 0

10 1 1 0 0 10 0 1 0 0

Se = D2D1D0 + D3D1D0 Sf = D3D1D0 + D3D2D1+ D3D2D0 + D3D2D1

David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

28 SOLUTIONS chapter 2

Sg
D3:2
D1:0 00 01 11 10

00 0 1 0 1

01 0 1 0 1

11 1 0 0 0

10 1 1 0 0

Sg = D3D2D1 + D3D1D0+ D3D2D1 + D3D2D1

 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 29

(b)

Sa Sb
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 0 X 1 00 1 1 X 1

01 0 1 X 1 01 1 0 X 1

11 1 1 X X 11 1 1 X X

10 0 1 X X 10 1 0 X X

Sa = D2D1D0 + D2D0 + D3 + D2D1 + D1D0 Sb = D1D0 + D1D0 + D2

Sc Sd
D3:2 D3:2
D1:0 00 01 = D D 11
S 10 + D + D
D + D2D D1:0 00 01 11 10
a 2 1 0 0 3 1

00 1 1 X 1 00 1 0 X 1

01 1 1 X 1 01 0 1 X 0

11 1 1 X X 11 1 0 X X

10 0 1 X X 10 1 1 X X

Sc = D1 + D0 + D2 Sd = D2D1D0 + D2D0+ D2D1 + D1D0

David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

30 SOLUTIONS chapter 2

Se Sf
D3:2 D3:2
D1:0 00 01 11 10 D1:0 00 01 11 10

00 1 0 X 1 00 1 1 X 1

01 0 0 X 0 01 0 1 X 1

11 0 0 X X 11 0 0 X X

10 1 1 X X 10 0 1 X X

Se = D2D0 + D1D0 Sf = D1D0 + D2D1+ D2D0 + D3

Sg
D3:2
D1:0 00 01 11 10

00 0 1 X 1

01 0 1 X 1

11 1 0 X X

10 1 1 X X

Sg = D2D1 + D2D0+ D2D1 + D3

 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 31

(c)
D3 D2 D1 D0

Sa Sb Sc Sd Se Sf Sg

Exercise 2.35
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

32 SOLUTIONS chapter 2

Decimal
Value A3 A2 A1 A0 D P
0 0 0 0 0 0 0
1 0 0 0 1 0 0
2 0 0 1 0 0 1
3 0 0 1 1 1 1
4 0 1 0 0 0 0
5 0 1 0 1 0 1
6 0 1 1 0 1 0
7 0 1 1 1 0 1
8 1 0 0 0 0 0
9 1 0 0 1 1 0
10 1 0 1 0 0 0
11 1 0 1 1 0 1
12 1 1 0 0 1 0
13 1 1 0 1 0 1
14 1 1 1 0 0 0
15 1 1 1 1 1 0

P has two possible minimal solutions:

D P
A3:2 A3:2
A1:0 00 01 11 10 A1:0 00 01 11 10

00 0 0 1 0 00 0 0 0 0

01 0 0 0 1 01 0 1 1 0

11 1 0 1 0 11 1 1 0 1

10 0 1 0 0 10 1 0 0 0

D = A3A2A1A0 + A3A2A1A0 + A3A2A1A0 P = A3A2A0 + A3A1A0 + A3A2A1

+ A3A2A1A0 + A3A2A1A0 + A2A1A0
P = A3A1A0 + A3A2A1 + A2A1A0
+ A2A1A0

Hardware implementations are below (implementing the first minimal

equation given for P).
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 33

A3 A2 A1 A0

Exercise 2.36

A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0 NONE
0 0 0 0 0 0 0 0 0 0 0 1
0 0 0 0 0 0 0 1 0 0 0 0
0 0 0 0 0 0 1 X 0 0 1 0
0 0 0 0 0 1 X X 0 1 0 0
0 0 0 0 1 X X X 0 1 1 0
0 0 0 1 X X X X 1 0 0 0
0 0 1 X X X X X 1 0 1 0
0 1 X X X X X X 1 1 0 0
1 X X X X X X X 1 1 1 0

Y2 = A7 + A6 + A5 + A4

Y1 = A7 + A6 + A5 A4 A3 + A5 A4 A2

Y0 = A7 + A6 A5 + A6 A4 A3 + A6 A4 A 2 A1

NONE = A 7 A 6 A 5 A 4 A 3 A 2 A 1 A 0
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

34 SOLUTIONS chapter 2

A7 A6 A5 A4 A3 A2 A1 A0

Y2

Y1

Y0

NONE

Exercise 2.37

The equations and circuit for Y2:0 is the same as in Exercise 2.25, repeated
here for convenience.
A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1

Y2 = A7 + A6 + A5 + A4

Y1 = A7 + A6 + A5 A4 A3 + A5 A4 A2

Y0 = A7 + A6 A5 + A6 A4 A3 + A6 A4 A2 A1
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 35

A7 A6 A5 A4 A3 A2 A1 A0

Y2

Y1

Y0

NONE
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

36 SOLUTIONS chapter 2

The truth table, equations, and circuit for Z2:0 are as follows.

A7 A6 A5 A4 A3 A2 A1 A0 Z2 Z1 Z0
0 0 0 0 0 0 1 1 0 0 0
0 0 0 0 0 1 0 1 0 0 0
0 0 0 0 1 0 0 1 0 0 0
0 0 0 1 0 0 0 1 0 0 0
0 0 1 0 0 0 0 1 0 0 0
0 1 0 0 0 0 0 1 0 0 0
1 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 1 1 X 0 0 1
0 0 0 0 1 0 1 X 0 0 1
0 0 0 1 0 0 1 X 0 0 1
0 0 1 0 0 0 1 X 0 0 1
0 1 0 0 0 0 1 X 0 0 1
1 0 0 0 0 0 1 X 0 0 1
0 0 0 0 1 1 X X 0 1 0
0 0 0 1 0 1 X X 0 1 0
0 0 1 0 0 1 X X 0 1 0
0 1 0 0 0 1 X X 0 1 0
1 0 0 0 0 1 X X 0 1 0
0 0 0 1 1 X X X 0 1 1
0 0 1 0 1 X X X 0 1 1
0 1 0 0 1 X X X 0 1 1
1 0 0 0 1 X X X 0 1 1
0 0 1 1 X X X X 1 0 0
0 1 0 1 X X X X 1 0 0
1 0 0 1 X X X X 1 0 0
0 1 1 X X X X X 1 0 1
1 0 1 X X X X X 1 0 1
1 1 X X X X X X 1 1 0

Z2 = A4 A5 + A6 + A7 + A5 A6 + A7 + A6 A7

Z1 = A2 A3 + A4 + A5 + A6 + A7 +
A3 A4 + A5 + A6 + A7 + A6 A7

Z0 = A1 A2 + A3 + A4 + A5 + A6 + A7 +
A3 A4 + A5 + A6 + A7 + A5 A6 + A7
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 37

A7 A6 A5 A4 A3 A2 A1 A0

Z2

Z1

Z0

Exercise 2.38

Y6 = A2 A1 A0
Y5 = A2 A1
Y4 = A2 A1 + A2 A0
Y3 = A2
Y2 = A2 + A1 A0
Y1 = A2 + A1
Y0 = A2 + A1 + A0
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

38 SOLUTIONS chapter 2

A2 A1 A0

Y6

Y5

Y4

Y3
Y2

Y1

Y0

Exercise 2.39

Y = A + C D = A + CD + CD

Exercise 2.40

Y = CD A B + AB = ACD + BCD + AB

Exercise 2.41
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 39

A B C A B Y A Y
A B C Y 0 0 C 0 BC
0 0 0 1 000 0 1 0 1 BC
0 0 1 0 001 1 0 0
0 1 0 0 010 1 1 C
0 1 1 0 011 A
Y AB
1 0 0 0 100 B
1 0 1 0 101 C 00 C 0
1 1 0 0 110 01 Y
Y
1 1 1 1 111 10 1
11

(a) (b) (c)

Exercise 2.42

A B C A C Y A Y
A B C Y 0 0 1 0 B+C
0 0 0 1 000 0 1 B 1 B
0 0 1 0 001 1 0 B
0 1 0 1 010 1 1 B
0 1 1 1 011 A
Y AC
1 0 0 0 100
C
1 0 1 0 101 00 0
B
1 1 0 1 110 B 01 Y
Y
1 1 1 1 111 10 1
11

(a) (b) (c)

Exercise 2.43

tpd = 3tpd_NAND2 = 60 ps
tcd = tcd_NAND2 = 15 ps
Exercise 2.44

tpd = tpd_AND2 + 2tpd_NOR2 + tpd_NAND2

= [30 + 2 (30) + 20] ps
= 110 ps
tcd = 2tcd_NAND2 + tcd_NOR2
= [2 (15) + 25] ps
= 55 ps
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

40 SOLUTIONS chapter 2

Exercise 2.45

tpd = tpd_NOT + tpd_AND3

= 15 ps + 40 ps
= 55 ps
tcd = tcd_AND3
= 30 ps

A2 A1 A0

Y7

Y6

Y5

Y4

Y3

Y2

Y1

Y0

Exercise 2.46
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 41

A3 A2 A1 A0

tpd = tpd_NOR2 + tpd_AND3 + tpd_NOR3 + tpd_NAND2

= [30 + 40 + 45 + 20] ps
= 135 ps
tcd = 2tcd_NAND2 + tcd_OR2
= [2 (15) + 30] ps
= 60 ps

Exercise 2.47
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

42 SOLUTIONS chapter 2

A7 A6 A5 A4 A3 A2 A1 A0

Y2

Y1

Y0

NONE

tpd = tpd_INV + 3tpd_NAND2 + tpd_NAND3

= [15 + 3 (20) + 30] ps
= 105 ps
tcd = tcd_NOT + tcd_NAND2
= [10 + 15] ps
= 25 ps

Exercise 2.48
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 43

S2 S1 S0

D0

D1

D2

D3

D4

D5

D6

D7

tpd_dy = tpd_TRI_AY
= 50 ps

Note: the propagation delay from the control (select) input to the output is
the circuits critical path:
tpd_sy = tpd_NOT + tpd_AND3 + tpd_TRI_SY
= [30 + 80 + 35] ps
= 145 ps
However, the problem specified to minimize the delay from data inputs to
output, tpd_dy.
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

44 SOLUTIONS chapter 2

Question 2.1

A
Y
B

Question 2.2

Y
A3:2
A1:0 00 01 11 10
Month A3 A2 A1 A0 Y
Jan 0 0 0 1 1 00 X 0 1 1
Feb 0 0 1 0 0
Mar 0 0 1 1 1
Apr 0 1 0 0 0
01 1 1 X 0
May 0 1 0 1 1 A3
Jun 0 1 1 0 0 Y
A0
Jul 0 1 1 1 1
Aug 1 0 0 0 1 11 1 1 X 0
Sep 1 0 0 1 0
Oct 1 0 1 0 1
Nov 1 0 1 1 0
Dec 1 1 0 0 1 10 0 0 X 1

Y = A3A0 + A3A0 = A3 + A0

Question 2.3

A tristate buffer has two inputs and three possible outputs: 0, 1, and Z. One
of the inputs is the data input and the other input is a control input, often called
the enable input. When the enable input is 1, the tristate buffer transfers the data
input to the output; otherwise, the output is high impedance, Z. Tristate buffers
are used when multiple sources drive a single output at different times. One and
only one tristate buffer is enabled at any given time.
 David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2nd Edition 2012 by Elsevier Inc.
Exercise Solutions

SOLUTIONS 45

Question 2.4

(a) An AND gate is not universal, because it cannot perform inversion

(NOT).
(b) The set {OR, NOT} is universal. It can construct any Boolean function.
For example, an OR gate with NOT gates on all of its inputs and output per-
forms the AND operation. Thus, the set {OR, NOT} is equivalent to the set
{AND, OR, NOT} and is universal.
(c) The NAND gate by itself is universal. A NAND gate with its inputs tied
together performs the NOT operation. A NAND gate with a NOT gate on its
output performs AND. And a NAND gate with NOT gates on its inputs per-
forms OR. Thus, a NAND gate is equivalent to the set {AND, OR, NOT} and
is universal.

Question 2.5

A circuits contamination delay might be less than its propagation delay be-
cause the circuit may operate over a range of temperatures and supply voltages,
for example, 3-3.6 V for LVCMOS (low voltage CMOS) chips. As temperature
increases and voltage decreases, circuit delay increases. Also, the circuit may
have different paths (critical and short paths) from the input to the output. A gate
itself may have varying delays between different inputs and the output, affect-
ing the gates critical and short paths. For example, for a two-input NAND gate,
a HIGH to LOW transition requires two nMOS transistor delays, whereas a
LOW to HIGH transition requires a single pMOS transistor delay.
David Money Harris and Sarah L. Harris, Digital Design and Computer Architecture, 2007 by Elsevier Inc.
Exercise Solutions

46 SOLUTIONS chapter 2