ADVANCED DIGITAL SYSTEM DESIGN LAB
LIST OF EXPERIMENTS
1. Design and Simulation of Logic gates and verify it using test bench.
2. Design and Simulation of full adder circuit and verify it using test bench.
3. Design and Simulation of binary to gray code converter and verify it using test
bench.
4. Implementation of 4:1 multiplexer using VHDL.
5. Design and Simulation of De-Multiplexer and verify it using test bench.
6. Implementation of of 2 line to 4 line decoder.
7. Design and Simulation of 8:3 Priority Encoder and verify it using test bench.
8. Design and Simulation of D flip/flop and verify it using test bench.
9. Implementation of BCD to 7-Segment converter.
10. Design and Simulation of Arithmetic and Logical and verify it using test bench.
11. Design and Simulation of up-down counter and verify it using test bench
12. Design and Simulation of Barrel Shifter and verify it using test bench
13. Design and Simulation of Multiplier and verify it using test bench.
14. Design and Simulation of Mealy and Moore machine which will detect the
sequences 1101 and verify it using test bench.
15. Open End Practical-Mini Project
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 1
ADVANCED DIGITAL SYSTEM DESIGN LAB
Aim: KNOW YOUR LAB ADSD.
TUTORIAL
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 2
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 1
Aim: Design and Simulation of all Logic gates and verify it using
test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 3
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: - Design and Simulation of all Logic gates and verify it using test bench.
OBJECTIVE:
To verify the functionality of all Logic gates.
To develop a logic for designing of all Logic gates.
EXPECTED LEARNING OUTCOME
Student will adopt the knowledge to design the digital System.
SOFTWARE: - A computer system with Xilinx ISE9.1.
AND gate
Input 1 Input 2 Output
0 0 0
0 1 0
1 0 0
1 1 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 4
ADVANCED DIGITAL SYSTEM DESIGN LAB
OR GATE
Input 1 Input 2 Output
0 0 0
0 1 1
1 0 1
1 1 1
EXCLUSIVE-OR GATE
XOR gate
Input 1 Input 2 Output
0 0 0
0 1 1
1 0 1
1 1 0
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 5
ADVANCED DIGITAL SYSTEM DESIGN LAB
NOT GATE
Inverter or NOT gate
Input Output
1 0
0 1
NAND GATE
NAND gate
Input 1 Input 2 Output
0 0 1
0 1 1
1 0 1
1 1 0
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 6
ADVANCED DIGITAL SYSTEM DESIGN LAB
NOR GATE
NOR gate
Input 1 Input 2 Output
0 0 1
0 1 0
1 0 0
1 1 0
XNOR GATE
XNOR gate
Input 1 Input 2 Output
0 0 1
0 1 0
1 0 0
1 1 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 7
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 2
Aim: Design and Simulation of full adder circuit and verify it
using test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 8
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: - Design and Simulation of full adder circuit and verify it using Test bench.
OBJECTIVE
To verify the functionality of full adder circuit.
To develop a logic for designing of full adder circuit.
EXPECTED LEARNING OUTCOME:
Student will perceive the designing of ALU Using Full adder.
SOFTWARE: - A computer system with Xilinx ISE9.1.
LOGICAL DIAGRAM:-
A ENTITY Sum
B FULL ADDER
Cin Cout
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 9
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:-
A B Cin SUM Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 10
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 3
Aim: Design and Simulation of binary to gray code Converter and
verify it using test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 11
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: - Design and Simulation of binary to gray code converter and verify it using Test
Bench.
OBJECTIVE
To verify the functionality of binary to gray code converter.
To develop a logic for designing of binary to gray code converter.
EXPECTED LEARNING OUTCOME:
Student will perceive the designing of encoder and decoder and its applications
using binary to gray code converter.
SOFTWARE: - A computer system with Xilinx ISE9.1.
LOGICAL DIAGRAM:-
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 12
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:-
BINARY GRAY
Sr. No.
B3 B2 B1 B0 G3 G2 G1 G0
01 0 0 0 0 0 0 0 0
02 0 0 0 1 0 0 0 1
03 0 0 1 0 0 0 1 1
04 0 0 1 1 0 0 1 0
05 0 1 0 0 0 1 1 0
06 0 1 0 1 0 1 1 1
07 0 1 1 0 0 1 0 1
08 0 1 1 1 1 1 0 0
09 1 0 0 0 1 1 0 0
10 1 0 0 1 1 1 0 1
12 1 0 1 0 1 1 1 1
13 1 0 1 1 1 1 1 0
14 1 1 0 0 1 0 1 0
15 1 1 0 1 1 0 1 1
16 1 1 1 0 1 0 0 1
17 1 1 1 1 1 0 0 0
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 13
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 4
Aim: Implementation of 4:1 multiplexer using VHDL.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 14
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Implementation of 4:1 multiplexer using VHDL.
OBJECTIVE
To verify the functionality of 4:1 multiplexer.
To develop a logic for designing of 4:1 multiplexer.
EXPECTED LEARNING OUTCOME:
Student will be able to design the digital System like Communication system,
Telephone network, Computer memory, Transmission from the computer system
of a satellite using 4:1 mux.
SOFTWARE: - A computer system with Quartus-II.
TRUTH TABLE:-
INPUT OUTPUT
S0 S1 Z
0 0 I(0)
0 1 I(1)
1 0 I(2)
1 1 I(3)
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 15
ADVANCED DIGITAL SYSTEM DESIGN LAB
LOGICAL DIAGRAM:-
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 16
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 5
Aim: Design and Simulation of De-Multiplexer and verify it using
test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 17
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Design and Simulation of 1:4 De-multiplexers and verify it using test bench.
OBJECTIVE
To verify the functionality of 1: 4 De-Multiplexer.
To develop a logic for designing of 1: 4 De-Multiplexer.
EXPECTED LEARNING OUTCOME:
Student will be able to design the digital System Communication system,
Telephone network, Computer memory, Transmission from the computer system
of a satellite.
SOFTWARE: - A computer system with Xilinx ISE9.1.
LOGICAL DIAGRAM:-
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 18
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:-
SELECT LINES OUTPUT
S1 Z
S2 Z1 Z2 Z3
0 0 I 0 0 0
0 1 0 I 0 0
1 0 0 0 I 0
1 1 0 0 0 I
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 19
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 6
Aim: Implementation of 2 line to 4 line decoder.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 20
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: - Implementation of 2 line to 4 line decoder.
OBJECTIVE
To verify the functionality of 2 line to 4 line decoder.
To develop a logic for designing of 2 line to 4 line decoder.
EXPECTED LEARNING OUTCOME:
Student will be able to model the digital System like communication
telecommunication switches, using decoder.
SOFTWARE: - A computer system with Quartus-II.
TRUTH TABLE:-
ENABLE INPUTS OUTPUTS
En W1 W2 X1 X2 X3 X4
1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 21
ADVANCED DIGITAL SYSTEM DESIGN LAB
LOGICAL DIAGRAM:-
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 22
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 7
Aim: Design and Simulation of 8:3 Priority Encoder and
verify it using test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 23
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Design and Simulation of 8:3 Priority Encoder and verify it using test bench.
OBJECTIVE
To verify the functionality of 8:3 Priority Encoder.
To develop a logic for designing of 8:3 Priority Encoder.
EXPECTED LEARNING OUTCOME:
Student will be able to model the different applications of priority encoder in
digital System.
SOFTWARE: - A computer system with Xilinx ISE9.1
Lowest Priority Output
a(0)
a(1) y(0)
a(2) 8:3
a(3) Priority y(1)
a(4) Encoder
a(5) y(2)
a(6)
a(7)
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 24
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:-
Digital Inputs Binary Outputs
A7 A6 A5 A4 A3 A2 A1 A0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0
0 0 0 0 0 0 1 X 0 0 1
0 0 0 0 0 1 X X 0 1 0
0 0 0 0 1 X X X 0 1 1
0 0 0 1 X X X X 1 0 0
0 0 1 X X X X X 1 0 1
0 1 X X X X X X 1 1 0
1 X X X X X X X 1 1 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 25
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 8
Aim: Design and Simulation of D flip/flop and verify it using test
bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 26
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Design and Simulation of VHDL Code for D flip/flop and verify it using test
bench.
OBJECTIVE:
To verify the functionality of D flip/flop.
To develop a logic for designing of D flip/flop.
EXPECTED LEARNING OUTCOME:
D flip-flop is used to design the digital System like memory designing.
SOFTWARE: - A computer system with Xilinx ISE9.1
TRUTH TABLE:
Qn Qn+1 D
0 0 0
0 1 1
1 0 0
1 1 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 27
ADVANCED DIGITAL SYSTEM DESIGN LAB
LOGICAL DIAGRAM:
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 28
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 9
Aim: Implementation of BCD to 7-Segment converter.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 29
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Implementation of BCD to 7-Segment converter
OBJECTIVE:
To verify the functionality of BCD to 7-Segment converter.
To develop a logic for designing of BCD to 7-Segment converter.
EXPECTED LEARNING OUTCOME:
BCD to 7-Segment converter is used to model the digital System like LCD
display.
SOFTWARE: - A computer system with Quartus-II.
Figure 8.1 Convention for Displaying Decimal Digits Figure 8.2 Seven-Segment
Numerical Display
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 30
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:
BCD 7-SEGMENT DISPLAY
B3 B2 B1 B0 A B C D E F G
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 1 1 1 1 1 1 0
0 0 1 1 1 1 0 1 1 0 1
0 0 1 0 1 1 1 1 0 0 1
0 1 1 0 0 0 1 0 0 1 1
0 1 1 1 1 0 1 1 0 1 1
0 1 0 1 0 0 1 1 1 1 1
1 1 0 0 1 1 1 0 0 0 0
1 1 0 0 1 1 1 1 1 1 1
1 1 0 1 1 1 1 0 0 1 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 31
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 10
Aim: Design and Simulation of Arithmetic and Logical Unit and
verify it using test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 32
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Design and Simulation of Arithmetic and Logical Unit and verify it using test
bench.
OBJECTIVE:
To verify the functionality of Arithmetic and Logical Unit.
To develop a logic for designing of Arithmetic and Logical Unit.
EXPECTED LEARNING OUTCOME:
Students will able to develop the logic of designing the digital calculator using
Arithmetic and Logical Unit.
SOFTWARE: - A computer system with Xilinx ISE9.1
TRUTH TABLE:
Select Lines
Operations
S2 S1 S0
0 0 0 CLEAR OUTPUT
0 0 1 A OR B
0 1 0 NOT B
0 1 1 A NOR B
1 0 0 A AND B
1 0 1 A NAND B
1 1 0 A XNOR B
1 1 1 A XOR B
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 33
ADVANCED DIGITAL SYSTEM DESIGN LAB
LOGICAL DIAGRAM:
a
ALU z
b 4
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 34
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 11
Aim: Design and Simulation of up-down counter and verify it
using test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 35
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: - Design and Simulation of up-down counter and verify it using test bench.
OBJECTIVE:
To verify the functionality of up-down counter.
To develop logic for designing of up-down counter.
EXPECTED LEARNING OUTCOME:
Students will able to develop the logic for designing of digital System like traffic
signals counter, watches using up-down counter.
SOFTWARE: - A computer system with Xilinx ISE9.1
LOGICAL DIAGRAM:-
updown
clk Up_Down q
clr
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 36
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:-
Q3 Q2 Q1 Q0 Up counter Down counter
0 0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 0 1 0 1 1 1 0
0 0 1 0 0 0 1 1 1 1 0 1
0 0 1 1 0 1 0 0 1 1 0 0
0 1 0 0 0 1 0 1 1 0 1 1
0 1 0 1 0 1 1 0 1 0 1 0
0 1 1 0 0 1 1 1 1 0 0 1
0 1 1 1 1 0 0 0 1 0 0 0
1 0 0 0 1 0 0 1 0 1 1 1
1 0 0 1 1 0 1 0 0 1 1 0
1 0 1 0 1 0 1 1 0 1 0 1
1 0 1 1 1 1 0 0 0 1 0 0
1 1 0 0 1 1 0 1 0 0 1 1
1 1 0 1 1 1 1 0 0 0 1 0
1 1 1 0 1 1 1 1 0 0 0 1
1 1 1 1 0 0 0 0 0 0 0 0
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 37
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 12
Aim: To design barrel shifter using VHDL and verify it using
test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 38
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Design and Simulation of barrel shifter using VHDL and verify it using test bench.
OBJECTIVE
To verify the functionality of barrel shifter.
To develop logic for designing of barrel shifter.
EXPECTED LEARNING OUTCOME:
Barrel shifter is used to design the digital System High speed ALU.
SOFTWARE: - A computer system with Xilinx ISE9.1
LOGIC DIAGRAM
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 39
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 40
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 13
Aim: To design different types of Multipliers using VHDL and
verify it using test bench.
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 41
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: Design and Simulation of different types of multiplier and verify it using test
bench.
OBJECTIVE
To verify the functionality of multiplier.
To develop logic for designing of multiplier.
EXPECTED LEARNING OUTCOME:
Student will be able to design the digital System like digital calculators.
SOFTWARE: - A computer system with Xilinx ISE9.1
LOGIC DIAGRAM
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 42
ADVANCED DIGITAL SYSTEM DESIGN LAB
EXPERIMENT NO 14.
Aim: Design a Mealy and Moore machine on FPGA which
detects the sequences 1101 and verify it using test bench
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 43
ADVANCED DIGITAL SYSTEM DESIGN LAB
AIM: - Design and Simulation of Mealy and Moore machine which will detect the
Sequences 1101 and verify it using Test Bench.
OBJECTIVE:
To verify the functionality of Melay and Moore machine which will detect the
sequences 1101
To develop logic for designing of Melay and Moore machine which will detect
the sequences 1101.
EXPECTED LEARNING OUTCOME:
Mealy and Moore Machine is used to design complex digital System like vending
machines, washing machines.
SOFTWARE: - A computer system with Xilinx ISE9.1
LOGICAL DIAGRAM:-
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 44
ADVANCED DIGITAL SYSTEM DESIGN LAB
TRUTH TABLE:-
Input
Present State Next state, Output Next state, Output
Input x=0 Input x=1
S1 S1, 0 S2 , 0
S2 S1, 0 S3, 0
S3 S4, 0 S3, 0
S4 S1, 0 S2, 1
Department of Electronics and Telecommunication Engineering J.D.C.O.E.M., Nagpur Page 45
